2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
28 #include <linux/i2c.h>
29 #include <linux/delay.h>
33 #include "intel_drv.h"
36 #include "intel_sdvo_regs.h"
40 struct intel_sdvo_priv
{
41 struct intel_i2c_chan
*i2c_bus
;
47 struct intel_sdvo_caps caps
;
48 int pixel_clock_min
, pixel_clock_max
;
51 u16 save_active_outputs
;
52 struct intel_sdvo_dtd save_input_dtd_1
, save_input_dtd_2
;
53 struct intel_sdvo_dtd save_output_dtd
[16];
58 * Writes the SDVOB or SDVOC with the given value, but always writes both
59 * SDVOB and SDVOC to work around apparent hardware issues (according to
60 * comments in the BIOS).
62 static void intel_sdvo_write_sdvox(struct intel_output
*intel_output
, u32 val
)
64 struct drm_device
*dev
= intel_output
->base
.dev
;
65 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
66 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
67 u32 bval
= val
, cval
= val
;
70 if (sdvo_priv
->output_device
== SDVOB
) {
71 cval
= I915_READ(SDVOC
);
73 bval
= I915_READ(SDVOB
);
76 * Write the registers twice for luck. Sometimes,
77 * writing them only once doesn't appear to 'stick'.
78 * The BIOS does this too. Yay, magic
80 for (i
= 0; i
< 2; i
++)
82 I915_WRITE(SDVOB
, bval
);
84 I915_WRITE(SDVOC
, cval
);
89 static bool intel_sdvo_read_byte(struct intel_output
*intel_output
, u8 addr
,
92 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
97 struct i2c_msg msgs
[] = {
99 .addr
= sdvo_priv
->i2c_bus
->slave_addr
,
105 .addr
= sdvo_priv
->i2c_bus
->slave_addr
,
115 if ((ret
= i2c_transfer(&sdvo_priv
->i2c_bus
->adapter
, msgs
, 2)) == 2)
121 DRM_DEBUG("i2c transfer returned %d\n", ret
);
125 static bool intel_sdvo_write_byte(struct intel_output
*intel_output
, int addr
,
129 struct i2c_msg msgs
[] = {
131 .addr
= intel_output
->i2c_bus
->slave_addr
,
141 if (i2c_transfer(&intel_output
->i2c_bus
->adapter
, msgs
, 1) == 1)
148 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
149 /** Mapping of command numbers to names, for debug output */
150 const static struct _sdvo_cmd_name
{
153 } sdvo_cmd_names
[] = {
154 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET
),
155 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS
),
156 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV
),
157 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS
),
158 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS
),
159 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS
),
160 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP
),
161 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP
),
162 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS
),
163 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT
),
164 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG
),
165 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG
),
166 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE
),
167 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT
),
168 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT
),
169 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1
),
170 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2
),
171 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1
),
172 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2
),
173 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1
),
174 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1
),
175 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2
),
176 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1
),
177 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2
),
178 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING
),
179 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1
),
180 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2
),
181 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE
),
182 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE
),
183 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS
),
184 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT
),
185 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT
),
186 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS
),
187 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT
),
188 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT
),
189 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_RESOLUTION_SUPPORT
),
190 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH
),
193 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
194 #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
197 static void intel_sdvo_debug_write(struct intel_output
*intel_output
, u8 cmd
,
198 void *args
, int args_len
)
200 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
203 DRM_DEBUG("%s: W: %02X ", SDVO_NAME(sdvo_priv
), cmd
);
204 for (i
= 0; i
< args_len
; i
++)
205 printk("%02X ", ((u8
*)args
)[i
]);
208 for (i
= 0; i
< sizeof(sdvo_cmd_names
) / sizeof(sdvo_cmd_names
[0]); i
++) {
209 if (cmd
== sdvo_cmd_names
[i
].cmd
) {
210 printk("(%s)", sdvo_cmd_names
[i
].name
);
214 if (i
== sizeof(sdvo_cmd_names
)/ sizeof(sdvo_cmd_names
[0]))
215 printk("(%02X)",cmd
);
219 #define intel_sdvo_debug_write(o, c, a, l)
222 static void intel_sdvo_write_cmd(struct intel_output
*intel_output
, u8 cmd
,
223 void *args
, int args_len
)
227 intel_sdvo_debug_write(intel_output
, cmd
, args
, args_len
);
229 for (i
= 0; i
< args_len
; i
++) {
230 intel_sdvo_write_byte(intel_output
, SDVO_I2C_ARG_0
- i
,
234 intel_sdvo_write_byte(intel_output
, SDVO_I2C_OPCODE
, cmd
);
238 static const char *cmd_status_names
[] = {
244 "Target not specified",
245 "Scaling not supported"
248 static void intel_sdvo_debug_response(struct intel_output
*intel_output
,
249 void *response
, int response_len
,
252 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
254 DRM_DEBUG("%s: R: ", SDVO_NAME(sdvo_priv
));
255 for (i
= 0; i
< response_len
; i
++)
256 printk("%02X ", ((u8
*)response
)[i
]);
259 if (status
<= SDVO_CMD_STATUS_SCALING_NOT_SUPP
)
260 printk("(%s)", cmd_status_names
[status
]);
262 printk("(??? %d)", status
);
266 #define intel_sdvo_debug_response(o, r, l, s)
269 static u8
intel_sdvo_read_response(struct intel_output
*intel_output
,
270 void *response
, int response_len
)
277 /* Read the command response */
278 for (i
= 0; i
< response_len
; i
++) {
279 intel_sdvo_read_byte(intel_output
,
280 SDVO_I2C_RETURN_0
+ i
,
281 &((u8
*)response
)[i
]);
284 /* read the return status */
285 intel_sdvo_read_byte(intel_output
, SDVO_I2C_CMD_STATUS
,
288 intel_sdvo_debug_response(intel_output
, response
, response_len
,
290 if (status
!= SDVO_CMD_STATUS_PENDING
)
299 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode
*mode
)
301 if (mode
->clock
>= 100000)
303 else if (mode
->clock
>= 50000)
310 * Don't check status code from this as it switches the bus back to the
311 * SDVO chips which defeats the purpose of doing a bus switch in the first
314 static void intel_sdvo_set_control_bus_switch(struct intel_output
*intel_output
,
317 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_CONTROL_BUS_SWITCH
, &target
, 1);
320 static bool intel_sdvo_set_target_input(struct intel_output
*intel_output
, bool target_0
, bool target_1
)
322 struct intel_sdvo_set_target_input_args targets
= {0};
325 if (target_0
&& target_1
)
326 return SDVO_CMD_STATUS_NOTSUPP
;
329 targets
.target_1
= 1;
331 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_TARGET_INPUT
, &targets
,
334 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
336 return (status
== SDVO_CMD_STATUS_SUCCESS
);
340 * Return whether each input is trained.
342 * This function is making an assumption about the layout of the response,
343 * which should be checked against the docs.
345 static bool intel_sdvo_get_trained_inputs(struct intel_output
*intel_output
, bool *input_1
, bool *input_2
)
347 struct intel_sdvo_get_trained_inputs_response response
;
350 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_TRAINED_INPUTS
, NULL
, 0);
351 status
= intel_sdvo_read_response(intel_output
, &response
, sizeof(response
));
352 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
355 *input_1
= response
.input0_trained
;
356 *input_2
= response
.input1_trained
;
360 static bool intel_sdvo_get_active_outputs(struct intel_output
*intel_output
,
365 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_ACTIVE_OUTPUTS
, NULL
, 0);
366 status
= intel_sdvo_read_response(intel_output
, outputs
, sizeof(*outputs
));
368 return (status
== SDVO_CMD_STATUS_SUCCESS
);
371 static bool intel_sdvo_set_active_outputs(struct intel_output
*intel_output
,
376 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_ACTIVE_OUTPUTS
, &outputs
,
378 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
379 return (status
== SDVO_CMD_STATUS_SUCCESS
);
382 static bool intel_sdvo_set_encoder_power_state(struct intel_output
*intel_output
,
385 u8 status
, state
= SDVO_ENCODER_STATE_ON
;
388 case DRM_MODE_DPMS_ON
:
389 state
= SDVO_ENCODER_STATE_ON
;
391 case DRM_MODE_DPMS_STANDBY
:
392 state
= SDVO_ENCODER_STATE_STANDBY
;
394 case DRM_MODE_DPMS_SUSPEND
:
395 state
= SDVO_ENCODER_STATE_SUSPEND
;
397 case DRM_MODE_DPMS_OFF
:
398 state
= SDVO_ENCODER_STATE_OFF
;
402 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_ENCODER_POWER_STATE
, &state
,
404 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
406 return (status
== SDVO_CMD_STATUS_SUCCESS
);
409 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output
*intel_output
,
413 struct intel_sdvo_pixel_clock_range clocks
;
416 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE
,
419 status
= intel_sdvo_read_response(intel_output
, &clocks
, sizeof(clocks
));
421 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
424 /* Convert the values from units of 10 kHz to kHz. */
425 *clock_min
= clocks
.min
* 10;
426 *clock_max
= clocks
.max
* 10;
431 static bool intel_sdvo_set_target_output(struct intel_output
*intel_output
,
436 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_TARGET_OUTPUT
, &outputs
,
439 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
440 return (status
== SDVO_CMD_STATUS_SUCCESS
);
443 static bool intel_sdvo_get_timing(struct intel_output
*intel_output
, u8 cmd
,
444 struct intel_sdvo_dtd
*dtd
)
448 intel_sdvo_write_cmd(intel_output
, cmd
, NULL
, 0);
449 status
= intel_sdvo_read_response(intel_output
, &dtd
->part1
,
451 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
454 intel_sdvo_write_cmd(intel_output
, cmd
+ 1, NULL
, 0);
455 status
= intel_sdvo_read_response(intel_output
, &dtd
->part2
,
457 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
463 static bool intel_sdvo_get_input_timing(struct intel_output
*intel_output
,
464 struct intel_sdvo_dtd
*dtd
)
466 return intel_sdvo_get_timing(intel_output
,
467 SDVO_CMD_GET_INPUT_TIMINGS_PART1
, dtd
);
470 static bool intel_sdvo_get_output_timing(struct intel_output
*intel_output
,
471 struct intel_sdvo_dtd
*dtd
)
473 return intel_sdvo_get_timing(intel_output
,
474 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1
, dtd
);
477 static bool intel_sdvo_set_timing(struct intel_output
*intel_output
, u8 cmd
,
478 struct intel_sdvo_dtd
*dtd
)
482 intel_sdvo_write_cmd(intel_output
, cmd
, &dtd
->part1
, sizeof(dtd
->part1
));
483 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
484 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
487 intel_sdvo_write_cmd(intel_output
, cmd
+ 1, &dtd
->part2
, sizeof(dtd
->part2
));
488 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
489 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
495 static bool intel_sdvo_set_input_timing(struct intel_output
*intel_output
,
496 struct intel_sdvo_dtd
*dtd
)
498 return intel_sdvo_set_timing(intel_output
,
499 SDVO_CMD_SET_INPUT_TIMINGS_PART1
, dtd
);
502 static bool intel_sdvo_set_output_timing(struct intel_output
*intel_output
,
503 struct intel_sdvo_dtd
*dtd
)
505 return intel_sdvo_set_timing(intel_output
,
506 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1
, dtd
);
510 static int intel_sdvo_get_clock_rate_mult(struct intel_output
*intel_output
)
514 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_CLOCK_RATE_MULT
, NULL
, 0);
515 status
= intel_sdvo_read_response(intel_output
, &response
, 1);
517 if (status
!= SDVO_CMD_STATUS_SUCCESS
) {
518 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
519 return SDVO_CLOCK_RATE_MULT_1X
;
521 DRM_DEBUG("Current clock rate multiplier: %d\n", response
);
527 static bool intel_sdvo_set_clock_rate_mult(struct intel_output
*intel_output
, u8 val
)
531 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_CLOCK_RATE_MULT
, &val
, 1);
532 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
533 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
539 static bool intel_sdvo_mode_fixup(struct drm_encoder
*encoder
,
540 struct drm_display_mode
*mode
,
541 struct drm_display_mode
*adjusted_mode
)
543 /* Make the CRTC code factor in the SDVO pixel multiplier. The SDVO
544 * device will be told of the multiplier during mode_set.
546 adjusted_mode
->clock
*= intel_sdvo_get_pixel_multiplier(mode
);
550 static void intel_sdvo_mode_set(struct drm_encoder
*encoder
,
551 struct drm_display_mode
*mode
,
552 struct drm_display_mode
*adjusted_mode
)
554 struct drm_device
*dev
= encoder
->dev
;
555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
556 struct drm_crtc
*crtc
= encoder
->crtc
;
557 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
558 struct intel_output
*intel_output
= enc_to_intel_output(encoder
);
559 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
561 u16 h_blank_len
, h_sync_len
, v_blank_len
, v_sync_len
;
562 u16 h_sync_offset
, v_sync_offset
;
564 struct intel_sdvo_dtd output_dtd
;
565 int sdvo_pixel_multiply
;
570 width
= mode
->crtc_hdisplay
;
571 height
= mode
->crtc_vdisplay
;
573 /* do some mode translations */
574 h_blank_len
= mode
->crtc_hblank_end
- mode
->crtc_hblank_start
;
575 h_sync_len
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
577 v_blank_len
= mode
->crtc_vblank_end
- mode
->crtc_vblank_start
;
578 v_sync_len
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
580 h_sync_offset
= mode
->crtc_hsync_start
- mode
->crtc_hblank_start
;
581 v_sync_offset
= mode
->crtc_vsync_start
- mode
->crtc_vblank_start
;
583 output_dtd
.part1
.clock
= mode
->clock
/ 10;
584 output_dtd
.part1
.h_active
= width
& 0xff;
585 output_dtd
.part1
.h_blank
= h_blank_len
& 0xff;
586 output_dtd
.part1
.h_high
= (((width
>> 8) & 0xf) << 4) |
587 ((h_blank_len
>> 8) & 0xf);
588 output_dtd
.part1
.v_active
= height
& 0xff;
589 output_dtd
.part1
.v_blank
= v_blank_len
& 0xff;
590 output_dtd
.part1
.v_high
= (((height
>> 8) & 0xf) << 4) |
591 ((v_blank_len
>> 8) & 0xf);
593 output_dtd
.part2
.h_sync_off
= h_sync_offset
;
594 output_dtd
.part2
.h_sync_width
= h_sync_len
& 0xff;
595 output_dtd
.part2
.v_sync_off_width
= (v_sync_offset
& 0xf) << 4 |
597 output_dtd
.part2
.sync_off_width_high
= ((h_sync_offset
& 0x300) >> 2) |
598 ((h_sync_len
& 0x300) >> 4) | ((v_sync_offset
& 0x30) >> 2) |
599 ((v_sync_len
& 0x30) >> 4);
601 output_dtd
.part2
.dtd_flags
= 0x18;
602 if (mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
603 output_dtd
.part2
.dtd_flags
|= 0x2;
604 if (mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
605 output_dtd
.part2
.dtd_flags
|= 0x4;
607 output_dtd
.part2
.sdvo_flags
= 0;
608 output_dtd
.part2
.v_sync_off_high
= v_sync_offset
& 0xc0;
609 output_dtd
.part2
.reserved
= 0;
611 /* Set the output timing to the screen */
612 intel_sdvo_set_target_output(intel_output
, sdvo_priv
->active_outputs
);
613 intel_sdvo_set_output_timing(intel_output
, &output_dtd
);
615 /* Set the input timing to the screen. Assume always input 0. */
616 intel_sdvo_set_target_input(intel_output
, true, false);
618 /* We would like to use i830_sdvo_create_preferred_input_timing() to
619 * provide the device with a timing it can support, if it supports that
620 * feature. However, presumably we would need to adjust the CRTC to
621 * output the preferred timing, and we don't support that currently.
623 intel_sdvo_set_input_timing(intel_output
, &output_dtd
);
625 switch (intel_sdvo_get_pixel_multiplier(mode
)) {
627 intel_sdvo_set_clock_rate_mult(intel_output
,
628 SDVO_CLOCK_RATE_MULT_1X
);
631 intel_sdvo_set_clock_rate_mult(intel_output
,
632 SDVO_CLOCK_RATE_MULT_2X
);
635 intel_sdvo_set_clock_rate_mult(intel_output
,
636 SDVO_CLOCK_RATE_MULT_4X
);
640 /* Set the SDVO control regs. */
641 if (0/*IS_I965GM(dev)*/) {
642 sdvox
= SDVO_BORDER_ENABLE
;
644 sdvox
= I915_READ(sdvo_priv
->output_device
);
645 switch (sdvo_priv
->output_device
) {
647 sdvox
&= SDVOB_PRESERVE_MASK
;
650 sdvox
&= SDVOC_PRESERVE_MASK
;
653 sdvox
|= (9 << 19) | SDVO_BORDER_ENABLE
;
655 if (intel_crtc
->pipe
== 1)
656 sdvox
|= SDVO_PIPE_B_SELECT
;
658 sdvo_pixel_multiply
= intel_sdvo_get_pixel_multiplier(mode
);
660 /* done in crtc_mode_set as the dpll_md reg must be written
662 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
663 /* done in crtc_mode_set as it lives inside the
666 sdvox
|= (sdvo_pixel_multiply
- 1) << SDVO_PORT_MULTIPLY_SHIFT
;
669 intel_sdvo_write_sdvox(intel_output
, sdvox
);
672 static void intel_sdvo_dpms(struct drm_encoder
*encoder
, int mode
)
674 struct drm_device
*dev
= encoder
->dev
;
675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
676 struct intel_output
*intel_output
= enc_to_intel_output(encoder
);
677 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
680 if (mode
!= DRM_MODE_DPMS_ON
) {
681 intel_sdvo_set_active_outputs(intel_output
, 0);
683 intel_sdvo_set_encoder_power_state(intel_output
, mode
);
685 if (mode
== DRM_MODE_DPMS_OFF
) {
686 temp
= I915_READ(sdvo_priv
->output_device
);
687 if ((temp
& SDVO_ENABLE
) != 0) {
688 intel_sdvo_write_sdvox(intel_output
, temp
& ~SDVO_ENABLE
);
696 temp
= I915_READ(sdvo_priv
->output_device
);
697 if ((temp
& SDVO_ENABLE
) == 0)
698 intel_sdvo_write_sdvox(intel_output
, temp
| SDVO_ENABLE
);
699 for (i
= 0; i
< 2; i
++)
700 intel_wait_for_vblank(dev
);
702 status
= intel_sdvo_get_trained_inputs(intel_output
, &input1
,
706 /* Warn if the device reported failure to sync.
707 * A lot of SDVO devices fail to notify of sync, but it's
708 * a given it the status is a success, we succeeded.
710 if (status
== SDVO_CMD_STATUS_SUCCESS
&& !input1
) {
711 DRM_DEBUG("First %s output reported failure to sync\n",
712 SDVO_NAME(sdvo_priv
));
716 intel_sdvo_set_encoder_power_state(intel_output
, mode
);
717 intel_sdvo_set_active_outputs(intel_output
, sdvo_priv
->active_outputs
);
722 static void intel_sdvo_save(struct drm_connector
*connector
)
724 struct drm_device
*dev
= connector
->dev
;
725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
726 struct intel_output
*intel_output
= to_intel_output(connector
);
727 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
730 sdvo_priv
->save_sdvo_mult
= intel_sdvo_get_clock_rate_mult(intel_output
);
731 intel_sdvo_get_active_outputs(intel_output
, &sdvo_priv
->save_active_outputs
);
733 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x1) {
734 intel_sdvo_set_target_input(intel_output
, true, false);
735 intel_sdvo_get_input_timing(intel_output
,
736 &sdvo_priv
->save_input_dtd_1
);
739 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x2) {
740 intel_sdvo_set_target_input(intel_output
, false, true);
741 intel_sdvo_get_input_timing(intel_output
,
742 &sdvo_priv
->save_input_dtd_2
);
745 for (o
= SDVO_OUTPUT_FIRST
; o
<= SDVO_OUTPUT_LAST
; o
++)
747 u16 this_output
= (1 << o
);
748 if (sdvo_priv
->caps
.output_flags
& this_output
)
750 intel_sdvo_set_target_output(intel_output
, this_output
);
751 intel_sdvo_get_output_timing(intel_output
,
752 &sdvo_priv
->save_output_dtd
[o
]);
756 sdvo_priv
->save_SDVOX
= I915_READ(sdvo_priv
->output_device
);
759 static void intel_sdvo_restore(struct drm_connector
*connector
)
761 struct drm_device
*dev
= connector
->dev
;
762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
763 struct intel_output
*intel_output
= to_intel_output(connector
);
764 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
770 intel_sdvo_set_active_outputs(intel_output
, 0);
772 for (o
= SDVO_OUTPUT_FIRST
; o
<= SDVO_OUTPUT_LAST
; o
++)
774 u16 this_output
= (1 << o
);
775 if (sdvo_priv
->caps
.output_flags
& this_output
) {
776 intel_sdvo_set_target_output(intel_output
, this_output
);
777 intel_sdvo_set_output_timing(intel_output
, &sdvo_priv
->save_output_dtd
[o
]);
781 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x1) {
782 intel_sdvo_set_target_input(intel_output
, true, false);
783 intel_sdvo_set_input_timing(intel_output
, &sdvo_priv
->save_input_dtd_1
);
786 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x2) {
787 intel_sdvo_set_target_input(intel_output
, false, true);
788 intel_sdvo_set_input_timing(intel_output
, &sdvo_priv
->save_input_dtd_2
);
791 intel_sdvo_set_clock_rate_mult(intel_output
, sdvo_priv
->save_sdvo_mult
);
793 I915_WRITE(sdvo_priv
->output_device
, sdvo_priv
->save_SDVOX
);
795 if (sdvo_priv
->save_SDVOX
& SDVO_ENABLE
)
797 for (i
= 0; i
< 2; i
++)
798 intel_wait_for_vblank(dev
);
799 status
= intel_sdvo_get_trained_inputs(intel_output
, &input1
, &input2
);
800 if (status
== SDVO_CMD_STATUS_SUCCESS
&& !input1
)
801 DRM_DEBUG("First %s output reported failure to sync\n",
802 SDVO_NAME(sdvo_priv
));
805 intel_sdvo_set_active_outputs(intel_output
, sdvo_priv
->save_active_outputs
);
808 static int intel_sdvo_mode_valid(struct drm_connector
*connector
,
809 struct drm_display_mode
*mode
)
811 struct intel_output
*intel_output
= to_intel_output(connector
);
812 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
814 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
815 return MODE_NO_DBLESCAN
;
817 if (sdvo_priv
->pixel_clock_min
> mode
->clock
)
818 return MODE_CLOCK_LOW
;
820 if (sdvo_priv
->pixel_clock_max
< mode
->clock
)
821 return MODE_CLOCK_HIGH
;
826 static bool intel_sdvo_get_capabilities(struct intel_output
*intel_output
, struct intel_sdvo_caps
*caps
)
830 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_DEVICE_CAPS
, NULL
, 0);
831 status
= intel_sdvo_read_response(intel_output
, caps
, sizeof(*caps
));
832 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
838 struct drm_connector
* intel_sdvo_find(struct drm_device
*dev
, int sdvoB
)
840 struct drm_connector
*connector
= NULL
;
841 struct intel_output
*iout
= NULL
;
842 struct intel_sdvo_priv
*sdvo
;
844 /* find the sdvo connector */
845 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
846 iout
= to_intel_output(connector
);
848 if (iout
->type
!= INTEL_OUTPUT_SDVO
)
851 sdvo
= iout
->dev_priv
;
853 if (sdvo
->output_device
== SDVOB
&& sdvoB
)
856 if (sdvo
->output_device
== SDVOC
&& !sdvoB
)
864 int intel_sdvo_supports_hotplug(struct drm_connector
*connector
)
868 struct intel_output
*intel_output
;
874 intel_output
= to_intel_output(connector
);
876 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_HOT_PLUG_SUPPORT
, NULL
, 0);
877 status
= intel_sdvo_read_response(intel_output
, &response
, 2);
885 void intel_sdvo_set_hotplug(struct drm_connector
*connector
, int on
)
889 struct intel_output
*intel_output
= to_intel_output(connector
);
891 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_ACTIVE_HOT_PLUG
, NULL
, 0);
892 intel_sdvo_read_response(intel_output
, &response
, 2);
895 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_HOT_PLUG_SUPPORT
, NULL
, 0);
896 status
= intel_sdvo_read_response(intel_output
, &response
, 2);
898 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_ACTIVE_HOT_PLUG
, &response
, 2);
902 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_ACTIVE_HOT_PLUG
, &response
, 2);
905 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_ACTIVE_HOT_PLUG
, NULL
, 0);
906 intel_sdvo_read_response(intel_output
, &response
, 2);
909 static enum drm_connector_status
intel_sdvo_detect(struct drm_connector
*connector
)
913 struct intel_output
*intel_output
= to_intel_output(connector
);
915 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_ATTACHED_DISPLAYS
, NULL
, 0);
916 status
= intel_sdvo_read_response(intel_output
, &response
, 2);
918 DRM_DEBUG("SDVO response %d %d\n", response
[0], response
[1]);
919 if ((response
[0] != 0) || (response
[1] != 0))
920 return connector_status_connected
;
922 return connector_status_disconnected
;
925 static int intel_sdvo_get_modes(struct drm_connector
*connector
)
927 struct intel_output
*intel_output
= to_intel_output(connector
);
929 /* set the bus switch and get the modes */
930 intel_sdvo_set_control_bus_switch(intel_output
, SDVO_CONTROL_BUS_DDC2
);
931 intel_ddc_get_modes(intel_output
);
933 if (list_empty(&connector
->probed_modes
))
938 static void intel_sdvo_destroy(struct drm_connector
*connector
)
940 struct intel_output
*intel_output
= to_intel_output(connector
);
942 if (intel_output
->i2c_bus
)
943 intel_i2c_destroy(intel_output
->i2c_bus
);
944 drm_sysfs_connector_remove(connector
);
945 drm_connector_cleanup(connector
);
949 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs
= {
950 .dpms
= intel_sdvo_dpms
,
951 .mode_fixup
= intel_sdvo_mode_fixup
,
952 .prepare
= intel_encoder_prepare
,
953 .mode_set
= intel_sdvo_mode_set
,
954 .commit
= intel_encoder_commit
,
957 static const struct drm_connector_funcs intel_sdvo_connector_funcs
= {
958 .save
= intel_sdvo_save
,
959 .restore
= intel_sdvo_restore
,
960 .detect
= intel_sdvo_detect
,
961 .fill_modes
= drm_helper_probe_single_connector_modes
,
962 .destroy
= intel_sdvo_destroy
,
965 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs
= {
966 .get_modes
= intel_sdvo_get_modes
,
967 .mode_valid
= intel_sdvo_mode_valid
,
968 .best_encoder
= intel_best_encoder
,
971 static void intel_sdvo_enc_destroy(struct drm_encoder
*encoder
)
973 drm_encoder_cleanup(encoder
);
976 static const struct drm_encoder_funcs intel_sdvo_enc_funcs
= {
977 .destroy
= intel_sdvo_enc_destroy
,
981 bool intel_sdvo_init(struct drm_device
*dev
, int output_device
)
983 struct drm_connector
*connector
;
984 struct intel_output
*intel_output
;
985 struct intel_sdvo_priv
*sdvo_priv
;
986 struct intel_i2c_chan
*i2cbus
= NULL
;
990 int encoder_type
, output_id
;
992 intel_output
= kcalloc(sizeof(struct intel_output
)+sizeof(struct intel_sdvo_priv
), 1, GFP_KERNEL
);
997 connector
= &intel_output
->base
;
999 drm_connector_init(dev
, connector
, &intel_sdvo_connector_funcs
,
1000 DRM_MODE_CONNECTOR_Unknown
);
1001 drm_connector_helper_add(connector
, &intel_sdvo_connector_helper_funcs
);
1002 sdvo_priv
= (struct intel_sdvo_priv
*)(intel_output
+ 1);
1003 intel_output
->type
= INTEL_OUTPUT_SDVO
;
1005 connector
->interlace_allowed
= 0;
1006 connector
->doublescan_allowed
= 0;
1008 /* setup the DDC bus. */
1009 if (output_device
== SDVOB
)
1010 i2cbus
= intel_i2c_create(dev
, GPIOE
, "SDVOCTRL_E for SDVOB");
1012 i2cbus
= intel_i2c_create(dev
, GPIOE
, "SDVOCTRL_E for SDVOC");
1017 sdvo_priv
->i2c_bus
= i2cbus
;
1019 if (output_device
== SDVOB
) {
1021 sdvo_priv
->i2c_bus
->slave_addr
= 0x38;
1024 sdvo_priv
->i2c_bus
->slave_addr
= 0x39;
1027 sdvo_priv
->output_device
= output_device
;
1028 intel_output
->i2c_bus
= i2cbus
;
1029 intel_output
->dev_priv
= sdvo_priv
;
1032 /* Read the regs to test if we can talk to the device */
1033 for (i
= 0; i
< 0x40; i
++) {
1034 if (!intel_sdvo_read_byte(intel_output
, i
, &ch
[i
])) {
1035 DRM_DEBUG("No SDVO device found on SDVO%c\n",
1036 output_device
== SDVOB
? 'B' : 'C');
1041 intel_sdvo_get_capabilities(intel_output
, &sdvo_priv
->caps
);
1043 memset(&sdvo_priv
->active_outputs
, 0, sizeof(sdvo_priv
->active_outputs
));
1045 /* TODO, CVBS, SVID, YPRPB & SCART outputs. */
1046 if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_RGB0
)
1048 sdvo_priv
->active_outputs
= SDVO_OUTPUT_RGB0
;
1049 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
;
1050 encoder_type
= DRM_MODE_ENCODER_DAC
;
1051 connector_type
= DRM_MODE_CONNECTOR_VGA
;
1053 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_RGB1
)
1055 sdvo_priv
->active_outputs
= SDVO_OUTPUT_RGB1
;
1056 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
;
1057 encoder_type
= DRM_MODE_ENCODER_DAC
;
1058 connector_type
= DRM_MODE_CONNECTOR_VGA
;
1060 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_TMDS0
)
1062 sdvo_priv
->active_outputs
= SDVO_OUTPUT_TMDS0
;
1063 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
;
1064 encoder_type
= DRM_MODE_ENCODER_TMDS
;
1065 connector_type
= DRM_MODE_CONNECTOR_DVID
;
1067 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_TMDS1
)
1069 sdvo_priv
->active_outputs
= SDVO_OUTPUT_TMDS1
;
1070 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
;
1071 encoder_type
= DRM_MODE_ENCODER_TMDS
;
1072 connector_type
= DRM_MODE_CONNECTOR_DVID
;
1076 unsigned char bytes
[2];
1078 memcpy (bytes
, &sdvo_priv
->caps
.output_flags
, 2);
1079 DRM_DEBUG("%s: No active RGB or TMDS outputs (0x%02x%02x)\n",
1080 SDVO_NAME(sdvo_priv
),
1081 bytes
[0], bytes
[1]);
1085 drm_encoder_init(dev
, &intel_output
->enc
, &intel_sdvo_enc_funcs
, encoder_type
);
1086 drm_encoder_helper_add(&intel_output
->enc
, &intel_sdvo_helper_funcs
);
1087 connector
->connector_type
= connector_type
;
1089 drm_mode_connector_attach_encoder(&intel_output
->base
, &intel_output
->enc
);
1090 drm_sysfs_connector_add(connector
);
1092 /* Set the input timing to the screen. Assume always input 0. */
1093 intel_sdvo_set_target_input(intel_output
, true, false);
1095 intel_sdvo_get_input_pixel_clock_range(intel_output
,
1096 &sdvo_priv
->pixel_clock_min
,
1097 &sdvo_priv
->pixel_clock_max
);
1100 DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, "
1101 "clock range %dMHz - %dMHz, "
1102 "input 1: %c, input 2: %c, "
1103 "output 1: %c, output 2: %c\n",
1104 SDVO_NAME(sdvo_priv
),
1105 sdvo_priv
->caps
.vendor_id
, sdvo_priv
->caps
.device_id
,
1106 sdvo_priv
->caps
.device_rev_id
,
1107 sdvo_priv
->pixel_clock_min
/ 1000,
1108 sdvo_priv
->pixel_clock_max
/ 1000,
1109 (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x1) ? 'Y' : 'N',
1110 (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x2) ? 'Y' : 'N',
1111 /* check currently supported outputs */
1112 sdvo_priv
->caps
.output_flags
&
1113 (SDVO_OUTPUT_TMDS0
| SDVO_OUTPUT_RGB0
) ? 'Y' : 'N',
1114 sdvo_priv
->caps
.output_flags
&
1115 (SDVO_OUTPUT_TMDS1
| SDVO_OUTPUT_RGB1
) ? 'Y' : 'N');
1117 intel_output
->ddc_bus
= i2cbus
;
1122 intel_i2c_destroy(intel_output
->i2c_bus
);
1124 drm_connector_cleanup(connector
);
1125 kfree(intel_output
);