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drm/i915/sdvo: Markup a few constant strings.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc.h"
34 #include "drm_edid.h"
35 #include "intel_drv.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "intel_sdvo_regs.h"
39
40 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
50 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
51
52
53 static const char *tv_format_names[] = {
54 "NTSC_M" , "NTSC_J" , "NTSC_443",
55 "PAL_B" , "PAL_D" , "PAL_G" ,
56 "PAL_H" , "PAL_I" , "PAL_M" ,
57 "PAL_N" , "PAL_NC" , "PAL_60" ,
58 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
59 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
60 "SECAM_60"
61 };
62
63 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
64
65 struct intel_sdvo {
66 struct intel_encoder base;
67
68 u8 slave_addr;
69
70 /* Register for the SDVO device: SDVOB or SDVOC */
71 int sdvo_reg;
72
73 /* Active outputs controlled by this SDVO output */
74 uint16_t controlled_output;
75
76 /*
77 * Capabilities of the SDVO device returned by
78 * i830_sdvo_get_capabilities()
79 */
80 struct intel_sdvo_caps caps;
81
82 /* Pixel clock limitations reported by the SDVO device, in kHz */
83 int pixel_clock_min, pixel_clock_max;
84
85 /*
86 * For multiple function SDVO device,
87 * this is for current attached outputs.
88 */
89 uint16_t attached_output;
90
91 /**
92 * This is set if we're going to treat the device as TV-out.
93 *
94 * While we have these nice friendly flags for output types that ought
95 * to decide this for us, the S-Video output on our HDMI+S-Video card
96 * shows up as RGB1 (VGA).
97 */
98 bool is_tv;
99
100 /* This is for current tv format name */
101 int tv_format_index;
102
103 /**
104 * This is set if we treat the device as HDMI, instead of DVI.
105 */
106 bool is_hdmi;
107
108 /**
109 * This is set if we detect output of sdvo device as LVDS.
110 */
111 bool is_lvds;
112
113 /**
114 * This is sdvo flags for input timing.
115 */
116 uint8_t sdvo_flags;
117
118 /**
119 * This is sdvo fixed pannel mode pointer
120 */
121 struct drm_display_mode *sdvo_lvds_fixed_mode;
122
123 /*
124 * supported encoding mode, used to determine whether HDMI is
125 * supported
126 */
127 struct intel_sdvo_encode encode;
128
129 /* DDC bus used by this SDVO encoder */
130 uint8_t ddc_bus;
131
132 /* Mac mini hack -- use the same DDC as the analog connector */
133 struct i2c_adapter *analog_ddc_bus;
134
135 };
136
137 struct intel_sdvo_connector {
138 struct intel_connector base;
139
140 /* Mark the type of connector */
141 uint16_t output_flag;
142
143 /* This contains all current supported TV format */
144 u8 tv_format_supported[TV_FORMAT_NUM];
145 int format_supported_num;
146 struct drm_property *tv_format;
147
148 /* add the property for the SDVO-TV */
149 struct drm_property *left;
150 struct drm_property *right;
151 struct drm_property *top;
152 struct drm_property *bottom;
153 struct drm_property *hpos;
154 struct drm_property *vpos;
155 struct drm_property *contrast;
156 struct drm_property *saturation;
157 struct drm_property *hue;
158 struct drm_property *sharpness;
159 struct drm_property *flicker_filter;
160 struct drm_property *flicker_filter_adaptive;
161 struct drm_property *flicker_filter_2d;
162 struct drm_property *tv_chroma_filter;
163 struct drm_property *tv_luma_filter;
164 struct drm_property *dot_crawl;
165
166 /* add the property for the SDVO-TV/LVDS */
167 struct drm_property *brightness;
168
169 /* Add variable to record current setting for the above property */
170 u32 left_margin, right_margin, top_margin, bottom_margin;
171
172 /* this is to get the range of margin.*/
173 u32 max_hscan, max_vscan;
174 u32 max_hpos, cur_hpos;
175 u32 max_vpos, cur_vpos;
176 u32 cur_brightness, max_brightness;
177 u32 cur_contrast, max_contrast;
178 u32 cur_saturation, max_saturation;
179 u32 cur_hue, max_hue;
180 u32 cur_sharpness, max_sharpness;
181 u32 cur_flicker_filter, max_flicker_filter;
182 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
183 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
184 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
185 u32 cur_tv_luma_filter, max_tv_luma_filter;
186 u32 cur_dot_crawl, max_dot_crawl;
187 };
188
189 static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder)
190 {
191 return container_of(enc_to_intel_encoder(encoder), struct intel_sdvo, base);
192 }
193
194 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
195 {
196 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
197 }
198
199 static bool
200 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
201 static bool
202 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
203 struct intel_sdvo_connector *intel_sdvo_connector,
204 int type);
205 static bool
206 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
207 struct intel_sdvo_connector *intel_sdvo_connector);
208
209 /**
210 * Writes the SDVOB or SDVOC with the given value, but always writes both
211 * SDVOB and SDVOC to work around apparent hardware issues (according to
212 * comments in the BIOS).
213 */
214 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
215 {
216 struct drm_device *dev = intel_sdvo->base.enc.dev;
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 u32 bval = val, cval = val;
219 int i;
220
221 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
222 I915_WRITE(intel_sdvo->sdvo_reg, val);
223 I915_READ(intel_sdvo->sdvo_reg);
224 return;
225 }
226
227 if (intel_sdvo->sdvo_reg == SDVOB) {
228 cval = I915_READ(SDVOC);
229 } else {
230 bval = I915_READ(SDVOB);
231 }
232 /*
233 * Write the registers twice for luck. Sometimes,
234 * writing them only once doesn't appear to 'stick'.
235 * The BIOS does this too. Yay, magic
236 */
237 for (i = 0; i < 2; i++)
238 {
239 I915_WRITE(SDVOB, bval);
240 I915_READ(SDVOB);
241 I915_WRITE(SDVOC, cval);
242 I915_READ(SDVOC);
243 }
244 }
245
246 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
247 {
248 u8 out_buf[2] = { addr, 0 };
249 u8 buf[2];
250 struct i2c_msg msgs[] = {
251 {
252 .addr = intel_sdvo->slave_addr >> 1,
253 .flags = 0,
254 .len = 1,
255 .buf = out_buf,
256 },
257 {
258 .addr = intel_sdvo->slave_addr >> 1,
259 .flags = I2C_M_RD,
260 .len = 1,
261 .buf = buf,
262 }
263 };
264 int ret;
265
266 if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2)
267 {
268 *ch = buf[0];
269 return true;
270 }
271
272 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
273 return false;
274 }
275
276 static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch)
277 {
278 u8 out_buf[2] = { addr, ch };
279 struct i2c_msg msgs[] = {
280 {
281 .addr = intel_sdvo->slave_addr >> 1,
282 .flags = 0,
283 .len = 2,
284 .buf = out_buf,
285 }
286 };
287
288 return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1;
289 }
290
291 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
292 /** Mapping of command numbers to names, for debug output */
293 static const struct _sdvo_cmd_name {
294 u8 cmd;
295 const char *name;
296 } sdvo_cmd_names[] = {
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
340
341 /* Add the op code for SDVO enhancements */
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
386
387 /* HDMI op code */
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
408 };
409
410 #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
411 #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
412
413 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
414 const void *args, int args_len)
415 {
416 int i;
417
418 DRM_DEBUG_KMS("%s: W: %02X ",
419 SDVO_NAME(intel_sdvo), cmd);
420 for (i = 0; i < args_len; i++)
421 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
422 for (; i < 8; i++)
423 DRM_LOG_KMS(" ");
424 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
425 if (cmd == sdvo_cmd_names[i].cmd) {
426 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
427 break;
428 }
429 }
430 if (i == ARRAY_SIZE(sdvo_cmd_names))
431 DRM_LOG_KMS("(%02X)", cmd);
432 DRM_LOG_KMS("\n");
433 }
434
435 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
436 const void *args, int args_len)
437 {
438 int i;
439
440 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
441
442 for (i = 0; i < args_len; i++) {
443 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
444 ((u8*)args)[i]))
445 return false;
446 }
447
448 return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
449 }
450
451 static const char *cmd_status_names[] = {
452 "Power on",
453 "Success",
454 "Not supported",
455 "Invalid arg",
456 "Pending",
457 "Target not specified",
458 "Scaling not supported"
459 };
460
461 static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo,
462 void *response, int response_len,
463 u8 status)
464 {
465 int i;
466
467 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
468 for (i = 0; i < response_len; i++)
469 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
470 for (; i < 8; i++)
471 DRM_LOG_KMS(" ");
472 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
473 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
474 else
475 DRM_LOG_KMS("(??? %d)", status);
476 DRM_LOG_KMS("\n");
477 }
478
479 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
480 void *response, int response_len)
481 {
482 int i;
483 u8 status;
484 u8 retry = 50;
485
486 while (retry--) {
487 /* Read the command response */
488 for (i = 0; i < response_len; i++) {
489 if (!intel_sdvo_read_byte(intel_sdvo,
490 SDVO_I2C_RETURN_0 + i,
491 &((u8 *)response)[i]))
492 return false;
493 }
494
495 /* read the return status */
496 if (!intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS,
497 &status))
498 return false;
499
500 intel_sdvo_debug_response(intel_sdvo, response, response_len,
501 status);
502 if (status != SDVO_CMD_STATUS_PENDING)
503 break;
504
505 mdelay(50);
506 }
507
508 return status == SDVO_CMD_STATUS_SUCCESS;
509 }
510
511 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
512 {
513 if (mode->clock >= 100000)
514 return 1;
515 else if (mode->clock >= 50000)
516 return 2;
517 else
518 return 4;
519 }
520
521 /**
522 * Try to read the response after issuie the DDC switch command. But it
523 * is noted that we must do the action of reading response and issuing DDC
524 * switch command in one I2C transaction. Otherwise when we try to start
525 * another I2C transaction after issuing the DDC bus switch, it will be
526 * switched to the internal SDVO register.
527 */
528 static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
529 u8 target)
530 {
531 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
532 struct i2c_msg msgs[] = {
533 {
534 .addr = intel_sdvo->slave_addr >> 1,
535 .flags = 0,
536 .len = 2,
537 .buf = out_buf,
538 },
539 /* the following two are to read the response */
540 {
541 .addr = intel_sdvo->slave_addr >> 1,
542 .flags = 0,
543 .len = 1,
544 .buf = cmd_buf,
545 },
546 {
547 .addr = intel_sdvo->slave_addr >> 1,
548 .flags = I2C_M_RD,
549 .len = 1,
550 .buf = ret_value,
551 },
552 };
553
554 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
555 &target, 1);
556 /* write the DDC switch command argument */
557 intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target);
558
559 out_buf[0] = SDVO_I2C_OPCODE;
560 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
561 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
562 cmd_buf[1] = 0;
563 ret_value[0] = 0;
564 ret_value[1] = 0;
565
566 ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3);
567 if (ret != 3) {
568 /* failure in I2C transfer */
569 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
570 return;
571 }
572 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
573 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
574 ret_value[0]);
575 return;
576 }
577 return;
578 }
579
580 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
581 {
582 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
583 return false;
584
585 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
586 }
587
588 static bool
589 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
590 {
591 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
592 return false;
593
594 return intel_sdvo_read_response(intel_sdvo, value, len);
595 }
596
597 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
598 {
599 struct intel_sdvo_set_target_input_args targets = {0};
600 return intel_sdvo_set_value(intel_sdvo,
601 SDVO_CMD_SET_TARGET_INPUT,
602 &targets, sizeof(targets));
603 }
604
605 /**
606 * Return whether each input is trained.
607 *
608 * This function is making an assumption about the layout of the response,
609 * which should be checked against the docs.
610 */
611 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
612 {
613 struct intel_sdvo_get_trained_inputs_response response;
614
615 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
616 &response, sizeof(response)))
617 return false;
618
619 *input_1 = response.input0_trained;
620 *input_2 = response.input1_trained;
621 return true;
622 }
623
624 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
625 u16 outputs)
626 {
627 return intel_sdvo_set_value(intel_sdvo,
628 SDVO_CMD_SET_ACTIVE_OUTPUTS,
629 &outputs, sizeof(outputs));
630 }
631
632 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
633 int mode)
634 {
635 u8 state = SDVO_ENCODER_STATE_ON;
636
637 switch (mode) {
638 case DRM_MODE_DPMS_ON:
639 state = SDVO_ENCODER_STATE_ON;
640 break;
641 case DRM_MODE_DPMS_STANDBY:
642 state = SDVO_ENCODER_STATE_STANDBY;
643 break;
644 case DRM_MODE_DPMS_SUSPEND:
645 state = SDVO_ENCODER_STATE_SUSPEND;
646 break;
647 case DRM_MODE_DPMS_OFF:
648 state = SDVO_ENCODER_STATE_OFF;
649 break;
650 }
651
652 return intel_sdvo_set_value(intel_sdvo,
653 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
654 }
655
656 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
657 int *clock_min,
658 int *clock_max)
659 {
660 struct intel_sdvo_pixel_clock_range clocks;
661
662 if (!intel_sdvo_get_value(intel_sdvo,
663 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
664 &clocks, sizeof(clocks)))
665 return false;
666
667 /* Convert the values from units of 10 kHz to kHz. */
668 *clock_min = clocks.min * 10;
669 *clock_max = clocks.max * 10;
670 return true;
671 }
672
673 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
674 u16 outputs)
675 {
676 return intel_sdvo_set_value(intel_sdvo,
677 SDVO_CMD_SET_TARGET_OUTPUT,
678 &outputs, sizeof(outputs));
679 }
680
681 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
682 struct intel_sdvo_dtd *dtd)
683 {
684 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
685 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
686 }
687
688 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
689 struct intel_sdvo_dtd *dtd)
690 {
691 return intel_sdvo_set_timing(intel_sdvo,
692 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
693 }
694
695 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
696 struct intel_sdvo_dtd *dtd)
697 {
698 return intel_sdvo_set_timing(intel_sdvo,
699 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
700 }
701
702 static bool
703 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
704 uint16_t clock,
705 uint16_t width,
706 uint16_t height)
707 {
708 struct intel_sdvo_preferred_input_timing_args args;
709
710 memset(&args, 0, sizeof(args));
711 args.clock = clock;
712 args.width = width;
713 args.height = height;
714 args.interlace = 0;
715
716 if (intel_sdvo->is_lvds &&
717 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
718 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
719 args.scaled = 1;
720
721 return intel_sdvo_set_value(intel_sdvo,
722 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
723 &args, sizeof(args));
724 }
725
726 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
727 struct intel_sdvo_dtd *dtd)
728 {
729 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
730 &dtd->part1, sizeof(dtd->part1)) &&
731 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
732 &dtd->part2, sizeof(dtd->part2));
733 }
734
735 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
736 {
737 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
738 }
739
740 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
741 const struct drm_display_mode *mode)
742 {
743 uint16_t width, height;
744 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
745 uint16_t h_sync_offset, v_sync_offset;
746
747 width = mode->crtc_hdisplay;
748 height = mode->crtc_vdisplay;
749
750 /* do some mode translations */
751 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
752 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
753
754 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
755 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
756
757 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
758 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
759
760 dtd->part1.clock = mode->clock / 10;
761 dtd->part1.h_active = width & 0xff;
762 dtd->part1.h_blank = h_blank_len & 0xff;
763 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
764 ((h_blank_len >> 8) & 0xf);
765 dtd->part1.v_active = height & 0xff;
766 dtd->part1.v_blank = v_blank_len & 0xff;
767 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
768 ((v_blank_len >> 8) & 0xf);
769
770 dtd->part2.h_sync_off = h_sync_offset & 0xff;
771 dtd->part2.h_sync_width = h_sync_len & 0xff;
772 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
773 (v_sync_len & 0xf);
774 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
775 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
776 ((v_sync_len & 0x30) >> 4);
777
778 dtd->part2.dtd_flags = 0x18;
779 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
780 dtd->part2.dtd_flags |= 0x2;
781 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
782 dtd->part2.dtd_flags |= 0x4;
783
784 dtd->part2.sdvo_flags = 0;
785 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
786 dtd->part2.reserved = 0;
787 }
788
789 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
790 const struct intel_sdvo_dtd *dtd)
791 {
792 mode->hdisplay = dtd->part1.h_active;
793 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
794 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
795 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
796 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
797 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
798 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
799 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
800
801 mode->vdisplay = dtd->part1.v_active;
802 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
803 mode->vsync_start = mode->vdisplay;
804 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
805 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
806 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
807 mode->vsync_end = mode->vsync_start +
808 (dtd->part2.v_sync_off_width & 0xf);
809 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
810 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
811 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
812
813 mode->clock = dtd->part1.clock * 10;
814
815 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
816 if (dtd->part2.dtd_flags & 0x2)
817 mode->flags |= DRM_MODE_FLAG_PHSYNC;
818 if (dtd->part2.dtd_flags & 0x4)
819 mode->flags |= DRM_MODE_FLAG_PVSYNC;
820 }
821
822 static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
823 struct intel_sdvo_encode *encode)
824 {
825 if (intel_sdvo_get_value(intel_sdvo,
826 SDVO_CMD_GET_SUPP_ENCODE,
827 encode, sizeof(*encode)))
828 return true;
829
830 /* non-support means DVI */
831 memset(encode, 0, sizeof(*encode));
832 return false;
833 }
834
835 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
836 uint8_t mode)
837 {
838 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
839 }
840
841 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
842 uint8_t mode)
843 {
844 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
845 }
846
847 #if 0
848 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
849 {
850 int i, j;
851 uint8_t set_buf_index[2];
852 uint8_t av_split;
853 uint8_t buf_size;
854 uint8_t buf[48];
855 uint8_t *pos;
856
857 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
858
859 for (i = 0; i <= av_split; i++) {
860 set_buf_index[0] = i; set_buf_index[1] = 0;
861 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
862 set_buf_index, 2);
863 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
864 intel_sdvo_read_response(encoder, &buf_size, 1);
865
866 pos = buf;
867 for (j = 0; j <= buf_size; j += 8) {
868 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
869 NULL, 0);
870 intel_sdvo_read_response(encoder, pos, 8);
871 pos += 8;
872 }
873 }
874 }
875 #endif
876
877 static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
878 int index,
879 uint8_t *data, int8_t size, uint8_t tx_rate)
880 {
881 uint8_t set_buf_index[2];
882
883 set_buf_index[0] = index;
884 set_buf_index[1] = 0;
885
886 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
887 set_buf_index, 2))
888 return false;
889
890 for (; size > 0; size -= 8) {
891 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8))
892 return false;
893
894 data += 8;
895 }
896
897 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
898 }
899
900 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
901 {
902 uint8_t csum = 0;
903 int i;
904
905 for (i = 0; i < size; i++)
906 csum += data[i];
907
908 return 0x100 - csum;
909 }
910
911 #define DIP_TYPE_AVI 0x82
912 #define DIP_VERSION_AVI 0x2
913 #define DIP_LEN_AVI 13
914
915 struct dip_infoframe {
916 uint8_t type;
917 uint8_t version;
918 uint8_t len;
919 uint8_t checksum;
920 union {
921 struct {
922 /* Packet Byte #1 */
923 uint8_t S:2;
924 uint8_t B:2;
925 uint8_t A:1;
926 uint8_t Y:2;
927 uint8_t rsvd1:1;
928 /* Packet Byte #2 */
929 uint8_t R:4;
930 uint8_t M:2;
931 uint8_t C:2;
932 /* Packet Byte #3 */
933 uint8_t SC:2;
934 uint8_t Q:2;
935 uint8_t EC:3;
936 uint8_t ITC:1;
937 /* Packet Byte #4 */
938 uint8_t VIC:7;
939 uint8_t rsvd2:1;
940 /* Packet Byte #5 */
941 uint8_t PR:4;
942 uint8_t rsvd3:4;
943 /* Packet Byte #6~13 */
944 uint16_t top_bar_end;
945 uint16_t bottom_bar_start;
946 uint16_t left_bar_end;
947 uint16_t right_bar_start;
948 } avi;
949 struct {
950 /* Packet Byte #1 */
951 uint8_t channel_count:3;
952 uint8_t rsvd1:1;
953 uint8_t coding_type:4;
954 /* Packet Byte #2 */
955 uint8_t sample_size:2; /* SS0, SS1 */
956 uint8_t sample_frequency:3;
957 uint8_t rsvd2:3;
958 /* Packet Byte #3 */
959 uint8_t coding_type_private:5;
960 uint8_t rsvd3:3;
961 /* Packet Byte #4 */
962 uint8_t channel_allocation;
963 /* Packet Byte #5 */
964 uint8_t rsvd4:3;
965 uint8_t level_shift:4;
966 uint8_t downmix_inhibit:1;
967 } audio;
968 uint8_t payload[28];
969 } __attribute__ ((packed)) u;
970 } __attribute__((packed));
971
972 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
973 struct drm_display_mode * mode)
974 {
975 struct dip_infoframe avi_if = {
976 .type = DIP_TYPE_AVI,
977 .version = DIP_VERSION_AVI,
978 .len = DIP_LEN_AVI,
979 };
980
981 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
982 4 + avi_if.len);
983 return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
984 4 + avi_if.len,
985 SDVO_HBUF_TX_VSYNC);
986 }
987
988 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
989 {
990 struct intel_sdvo_tv_format format;
991 uint32_t format_map;
992
993 format_map = 1 << intel_sdvo->tv_format_index;
994 memset(&format, 0, sizeof(format));
995 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
996
997 BUILD_BUG_ON(sizeof(format) != 6);
998 return intel_sdvo_set_value(intel_sdvo,
999 SDVO_CMD_SET_TV_FORMAT,
1000 &format, sizeof(format));
1001 }
1002
1003 static bool
1004 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1005 struct drm_display_mode *mode)
1006 {
1007 struct intel_sdvo_dtd output_dtd;
1008
1009 if (!intel_sdvo_set_target_output(intel_sdvo,
1010 intel_sdvo->attached_output))
1011 return false;
1012
1013 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1014 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1015 return false;
1016
1017 return true;
1018 }
1019
1020 static bool
1021 intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
1022 struct drm_display_mode *mode,
1023 struct drm_display_mode *adjusted_mode)
1024 {
1025 struct intel_sdvo_dtd input_dtd;
1026
1027 /* Reset the input timing to the screen. Assume always input 0. */
1028 if (!intel_sdvo_set_target_input(intel_sdvo))
1029 return false;
1030
1031 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1032 mode->clock / 10,
1033 mode->hdisplay,
1034 mode->vdisplay))
1035 return false;
1036
1037 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1038 &input_dtd))
1039 return false;
1040
1041 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1042 intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags;
1043
1044 drm_mode_set_crtcinfo(adjusted_mode, 0);
1045 mode->clock = adjusted_mode->clock;
1046 return true;
1047 }
1048
1049 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1050 struct drm_display_mode *mode,
1051 struct drm_display_mode *adjusted_mode)
1052 {
1053 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1054
1055 /* We need to construct preferred input timings based on our
1056 * output timings. To do that, we have to set the output
1057 * timings, even though this isn't really the right place in
1058 * the sequence to do it. Oh well.
1059 */
1060 if (intel_sdvo->is_tv) {
1061 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1062 return false;
1063
1064 if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode))
1065 return false;
1066 } else if (intel_sdvo->is_lvds) {
1067 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0);
1068
1069 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1070 intel_sdvo->sdvo_lvds_fixed_mode))
1071 return false;
1072
1073 if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode))
1074 return false;
1075 }
1076
1077 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1078 * SDVO device will be told of the multiplier during mode_set.
1079 */
1080 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1081
1082 return true;
1083 }
1084
1085 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1086 struct drm_display_mode *mode,
1087 struct drm_display_mode *adjusted_mode)
1088 {
1089 struct drm_device *dev = encoder->dev;
1090 struct drm_i915_private *dev_priv = dev->dev_private;
1091 struct drm_crtc *crtc = encoder->crtc;
1092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1094 u32 sdvox = 0;
1095 int sdvo_pixel_multiply, rate;
1096 struct intel_sdvo_in_out_map in_out;
1097 struct intel_sdvo_dtd input_dtd;
1098
1099 if (!mode)
1100 return;
1101
1102 /* First, set the input mapping for the first input to our controlled
1103 * output. This is only correct if we're a single-input device, in
1104 * which case the first input is the output from the appropriate SDVO
1105 * channel on the motherboard. In a two-input device, the first input
1106 * will be SDVOB and the second SDVOC.
1107 */
1108 in_out.in0 = intel_sdvo->attached_output;
1109 in_out.in1 = 0;
1110
1111 if (!intel_sdvo_set_value(intel_sdvo,
1112 SDVO_CMD_SET_IN_OUT_MAP,
1113 &in_out, sizeof(in_out)))
1114 return;
1115
1116 if (intel_sdvo->is_hdmi) {
1117 if (!intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
1118 return;
1119
1120 sdvox |= SDVO_AUDIO_ENABLE;
1121 }
1122
1123 /* We have tried to get input timing in mode_fixup, and filled into
1124 adjusted_mode */
1125 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1126 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1127 input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags;
1128 } else
1129 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1130
1131 /* If it's a TV, we already set the output timing in mode_fixup.
1132 * Otherwise, the output timing is equal to the input timing.
1133 */
1134 if (!intel_sdvo->is_tv && !intel_sdvo->is_lvds) {
1135 /* Set the output timing to the screen */
1136 if (!intel_sdvo_set_target_output(intel_sdvo,
1137 intel_sdvo->attached_output))
1138 return;
1139
1140 if (!intel_sdvo_set_output_timing(intel_sdvo, &input_dtd))
1141 return;
1142 }
1143
1144 /* Set the input timing to the screen. Assume always input 0. */
1145 if (!intel_sdvo_set_target_input(intel_sdvo))
1146 return;
1147
1148 if (intel_sdvo->is_tv) {
1149 if (!intel_sdvo_set_tv_format(intel_sdvo))
1150 return;
1151 }
1152
1153 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1154 * provide the device with a timing it can support, if it supports that
1155 * feature. However, presumably we would need to adjust the CRTC to
1156 * output the preferred timing, and we don't support that currently.
1157 */
1158 #if 0
1159 success = intel_sdvo_create_preferred_input_timing(encoder, clock,
1160 width, height);
1161 if (success) {
1162 struct intel_sdvo_dtd *input_dtd;
1163
1164 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1165 intel_sdvo_set_input_timing(encoder, &input_dtd);
1166 }
1167 #else
1168 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1169 return;
1170 #endif
1171
1172 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1173 switch (sdvo_pixel_multiply) {
1174 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1175 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1176 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1177 }
1178 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1179 return;
1180
1181 /* Set the SDVO control regs. */
1182 if (IS_I965G(dev)) {
1183 sdvox |= SDVO_BORDER_ENABLE;
1184 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1185 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1186 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1187 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
1188 } else {
1189 sdvox |= I915_READ(intel_sdvo->sdvo_reg);
1190 switch (intel_sdvo->sdvo_reg) {
1191 case SDVOB:
1192 sdvox &= SDVOB_PRESERVE_MASK;
1193 break;
1194 case SDVOC:
1195 sdvox &= SDVOC_PRESERVE_MASK;
1196 break;
1197 }
1198 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1199 }
1200 if (intel_crtc->pipe == 1)
1201 sdvox |= SDVO_PIPE_B_SELECT;
1202
1203 if (IS_I965G(dev)) {
1204 /* done in crtc_mode_set as the dpll_md reg must be written early */
1205 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1206 /* done in crtc_mode_set as it lives inside the dpll register */
1207 } else {
1208 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1209 }
1210
1211 if (intel_sdvo->sdvo_flags & SDVO_NEED_TO_STALL)
1212 sdvox |= SDVO_STALL_SELECT;
1213 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1214 }
1215
1216 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1217 {
1218 struct drm_device *dev = encoder->dev;
1219 struct drm_i915_private *dev_priv = dev->dev_private;
1220 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1221 u32 temp;
1222
1223 if (mode != DRM_MODE_DPMS_ON) {
1224 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1225 if (0)
1226 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1227
1228 if (mode == DRM_MODE_DPMS_OFF) {
1229 temp = I915_READ(intel_sdvo->sdvo_reg);
1230 if ((temp & SDVO_ENABLE) != 0) {
1231 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1232 }
1233 }
1234 } else {
1235 bool input1, input2;
1236 int i;
1237 u8 status;
1238
1239 temp = I915_READ(intel_sdvo->sdvo_reg);
1240 if ((temp & SDVO_ENABLE) == 0)
1241 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
1242 for (i = 0; i < 2; i++)
1243 intel_wait_for_vblank(dev);
1244
1245 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1246 /* Warn if the device reported failure to sync.
1247 * A lot of SDVO devices fail to notify of sync, but it's
1248 * a given it the status is a success, we succeeded.
1249 */
1250 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1251 DRM_DEBUG_KMS("First %s output reported failure to "
1252 "sync\n", SDVO_NAME(intel_sdvo));
1253 }
1254
1255 if (0)
1256 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1257 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1258 }
1259 return;
1260 }
1261
1262 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1263 struct drm_display_mode *mode)
1264 {
1265 struct drm_encoder *encoder = intel_attached_encoder(connector);
1266 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1267
1268 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1269 return MODE_NO_DBLESCAN;
1270
1271 if (intel_sdvo->pixel_clock_min > mode->clock)
1272 return MODE_CLOCK_LOW;
1273
1274 if (intel_sdvo->pixel_clock_max < mode->clock)
1275 return MODE_CLOCK_HIGH;
1276
1277 if (intel_sdvo->is_lvds == true) {
1278 if (intel_sdvo->sdvo_lvds_fixed_mode == NULL)
1279 return MODE_PANEL;
1280
1281 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1282 return MODE_PANEL;
1283
1284 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1285 return MODE_PANEL;
1286 }
1287
1288 return MODE_OK;
1289 }
1290
1291 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1292 {
1293 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps));
1294 }
1295
1296 /* No use! */
1297 #if 0
1298 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1299 {
1300 struct drm_connector *connector = NULL;
1301 struct intel_sdvo *iout = NULL;
1302 struct intel_sdvo *sdvo;
1303
1304 /* find the sdvo connector */
1305 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1306 iout = to_intel_sdvo(connector);
1307
1308 if (iout->type != INTEL_OUTPUT_SDVO)
1309 continue;
1310
1311 sdvo = iout->dev_priv;
1312
1313 if (sdvo->sdvo_reg == SDVOB && sdvoB)
1314 return connector;
1315
1316 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
1317 return connector;
1318
1319 }
1320
1321 return NULL;
1322 }
1323
1324 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1325 {
1326 u8 response[2];
1327 u8 status;
1328 struct intel_sdvo *intel_sdvo;
1329 DRM_DEBUG_KMS("\n");
1330
1331 if (!connector)
1332 return 0;
1333
1334 intel_sdvo = to_intel_sdvo(connector);
1335
1336 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1337 &response, 2) && response[0];
1338 }
1339
1340 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1341 {
1342 u8 response[2];
1343 u8 status;
1344 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
1345
1346 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1347 intel_sdvo_read_response(intel_sdvo, &response, 2);
1348
1349 if (on) {
1350 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1351 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
1352
1353 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1354 } else {
1355 response[0] = 0;
1356 response[1] = 0;
1357 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1358 }
1359
1360 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1361 intel_sdvo_read_response(intel_sdvo, &response, 2);
1362 }
1363 #endif
1364
1365 static bool
1366 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1367 {
1368 int caps = 0;
1369
1370 if (intel_sdvo->caps.output_flags &
1371 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1372 caps++;
1373 if (intel_sdvo->caps.output_flags &
1374 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1375 caps++;
1376 if (intel_sdvo->caps.output_flags &
1377 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1378 caps++;
1379 if (intel_sdvo->caps.output_flags &
1380 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1381 caps++;
1382 if (intel_sdvo->caps.output_flags &
1383 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1384 caps++;
1385
1386 if (intel_sdvo->caps.output_flags &
1387 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1388 caps++;
1389
1390 if (intel_sdvo->caps.output_flags &
1391 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1392 caps++;
1393
1394 return (caps > 1);
1395 }
1396
1397 static struct drm_connector *
1398 intel_find_analog_connector(struct drm_device *dev)
1399 {
1400 struct drm_connector *connector;
1401 struct drm_encoder *encoder;
1402 struct intel_sdvo *intel_sdvo;
1403
1404 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1405 intel_sdvo = enc_to_intel_sdvo(encoder);
1406 if (intel_sdvo->base.type == INTEL_OUTPUT_ANALOG) {
1407 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1408 if (encoder == intel_attached_encoder(connector))
1409 return connector;
1410 }
1411 }
1412 }
1413 return NULL;
1414 }
1415
1416 static int
1417 intel_analog_is_connected(struct drm_device *dev)
1418 {
1419 struct drm_connector *analog_connector;
1420
1421 analog_connector = intel_find_analog_connector(dev);
1422 if (!analog_connector)
1423 return false;
1424
1425 if (analog_connector->funcs->detect(analog_connector) ==
1426 connector_status_disconnected)
1427 return false;
1428
1429 return true;
1430 }
1431
1432 enum drm_connector_status
1433 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1434 {
1435 struct drm_encoder *encoder = intel_attached_encoder(connector);
1436 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1437 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1438 enum drm_connector_status status = connector_status_connected;
1439 struct edid *edid = NULL;
1440
1441 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
1442
1443 /* This is only applied to SDVO cards with multiple outputs */
1444 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
1445 uint8_t saved_ddc, temp_ddc;
1446 saved_ddc = intel_sdvo->ddc_bus;
1447 temp_ddc = intel_sdvo->ddc_bus >> 1;
1448 /*
1449 * Don't use the 1 as the argument of DDC bus switch to get
1450 * the EDID. It is used for SDVO SPD ROM.
1451 */
1452 while(temp_ddc > 1) {
1453 intel_sdvo->ddc_bus = temp_ddc;
1454 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
1455 if (edid) {
1456 /*
1457 * When we can get the EDID, maybe it is the
1458 * correct DDC bus. Update it.
1459 */
1460 intel_sdvo->ddc_bus = temp_ddc;
1461 break;
1462 }
1463 temp_ddc >>= 1;
1464 }
1465 if (edid == NULL)
1466 intel_sdvo->ddc_bus = saved_ddc;
1467 }
1468 /* when there is no edid and no monitor is connected with VGA
1469 * port, try to use the CRT ddc to read the EDID for DVI-connector
1470 */
1471 if (edid == NULL && intel_sdvo->analog_ddc_bus &&
1472 !intel_analog_is_connected(connector->dev))
1473 edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus);
1474
1475 if (edid != NULL) {
1476 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1477 bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK);
1478
1479 /* DDC bus is shared, match EDID to connector type */
1480 if (is_digital && need_digital)
1481 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
1482 else if (is_digital != need_digital)
1483 status = connector_status_disconnected;
1484
1485 connector->display_info.raw_edid = NULL;
1486 } else
1487 status = connector_status_disconnected;
1488
1489 kfree(edid);
1490
1491 return status;
1492 }
1493
1494 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1495 {
1496 uint16_t response;
1497 struct drm_encoder *encoder = intel_attached_encoder(connector);
1498 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1499 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1500 enum drm_connector_status ret;
1501
1502 if (!intel_sdvo_write_cmd(intel_sdvo,
1503 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1504 return connector_status_unknown;
1505 if (intel_sdvo->is_tv) {
1506 /* add 30ms delay when the output type is SDVO-TV */
1507 mdelay(30);
1508 }
1509 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1510 return connector_status_unknown;
1511
1512 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
1513
1514 if (response == 0)
1515 return connector_status_disconnected;
1516
1517 intel_sdvo->attached_output = response;
1518
1519 if ((intel_sdvo_connector->output_flag & response) == 0)
1520 ret = connector_status_disconnected;
1521 else if (response & SDVO_TMDS_MASK)
1522 ret = intel_sdvo_hdmi_sink_detect(connector);
1523 else
1524 ret = connector_status_connected;
1525
1526 /* May update encoder flag for like clock for SDVO TV, etc.*/
1527 if (ret == connector_status_connected) {
1528 intel_sdvo->is_tv = false;
1529 intel_sdvo->is_lvds = false;
1530 intel_sdvo->base.needs_tv_clock = false;
1531
1532 if (response & SDVO_TV_MASK) {
1533 intel_sdvo->is_tv = true;
1534 intel_sdvo->base.needs_tv_clock = true;
1535 }
1536 if (response & SDVO_LVDS_MASK)
1537 intel_sdvo->is_lvds = true;
1538 }
1539
1540 return ret;
1541 }
1542
1543 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1544 {
1545 struct drm_encoder *encoder = intel_attached_encoder(connector);
1546 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1547 int num_modes;
1548
1549 /* set the bus switch and get the modes */
1550 num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
1551
1552 /*
1553 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1554 * link between analog and digital outputs. So, if the regular SDVO
1555 * DDC fails, check to see if the analog output is disconnected, in
1556 * which case we'll look there for the digital DDC data.
1557 */
1558 if (num_modes == 0 &&
1559 intel_sdvo->analog_ddc_bus &&
1560 !intel_analog_is_connected(connector->dev)) {
1561 /* Switch to the analog ddc bus and try that
1562 */
1563 (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus);
1564 }
1565 }
1566
1567 /*
1568 * Set of SDVO TV modes.
1569 * Note! This is in reply order (see loop in get_tv_modes).
1570 * XXX: all 60Hz refresh?
1571 */
1572 struct drm_display_mode sdvo_tv_modes[] = {
1573 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1574 416, 0, 200, 201, 232, 233, 0,
1575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1576 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1577 416, 0, 240, 241, 272, 273, 0,
1578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1579 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1580 496, 0, 300, 301, 332, 333, 0,
1581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1582 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1583 736, 0, 350, 351, 382, 383, 0,
1584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1585 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1586 736, 0, 400, 401, 432, 433, 0,
1587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1588 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1589 736, 0, 480, 481, 512, 513, 0,
1590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1591 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1592 800, 0, 480, 481, 512, 513, 0,
1593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1594 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1595 800, 0, 576, 577, 608, 609, 0,
1596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1597 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1598 816, 0, 350, 351, 382, 383, 0,
1599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1600 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1601 816, 0, 400, 401, 432, 433, 0,
1602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1603 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1604 816, 0, 480, 481, 512, 513, 0,
1605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1606 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1607 816, 0, 540, 541, 572, 573, 0,
1608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1609 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1610 816, 0, 576, 577, 608, 609, 0,
1611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1612 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1613 864, 0, 576, 577, 608, 609, 0,
1614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1615 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1616 896, 0, 600, 601, 632, 633, 0,
1617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1618 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1619 928, 0, 624, 625, 656, 657, 0,
1620 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1621 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1622 1016, 0, 766, 767, 798, 799, 0,
1623 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1624 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1625 1120, 0, 768, 769, 800, 801, 0,
1626 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1627 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1628 1376, 0, 1024, 1025, 1056, 1057, 0,
1629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1630 };
1631
1632 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1633 {
1634 struct drm_encoder *encoder = intel_attached_encoder(connector);
1635 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1636 struct intel_sdvo_sdtv_resolution_request tv_res;
1637 uint32_t reply = 0, format_map = 0;
1638 int i;
1639
1640 /* Read the list of supported input resolutions for the selected TV
1641 * format.
1642 */
1643 format_map = 1 << intel_sdvo->tv_format_index;
1644 memcpy(&tv_res, &format_map,
1645 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
1646
1647 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1648 return;
1649
1650 BUILD_BUG_ON(sizeof(tv_res) != 3);
1651 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1652 &tv_res, sizeof(tv_res)))
1653 return;
1654 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
1655 return;
1656
1657 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1658 if (reply & (1 << i)) {
1659 struct drm_display_mode *nmode;
1660 nmode = drm_mode_duplicate(connector->dev,
1661 &sdvo_tv_modes[i]);
1662 if (nmode)
1663 drm_mode_probed_add(connector, nmode);
1664 }
1665 }
1666
1667 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1668 {
1669 struct drm_encoder *encoder = intel_attached_encoder(connector);
1670 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1671 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1672 struct drm_display_mode *newmode;
1673
1674 /*
1675 * Attempt to get the mode list from DDC.
1676 * Assume that the preferred modes are
1677 * arranged in priority order.
1678 */
1679 intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
1680 if (list_empty(&connector->probed_modes) == false)
1681 goto end;
1682
1683 /* Fetch modes from VBT */
1684 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1685 newmode = drm_mode_duplicate(connector->dev,
1686 dev_priv->sdvo_lvds_vbt_mode);
1687 if (newmode != NULL) {
1688 /* Guarantee the mode is preferred */
1689 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1690 DRM_MODE_TYPE_DRIVER);
1691 drm_mode_probed_add(connector, newmode);
1692 }
1693 }
1694
1695 end:
1696 list_for_each_entry(newmode, &connector->probed_modes, head) {
1697 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1698 intel_sdvo->sdvo_lvds_fixed_mode =
1699 drm_mode_duplicate(connector->dev, newmode);
1700 break;
1701 }
1702 }
1703
1704 }
1705
1706 static int intel_sdvo_get_modes(struct drm_connector *connector)
1707 {
1708 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1709
1710 if (IS_TV(intel_sdvo_connector))
1711 intel_sdvo_get_tv_modes(connector);
1712 else if (IS_LVDS(intel_sdvo_connector))
1713 intel_sdvo_get_lvds_modes(connector);
1714 else
1715 intel_sdvo_get_ddc_modes(connector);
1716
1717 return !list_empty(&connector->probed_modes);
1718 }
1719
1720 static void
1721 intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1722 {
1723 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1724 struct drm_device *dev = connector->dev;
1725
1726 if (intel_sdvo_connector->left)
1727 drm_property_destroy(dev, intel_sdvo_connector->left);
1728 if (intel_sdvo_connector->right)
1729 drm_property_destroy(dev, intel_sdvo_connector->right);
1730 if (intel_sdvo_connector->top)
1731 drm_property_destroy(dev, intel_sdvo_connector->top);
1732 if (intel_sdvo_connector->bottom)
1733 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1734 if (intel_sdvo_connector->hpos)
1735 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1736 if (intel_sdvo_connector->vpos)
1737 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1738 if (intel_sdvo_connector->saturation)
1739 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1740 if (intel_sdvo_connector->contrast)
1741 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1742 if (intel_sdvo_connector->hue)
1743 drm_property_destroy(dev, intel_sdvo_connector->hue);
1744 if (intel_sdvo_connector->sharpness)
1745 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1746 if (intel_sdvo_connector->flicker_filter)
1747 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1748 if (intel_sdvo_connector->flicker_filter_2d)
1749 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1750 if (intel_sdvo_connector->flicker_filter_adaptive)
1751 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1752 if (intel_sdvo_connector->tv_luma_filter)
1753 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1754 if (intel_sdvo_connector->tv_chroma_filter)
1755 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
1756 if (intel_sdvo_connector->dot_crawl)
1757 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
1758 if (intel_sdvo_connector->brightness)
1759 drm_property_destroy(dev, intel_sdvo_connector->brightness);
1760 }
1761
1762 static void intel_sdvo_destroy(struct drm_connector *connector)
1763 {
1764 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1765
1766 if (intel_sdvo_connector->tv_format)
1767 drm_property_destroy(connector->dev,
1768 intel_sdvo_connector->tv_format);
1769
1770 intel_sdvo_destroy_enhance_property(connector);
1771 drm_sysfs_connector_remove(connector);
1772 drm_connector_cleanup(connector);
1773 kfree(connector);
1774 }
1775
1776 static int
1777 intel_sdvo_set_property(struct drm_connector *connector,
1778 struct drm_property *property,
1779 uint64_t val)
1780 {
1781 struct drm_encoder *encoder = intel_attached_encoder(connector);
1782 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1783 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1784 uint16_t temp_value;
1785 uint8_t cmd;
1786 int ret;
1787
1788 ret = drm_connector_property_set_value(connector, property, val);
1789 if (ret)
1790 return ret;
1791
1792 #define CHECK_PROPERTY(name, NAME) \
1793 if (intel_sdvo_connector->name == property) { \
1794 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1795 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1796 cmd = SDVO_CMD_SET_##NAME; \
1797 intel_sdvo_connector->cur_##name = temp_value; \
1798 goto set_value; \
1799 }
1800
1801 if (property == intel_sdvo_connector->tv_format) {
1802 if (val >= TV_FORMAT_NUM)
1803 return -EINVAL;
1804
1805 if (intel_sdvo->tv_format_index ==
1806 intel_sdvo_connector->tv_format_supported[val])
1807 return 0;
1808
1809 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
1810 goto done;
1811 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
1812 temp_value = val;
1813 if (intel_sdvo_connector->left == property) {
1814 drm_connector_property_set_value(connector,
1815 intel_sdvo_connector->right, val);
1816 if (intel_sdvo_connector->left_margin == temp_value)
1817 return 0;
1818
1819 intel_sdvo_connector->left_margin = temp_value;
1820 intel_sdvo_connector->right_margin = temp_value;
1821 temp_value = intel_sdvo_connector->max_hscan -
1822 intel_sdvo_connector->left_margin;
1823 cmd = SDVO_CMD_SET_OVERSCAN_H;
1824 goto set_value;
1825 } else if (intel_sdvo_connector->right == property) {
1826 drm_connector_property_set_value(connector,
1827 intel_sdvo_connector->left, val);
1828 if (intel_sdvo_connector->right_margin == temp_value)
1829 return 0;
1830
1831 intel_sdvo_connector->left_margin = temp_value;
1832 intel_sdvo_connector->right_margin = temp_value;
1833 temp_value = intel_sdvo_connector->max_hscan -
1834 intel_sdvo_connector->left_margin;
1835 cmd = SDVO_CMD_SET_OVERSCAN_H;
1836 goto set_value;
1837 } else if (intel_sdvo_connector->top == property) {
1838 drm_connector_property_set_value(connector,
1839 intel_sdvo_connector->bottom, val);
1840 if (intel_sdvo_connector->top_margin == temp_value)
1841 return 0;
1842
1843 intel_sdvo_connector->top_margin = temp_value;
1844 intel_sdvo_connector->bottom_margin = temp_value;
1845 temp_value = intel_sdvo_connector->max_vscan -
1846 intel_sdvo_connector->top_margin;
1847 cmd = SDVO_CMD_SET_OVERSCAN_V;
1848 goto set_value;
1849 } else if (intel_sdvo_connector->bottom == property) {
1850 drm_connector_property_set_value(connector,
1851 intel_sdvo_connector->top, val);
1852 if (intel_sdvo_connector->bottom_margin == temp_value)
1853 return 0;
1854
1855 intel_sdvo_connector->top_margin = temp_value;
1856 intel_sdvo_connector->bottom_margin = temp_value;
1857 temp_value = intel_sdvo_connector->max_vscan -
1858 intel_sdvo_connector->top_margin;
1859 cmd = SDVO_CMD_SET_OVERSCAN_V;
1860 goto set_value;
1861 }
1862 CHECK_PROPERTY(hpos, HPOS)
1863 CHECK_PROPERTY(vpos, VPOS)
1864 CHECK_PROPERTY(saturation, SATURATION)
1865 CHECK_PROPERTY(contrast, CONTRAST)
1866 CHECK_PROPERTY(hue, HUE)
1867 CHECK_PROPERTY(brightness, BRIGHTNESS)
1868 CHECK_PROPERTY(sharpness, SHARPNESS)
1869 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1870 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1871 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1872 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1873 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
1874 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
1875 }
1876
1877 return -EINVAL; /* unknown property */
1878
1879 set_value:
1880 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1881 return -EIO;
1882
1883
1884 done:
1885 if (encoder->crtc) {
1886 struct drm_crtc *crtc = encoder->crtc;
1887
1888 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1889 crtc->y, crtc->fb);
1890 }
1891
1892 return 0;
1893 #undef CHECK_PROPERTY
1894 }
1895
1896 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1897 .dpms = intel_sdvo_dpms,
1898 .mode_fixup = intel_sdvo_mode_fixup,
1899 .prepare = intel_encoder_prepare,
1900 .mode_set = intel_sdvo_mode_set,
1901 .commit = intel_encoder_commit,
1902 };
1903
1904 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1905 .dpms = drm_helper_connector_dpms,
1906 .detect = intel_sdvo_detect,
1907 .fill_modes = drm_helper_probe_single_connector_modes,
1908 .set_property = intel_sdvo_set_property,
1909 .destroy = intel_sdvo_destroy,
1910 };
1911
1912 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1913 .get_modes = intel_sdvo_get_modes,
1914 .mode_valid = intel_sdvo_mode_valid,
1915 .best_encoder = intel_attached_encoder,
1916 };
1917
1918 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1919 {
1920 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1921
1922 if (intel_sdvo->analog_ddc_bus)
1923 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
1924
1925 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
1926 drm_mode_destroy(encoder->dev,
1927 intel_sdvo->sdvo_lvds_fixed_mode);
1928
1929 intel_encoder_destroy(encoder);
1930 }
1931
1932 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1933 .destroy = intel_sdvo_enc_destroy,
1934 };
1935
1936
1937 /**
1938 * Choose the appropriate DDC bus for control bus switch command for this
1939 * SDVO output based on the controlled output.
1940 *
1941 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1942 * outputs, then LVDS outputs.
1943 */
1944 static void
1945 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
1946 struct intel_sdvo *sdvo, u32 reg)
1947 {
1948 struct sdvo_device_mapping *mapping;
1949
1950 if (IS_SDVOB(reg))
1951 mapping = &(dev_priv->sdvo_mappings[0]);
1952 else
1953 mapping = &(dev_priv->sdvo_mappings[1]);
1954
1955 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1956 }
1957
1958 static bool
1959 intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
1960 {
1961 return intel_sdvo_set_target_output(intel_sdvo,
1962 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) &&
1963 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1964 &intel_sdvo->is_hdmi, 1);
1965 }
1966
1967 static struct intel_sdvo *
1968 intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan)
1969 {
1970 struct drm_device *dev = chan->drm_dev;
1971 struct drm_encoder *encoder;
1972
1973 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1974 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1975 if (intel_sdvo->base.ddc_bus == &chan->adapter)
1976 return intel_sdvo;
1977 }
1978
1979 return NULL;
1980 }
1981
1982 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
1983 struct i2c_msg msgs[], int num)
1984 {
1985 struct intel_sdvo *intel_sdvo;
1986 struct i2c_algo_bit_data *algo_data;
1987 const struct i2c_algorithm *algo;
1988
1989 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
1990 intel_sdvo =
1991 intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *)
1992 (algo_data->data));
1993 if (intel_sdvo == NULL)
1994 return -EINVAL;
1995
1996 algo = intel_sdvo->base.i2c_bus->algo;
1997
1998 intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus);
1999 return algo->master_xfer(i2c_adap, msgs, num);
2000 }
2001
2002 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2003 .master_xfer = intel_sdvo_master_xfer,
2004 };
2005
2006 static u8
2007 intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
2008 {
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 struct sdvo_device_mapping *my_mapping, *other_mapping;
2011
2012 if (IS_SDVOB(sdvo_reg)) {
2013 my_mapping = &dev_priv->sdvo_mappings[0];
2014 other_mapping = &dev_priv->sdvo_mappings[1];
2015 } else {
2016 my_mapping = &dev_priv->sdvo_mappings[1];
2017 other_mapping = &dev_priv->sdvo_mappings[0];
2018 }
2019
2020 /* If the BIOS described our SDVO device, take advantage of it. */
2021 if (my_mapping->slave_addr)
2022 return my_mapping->slave_addr;
2023
2024 /* If the BIOS only described a different SDVO device, use the
2025 * address that it isn't using.
2026 */
2027 if (other_mapping->slave_addr) {
2028 if (other_mapping->slave_addr == 0x70)
2029 return 0x72;
2030 else
2031 return 0x70;
2032 }
2033
2034 /* No SDVO device info is found for another DVO port,
2035 * so use mapping assumption we had before BIOS parsing.
2036 */
2037 if (IS_SDVOB(sdvo_reg))
2038 return 0x70;
2039 else
2040 return 0x72;
2041 }
2042
2043 static void
2044 intel_sdvo_connector_init(struct drm_encoder *encoder,
2045 struct drm_connector *connector)
2046 {
2047 drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs,
2048 connector->connector_type);
2049
2050 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2051
2052 connector->interlace_allowed = 0;
2053 connector->doublescan_allowed = 0;
2054 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2055
2056 drm_mode_connector_attach_encoder(connector, encoder);
2057 drm_sysfs_connector_add(connector);
2058 }
2059
2060 static bool
2061 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2062 {
2063 struct drm_encoder *encoder = &intel_sdvo->base.enc;
2064 struct drm_connector *connector;
2065 struct intel_connector *intel_connector;
2066 struct intel_sdvo_connector *intel_sdvo_connector;
2067
2068 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2069 if (!intel_sdvo_connector)
2070 return false;
2071
2072 if (device == 0) {
2073 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2074 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2075 } else if (device == 1) {
2076 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2077 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2078 }
2079
2080 intel_connector = &intel_sdvo_connector->base;
2081 connector = &intel_connector->base;
2082 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2083 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2084 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2085
2086 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
2087 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
2088 && intel_sdvo->is_hdmi) {
2089 /* enable hdmi encoding mode if supported */
2090 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2091 intel_sdvo_set_colorimetry(intel_sdvo,
2092 SDVO_COLORIMETRY_RGB256);
2093 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2094 }
2095 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2096 (1 << INTEL_ANALOG_CLONE_BIT));
2097
2098 intel_sdvo_connector_init(encoder, connector);
2099
2100 return true;
2101 }
2102
2103 static bool
2104 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2105 {
2106 struct drm_encoder *encoder = &intel_sdvo->base.enc;
2107 struct drm_connector *connector;
2108 struct intel_connector *intel_connector;
2109 struct intel_sdvo_connector *intel_sdvo_connector;
2110
2111 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2112 if (!intel_sdvo_connector)
2113 return false;
2114
2115 intel_connector = &intel_sdvo_connector->base;
2116 connector = &intel_connector->base;
2117 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2118 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2119
2120 intel_sdvo->controlled_output |= type;
2121 intel_sdvo_connector->output_flag = type;
2122
2123 intel_sdvo->is_tv = true;
2124 intel_sdvo->base.needs_tv_clock = true;
2125 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2126
2127 intel_sdvo_connector_init(encoder, connector);
2128
2129 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2130 goto err;
2131
2132 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2133 goto err;
2134
2135 return true;
2136
2137 err:
2138 intel_sdvo_destroy_enhance_property(connector);
2139 kfree(intel_sdvo_connector);
2140 return false;
2141 }
2142
2143 static bool
2144 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2145 {
2146 struct drm_encoder *encoder = &intel_sdvo->base.enc;
2147 struct drm_connector *connector;
2148 struct intel_connector *intel_connector;
2149 struct intel_sdvo_connector *intel_sdvo_connector;
2150
2151 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2152 if (!intel_sdvo_connector)
2153 return false;
2154
2155 intel_connector = &intel_sdvo_connector->base;
2156 connector = &intel_connector->base;
2157 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2158 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2159 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2160
2161 if (device == 0) {
2162 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2163 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2164 } else if (device == 1) {
2165 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2166 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2167 }
2168
2169 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2170 (1 << INTEL_ANALOG_CLONE_BIT));
2171
2172 intel_sdvo_connector_init(encoder, connector);
2173 return true;
2174 }
2175
2176 static bool
2177 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2178 {
2179 struct drm_encoder *encoder = &intel_sdvo->base.enc;
2180 struct drm_connector *connector;
2181 struct intel_connector *intel_connector;
2182 struct intel_sdvo_connector *intel_sdvo_connector;
2183
2184 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2185 if (!intel_sdvo_connector)
2186 return false;
2187
2188 intel_connector = &intel_sdvo_connector->base;
2189 connector = &intel_connector->base;
2190 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2191 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2192
2193 intel_sdvo->is_lvds = true;
2194
2195 if (device == 0) {
2196 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2197 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2198 } else if (device == 1) {
2199 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2200 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2201 }
2202
2203 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
2204 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
2205
2206 intel_sdvo_connector_init(encoder, connector);
2207 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2208 goto err;
2209
2210 return true;
2211
2212 err:
2213 intel_sdvo_destroy_enhance_property(connector);
2214 kfree(intel_sdvo_connector);
2215 return false;
2216 }
2217
2218 static bool
2219 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
2220 {
2221 intel_sdvo->is_tv = false;
2222 intel_sdvo->base.needs_tv_clock = false;
2223 intel_sdvo->is_lvds = false;
2224
2225 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2226
2227 if (flags & SDVO_OUTPUT_TMDS0)
2228 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2229 return false;
2230
2231 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2232 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2233 return false;
2234
2235 /* TV has no XXX1 function block */
2236 if (flags & SDVO_OUTPUT_SVID0)
2237 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2238 return false;
2239
2240 if (flags & SDVO_OUTPUT_CVBS0)
2241 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2242 return false;
2243
2244 if (flags & SDVO_OUTPUT_RGB0)
2245 if (!intel_sdvo_analog_init(intel_sdvo, 0))
2246 return false;
2247
2248 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2249 if (!intel_sdvo_analog_init(intel_sdvo, 1))
2250 return false;
2251
2252 if (flags & SDVO_OUTPUT_LVDS0)
2253 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2254 return false;
2255
2256 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2257 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2258 return false;
2259
2260 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2261 unsigned char bytes[2];
2262
2263 intel_sdvo->controlled_output = 0;
2264 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2265 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2266 SDVO_NAME(intel_sdvo),
2267 bytes[0], bytes[1]);
2268 return false;
2269 }
2270 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
2271
2272 return true;
2273 }
2274
2275 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2276 struct intel_sdvo_connector *intel_sdvo_connector,
2277 int type)
2278 {
2279 struct drm_device *dev = intel_sdvo->base.enc.dev;
2280 struct intel_sdvo_tv_format format;
2281 uint32_t format_map, i;
2282
2283 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2284 return false;
2285
2286 if (!intel_sdvo_get_value(intel_sdvo,
2287 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2288 &format, sizeof(format)))
2289 return false;
2290
2291 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2292
2293 if (format_map == 0)
2294 return false;
2295
2296 intel_sdvo_connector->format_supported_num = 0;
2297 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2298 if (format_map & (1 << i))
2299 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
2300
2301
2302 intel_sdvo_connector->tv_format =
2303 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2304 "mode", intel_sdvo_connector->format_supported_num);
2305 if (!intel_sdvo_connector->tv_format)
2306 return false;
2307
2308 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2309 drm_property_add_enum(
2310 intel_sdvo_connector->tv_format, i,
2311 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2312
2313 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
2314 drm_connector_attach_property(&intel_sdvo_connector->base.base,
2315 intel_sdvo_connector->tv_format, 0);
2316 return true;
2317
2318 }
2319
2320 #define ENHANCEMENT(name, NAME) do { \
2321 if (enhancements.name) { \
2322 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2323 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2324 return false; \
2325 intel_sdvo_connector->max_##name = data_value[0]; \
2326 intel_sdvo_connector->cur_##name = response; \
2327 intel_sdvo_connector->name = \
2328 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2329 if (!intel_sdvo_connector->name) return false; \
2330 intel_sdvo_connector->name->values[0] = 0; \
2331 intel_sdvo_connector->name->values[1] = data_value[0]; \
2332 drm_connector_attach_property(connector, \
2333 intel_sdvo_connector->name, \
2334 intel_sdvo_connector->cur_##name); \
2335 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2336 data_value[0], data_value[1], response); \
2337 } \
2338 } while(0)
2339
2340 static bool
2341 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2342 struct intel_sdvo_connector *intel_sdvo_connector,
2343 struct intel_sdvo_enhancements_reply enhancements)
2344 {
2345 struct drm_device *dev = intel_sdvo->base.enc.dev;
2346 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2347 uint16_t response, data_value[2];
2348
2349 /* when horizontal overscan is supported, Add the left/right property */
2350 if (enhancements.overscan_h) {
2351 if (!intel_sdvo_get_value(intel_sdvo,
2352 SDVO_CMD_GET_MAX_OVERSCAN_H,
2353 &data_value, 4))
2354 return false;
2355
2356 if (!intel_sdvo_get_value(intel_sdvo,
2357 SDVO_CMD_GET_OVERSCAN_H,
2358 &response, 2))
2359 return false;
2360
2361 intel_sdvo_connector->max_hscan = data_value[0];
2362 intel_sdvo_connector->left_margin = data_value[0] - response;
2363 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2364 intel_sdvo_connector->left =
2365 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2366 "left_margin", 2);
2367 if (!intel_sdvo_connector->left)
2368 return false;
2369
2370 intel_sdvo_connector->left->values[0] = 0;
2371 intel_sdvo_connector->left->values[1] = data_value[0];
2372 drm_connector_attach_property(connector,
2373 intel_sdvo_connector->left,
2374 intel_sdvo_connector->left_margin);
2375
2376 intel_sdvo_connector->right =
2377 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2378 "right_margin", 2);
2379 if (!intel_sdvo_connector->right)
2380 return false;
2381
2382 intel_sdvo_connector->right->values[0] = 0;
2383 intel_sdvo_connector->right->values[1] = data_value[0];
2384 drm_connector_attach_property(connector,
2385 intel_sdvo_connector->right,
2386 intel_sdvo_connector->right_margin);
2387 DRM_DEBUG_KMS("h_overscan: max %d, "
2388 "default %d, current %d\n",
2389 data_value[0], data_value[1], response);
2390 }
2391
2392 if (enhancements.overscan_v) {
2393 if (!intel_sdvo_get_value(intel_sdvo,
2394 SDVO_CMD_GET_MAX_OVERSCAN_V,
2395 &data_value, 4))
2396 return false;
2397
2398 if (!intel_sdvo_get_value(intel_sdvo,
2399 SDVO_CMD_GET_OVERSCAN_V,
2400 &response, 2))
2401 return false;
2402
2403 intel_sdvo_connector->max_vscan = data_value[0];
2404 intel_sdvo_connector->top_margin = data_value[0] - response;
2405 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2406 intel_sdvo_connector->top =
2407 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2408 "top_margin", 2);
2409 if (!intel_sdvo_connector->top)
2410 return false;
2411
2412 intel_sdvo_connector->top->values[0] = 0;
2413 intel_sdvo_connector->top->values[1] = data_value[0];
2414 drm_connector_attach_property(connector,
2415 intel_sdvo_connector->top,
2416 intel_sdvo_connector->top_margin);
2417
2418 intel_sdvo_connector->bottom =
2419 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2420 "bottom_margin", 2);
2421 if (!intel_sdvo_connector->bottom)
2422 return false;
2423
2424 intel_sdvo_connector->bottom->values[0] = 0;
2425 intel_sdvo_connector->bottom->values[1] = data_value[0];
2426 drm_connector_attach_property(connector,
2427 intel_sdvo_connector->bottom,
2428 intel_sdvo_connector->bottom_margin);
2429 DRM_DEBUG_KMS("v_overscan: max %d, "
2430 "default %d, current %d\n",
2431 data_value[0], data_value[1], response);
2432 }
2433
2434 ENHANCEMENT(hpos, HPOS);
2435 ENHANCEMENT(vpos, VPOS);
2436 ENHANCEMENT(saturation, SATURATION);
2437 ENHANCEMENT(contrast, CONTRAST);
2438 ENHANCEMENT(hue, HUE);
2439 ENHANCEMENT(sharpness, SHARPNESS);
2440 ENHANCEMENT(brightness, BRIGHTNESS);
2441 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2442 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2443 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2444 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2445 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
2446
2447 if (enhancements.dot_crawl) {
2448 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2449 return false;
2450
2451 intel_sdvo_connector->max_dot_crawl = 1;
2452 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2453 intel_sdvo_connector->dot_crawl =
2454 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2455 if (!intel_sdvo_connector->dot_crawl)
2456 return false;
2457
2458 intel_sdvo_connector->dot_crawl->values[0] = 0;
2459 intel_sdvo_connector->dot_crawl->values[1] = 1;
2460 drm_connector_attach_property(connector,
2461 intel_sdvo_connector->dot_crawl,
2462 intel_sdvo_connector->cur_dot_crawl);
2463 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2464 }
2465
2466 return true;
2467 }
2468
2469 static bool
2470 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2471 struct intel_sdvo_connector *intel_sdvo_connector,
2472 struct intel_sdvo_enhancements_reply enhancements)
2473 {
2474 struct drm_device *dev = intel_sdvo->base.enc.dev;
2475 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2476 uint16_t response, data_value[2];
2477
2478 ENHANCEMENT(brightness, BRIGHTNESS);
2479
2480 return true;
2481 }
2482 #undef ENHANCEMENT
2483
2484 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2485 struct intel_sdvo_connector *intel_sdvo_connector)
2486 {
2487 union {
2488 struct intel_sdvo_enhancements_reply reply;
2489 uint16_t response;
2490 } enhancements;
2491
2492 if (!intel_sdvo_get_value(intel_sdvo,
2493 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2494 &enhancements, sizeof(enhancements)))
2495 return false;
2496
2497 if (enhancements.response == 0) {
2498 DRM_DEBUG_KMS("No enhancement is supported\n");
2499 return true;
2500 }
2501
2502 if (IS_TV(intel_sdvo_connector))
2503 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2504 else if(IS_LVDS(intel_sdvo_connector))
2505 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2506 else
2507 return true;
2508
2509 }
2510
2511 bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2512 {
2513 struct drm_i915_private *dev_priv = dev->dev_private;
2514 struct intel_encoder *intel_encoder;
2515 struct intel_sdvo *intel_sdvo;
2516 u8 ch[0x40];
2517 int i;
2518 u32 i2c_reg, ddc_reg, analog_ddc_reg;
2519
2520 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2521 if (!intel_sdvo)
2522 return false;
2523
2524 intel_sdvo->sdvo_reg = sdvo_reg;
2525
2526 intel_encoder = &intel_sdvo->base;
2527 intel_encoder->type = INTEL_OUTPUT_SDVO;
2528
2529 if (HAS_PCH_SPLIT(dev)) {
2530 i2c_reg = PCH_GPIOE;
2531 ddc_reg = PCH_GPIOE;
2532 analog_ddc_reg = PCH_GPIOA;
2533 } else {
2534 i2c_reg = GPIOE;
2535 ddc_reg = GPIOE;
2536 analog_ddc_reg = GPIOA;
2537 }
2538
2539 /* setup the DDC bus. */
2540 if (IS_SDVOB(sdvo_reg))
2541 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB");
2542 else
2543 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC");
2544
2545 if (!intel_encoder->i2c_bus)
2546 goto err_inteloutput;
2547
2548 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
2549
2550 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2551 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
2552
2553 /* Read the regs to test if we can talk to the device */
2554 for (i = 0; i < 0x40; i++) {
2555 if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) {
2556 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2557 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
2558 goto err_i2c;
2559 }
2560 }
2561
2562 /* setup the DDC bus. */
2563 if (IS_SDVOB(sdvo_reg)) {
2564 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
2565 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
2566 "SDVOB/VGA DDC BUS");
2567 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
2568 } else {
2569 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
2570 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
2571 "SDVOC/VGA DDC BUS");
2572 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
2573 }
2574 if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL)
2575 goto err_i2c;
2576
2577 /* Wrap with our custom algo which switches to DDC mode */
2578 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2579
2580 /* encoder type will be decided later */
2581 drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0);
2582 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
2583
2584 /* In default case sdvo lvds is false */
2585 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2586 goto err_enc;
2587
2588 if (intel_sdvo_output_setup(intel_sdvo,
2589 intel_sdvo->caps.output_flags) != true) {
2590 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2591 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
2592 goto err_enc;
2593 }
2594
2595 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
2596
2597 /* Set the input timing to the screen. Assume always input 0. */
2598 if (!intel_sdvo_set_target_input(intel_sdvo))
2599 goto err_enc;
2600
2601 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2602 &intel_sdvo->pixel_clock_min,
2603 &intel_sdvo->pixel_clock_max))
2604 goto err_enc;
2605
2606 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2607 "clock range %dMHz - %dMHz, "
2608 "input 1: %c, input 2: %c, "
2609 "output 1: %c, output 2: %c\n",
2610 SDVO_NAME(intel_sdvo),
2611 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2612 intel_sdvo->caps.device_rev_id,
2613 intel_sdvo->pixel_clock_min / 1000,
2614 intel_sdvo->pixel_clock_max / 1000,
2615 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2616 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2617 /* check currently supported outputs */
2618 intel_sdvo->caps.output_flags &
2619 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2620 intel_sdvo->caps.output_flags &
2621 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2622 return true;
2623
2624 err_enc:
2625 drm_encoder_cleanup(&intel_encoder->enc);
2626 err_i2c:
2627 if (intel_sdvo->analog_ddc_bus != NULL)
2628 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
2629 if (intel_encoder->ddc_bus != NULL)
2630 intel_i2c_destroy(intel_encoder->ddc_bus);
2631 if (intel_encoder->i2c_bus != NULL)
2632 intel_i2c_destroy(intel_encoder->i2c_bus);
2633 err_inteloutput:
2634 kfree(intel_sdvo);
2635
2636 return false;
2637 }
Linux kernel - Deliverables
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