2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
28 #include <linux/i2c.h>
29 #include <linux/delay.h>
33 #include "intel_drv.h"
36 #include "intel_sdvo_regs.h"
40 struct intel_sdvo_priv
{
41 struct intel_i2c_chan
*i2c_bus
;
44 /* Register for the SDVO device: SDVOB or SDVOC */
47 /* Active outputs controlled by this SDVO output */
48 uint16_t controlled_output
;
51 * Capabilities of the SDVO device returned by
52 * i830_sdvo_get_capabilities()
54 struct intel_sdvo_caps caps
;
56 /* Pixel clock limitations reported by the SDVO device, in kHz */
57 int pixel_clock_min
, pixel_clock_max
;
60 * This is set if we're going to treat the device as TV-out.
62 * While we have these nice friendly flags for output types that ought
63 * to decide this for us, the S-Video output on our HDMI+S-Video card
64 * shows up as RGB1 (VGA).
69 * This is set if we treat the device as HDMI, instead of DVI.
74 * Returned SDTV resolutions allowed for the current format, if the
77 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions
;
80 * Current selected TV format.
82 * This is stored in the same structure that's passed to the device, for
85 struct intel_sdvo_tv_format tv_format
;
88 * supported encoding mode, used to determine whether HDMI is
91 struct intel_sdvo_encode encode
;
93 /* DDC bus used by this SDVO output */
97 u16 save_active_outputs
;
98 struct intel_sdvo_dtd save_input_dtd_1
, save_input_dtd_2
;
99 struct intel_sdvo_dtd save_output_dtd
[16];
104 * Writes the SDVOB or SDVOC with the given value, but always writes both
105 * SDVOB and SDVOC to work around apparent hardware issues (according to
106 * comments in the BIOS).
108 static void intel_sdvo_write_sdvox(struct intel_output
*intel_output
, u32 val
)
110 struct drm_device
*dev
= intel_output
->base
.dev
;
111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
112 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
113 u32 bval
= val
, cval
= val
;
116 if (sdvo_priv
->output_device
== SDVOB
) {
117 cval
= I915_READ(SDVOC
);
119 bval
= I915_READ(SDVOB
);
122 * Write the registers twice for luck. Sometimes,
123 * writing them only once doesn't appear to 'stick'.
124 * The BIOS does this too. Yay, magic
126 for (i
= 0; i
< 2; i
++)
128 I915_WRITE(SDVOB
, bval
);
130 I915_WRITE(SDVOC
, cval
);
135 static bool intel_sdvo_read_byte(struct intel_output
*intel_output
, u8 addr
,
138 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
143 struct i2c_msg msgs
[] = {
145 .addr
= sdvo_priv
->i2c_bus
->slave_addr
,
151 .addr
= sdvo_priv
->i2c_bus
->slave_addr
,
161 if ((ret
= i2c_transfer(&sdvo_priv
->i2c_bus
->adapter
, msgs
, 2)) == 2)
167 DRM_DEBUG("i2c transfer returned %d\n", ret
);
171 static bool intel_sdvo_write_byte(struct intel_output
*intel_output
, int addr
,
175 struct i2c_msg msgs
[] = {
177 .addr
= intel_output
->i2c_bus
->slave_addr
,
187 if (i2c_transfer(&intel_output
->i2c_bus
->adapter
, msgs
, 1) == 1)
194 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
195 /** Mapping of command numbers to names, for debug output */
196 static const struct _sdvo_cmd_name
{
199 } sdvo_cmd_names
[] = {
200 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET
),
201 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS
),
202 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV
),
203 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS
),
204 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS
),
205 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS
),
206 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP
),
207 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP
),
208 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS
),
209 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT
),
210 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG
),
211 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG
),
212 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE
),
213 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT
),
214 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT
),
215 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1
),
216 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2
),
217 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1
),
218 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2
),
219 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1
),
220 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1
),
221 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2
),
222 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1
),
223 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2
),
224 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING
),
225 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1
),
226 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2
),
227 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE
),
228 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE
),
229 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS
),
230 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT
),
231 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT
),
232 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS
),
233 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT
),
234 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT
),
235 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES
),
236 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE
),
237 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE
),
238 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE
),
239 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH
),
240 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT
),
241 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT
),
242 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS
),
244 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE
),
245 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE
),
246 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE
),
247 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI
),
248 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI
),
249 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP
),
250 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY
),
251 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY
),
252 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER
),
253 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT
),
254 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT
),
255 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX
),
256 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX
),
257 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO
),
258 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT
),
259 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT
),
260 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE
),
261 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE
),
262 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA
),
263 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA
),
266 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
267 #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
270 static void intel_sdvo_debug_write(struct intel_output
*intel_output
, u8 cmd
,
271 void *args
, int args_len
)
273 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
276 printk(KERN_DEBUG
"%s: W: %02X ", SDVO_NAME(sdvo_priv
), cmd
);
277 for (i
= 0; i
< args_len
; i
++)
278 printk(KERN_DEBUG
"%02X ", ((u8
*)args
)[i
]);
280 printk(KERN_DEBUG
" ");
281 for (i
= 0; i
< sizeof(sdvo_cmd_names
) / sizeof(sdvo_cmd_names
[0]); i
++) {
282 if (cmd
== sdvo_cmd_names
[i
].cmd
) {
283 printk(KERN_DEBUG
"(%s)", sdvo_cmd_names
[i
].name
);
287 if (i
== sizeof(sdvo_cmd_names
)/ sizeof(sdvo_cmd_names
[0]))
288 printk(KERN_DEBUG
"(%02X)", cmd
);
289 printk(KERN_DEBUG
"\n");
292 #define intel_sdvo_debug_write(o, c, a, l)
295 static void intel_sdvo_write_cmd(struct intel_output
*intel_output
, u8 cmd
,
296 void *args
, int args_len
)
300 intel_sdvo_debug_write(intel_output
, cmd
, args
, args_len
);
302 for (i
= 0; i
< args_len
; i
++) {
303 intel_sdvo_write_byte(intel_output
, SDVO_I2C_ARG_0
- i
,
307 intel_sdvo_write_byte(intel_output
, SDVO_I2C_OPCODE
, cmd
);
311 static const char *cmd_status_names
[] = {
317 "Target not specified",
318 "Scaling not supported"
321 static void intel_sdvo_debug_response(struct intel_output
*intel_output
,
322 void *response
, int response_len
,
325 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
328 printk(KERN_DEBUG
"%s: R: ", SDVO_NAME(sdvo_priv
));
329 for (i
= 0; i
< response_len
; i
++)
330 printk(KERN_DEBUG
"%02X ", ((u8
*)response
)[i
]);
332 printk(KERN_DEBUG
" ");
333 if (status
<= SDVO_CMD_STATUS_SCALING_NOT_SUPP
)
334 printk(KERN_DEBUG
"(%s)", cmd_status_names
[status
]);
336 printk(KERN_DEBUG
"(??? %d)", status
);
337 printk(KERN_DEBUG
"\n");
340 #define intel_sdvo_debug_response(o, r, l, s)
343 static u8
intel_sdvo_read_response(struct intel_output
*intel_output
,
344 void *response
, int response_len
)
351 /* Read the command response */
352 for (i
= 0; i
< response_len
; i
++) {
353 intel_sdvo_read_byte(intel_output
,
354 SDVO_I2C_RETURN_0
+ i
,
355 &((u8
*)response
)[i
]);
358 /* read the return status */
359 intel_sdvo_read_byte(intel_output
, SDVO_I2C_CMD_STATUS
,
362 intel_sdvo_debug_response(intel_output
, response
, response_len
,
364 if (status
!= SDVO_CMD_STATUS_PENDING
)
373 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode
*mode
)
375 if (mode
->clock
>= 100000)
377 else if (mode
->clock
>= 50000)
384 * Don't check status code from this as it switches the bus back to the
385 * SDVO chips which defeats the purpose of doing a bus switch in the first
388 static void intel_sdvo_set_control_bus_switch(struct intel_output
*intel_output
,
391 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_CONTROL_BUS_SWITCH
, &target
, 1);
394 static bool intel_sdvo_set_target_input(struct intel_output
*intel_output
, bool target_0
, bool target_1
)
396 struct intel_sdvo_set_target_input_args targets
= {0};
399 if (target_0
&& target_1
)
400 return SDVO_CMD_STATUS_NOTSUPP
;
403 targets
.target_1
= 1;
405 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_TARGET_INPUT
, &targets
,
408 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
410 return (status
== SDVO_CMD_STATUS_SUCCESS
);
414 * Return whether each input is trained.
416 * This function is making an assumption about the layout of the response,
417 * which should be checked against the docs.
419 static bool intel_sdvo_get_trained_inputs(struct intel_output
*intel_output
, bool *input_1
, bool *input_2
)
421 struct intel_sdvo_get_trained_inputs_response response
;
424 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_TRAINED_INPUTS
, NULL
, 0);
425 status
= intel_sdvo_read_response(intel_output
, &response
, sizeof(response
));
426 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
429 *input_1
= response
.input0_trained
;
430 *input_2
= response
.input1_trained
;
434 static bool intel_sdvo_get_active_outputs(struct intel_output
*intel_output
,
439 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_ACTIVE_OUTPUTS
, NULL
, 0);
440 status
= intel_sdvo_read_response(intel_output
, outputs
, sizeof(*outputs
));
442 return (status
== SDVO_CMD_STATUS_SUCCESS
);
445 static bool intel_sdvo_set_active_outputs(struct intel_output
*intel_output
,
450 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_ACTIVE_OUTPUTS
, &outputs
,
452 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
453 return (status
== SDVO_CMD_STATUS_SUCCESS
);
456 static bool intel_sdvo_set_encoder_power_state(struct intel_output
*intel_output
,
459 u8 status
, state
= SDVO_ENCODER_STATE_ON
;
462 case DRM_MODE_DPMS_ON
:
463 state
= SDVO_ENCODER_STATE_ON
;
465 case DRM_MODE_DPMS_STANDBY
:
466 state
= SDVO_ENCODER_STATE_STANDBY
;
468 case DRM_MODE_DPMS_SUSPEND
:
469 state
= SDVO_ENCODER_STATE_SUSPEND
;
471 case DRM_MODE_DPMS_OFF
:
472 state
= SDVO_ENCODER_STATE_OFF
;
476 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_ENCODER_POWER_STATE
, &state
,
478 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
480 return (status
== SDVO_CMD_STATUS_SUCCESS
);
483 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output
*intel_output
,
487 struct intel_sdvo_pixel_clock_range clocks
;
490 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE
,
493 status
= intel_sdvo_read_response(intel_output
, &clocks
, sizeof(clocks
));
495 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
498 /* Convert the values from units of 10 kHz to kHz. */
499 *clock_min
= clocks
.min
* 10;
500 *clock_max
= clocks
.max
* 10;
505 static bool intel_sdvo_set_target_output(struct intel_output
*intel_output
,
510 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_TARGET_OUTPUT
, &outputs
,
513 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
514 return (status
== SDVO_CMD_STATUS_SUCCESS
);
517 static bool intel_sdvo_get_timing(struct intel_output
*intel_output
, u8 cmd
,
518 struct intel_sdvo_dtd
*dtd
)
522 intel_sdvo_write_cmd(intel_output
, cmd
, NULL
, 0);
523 status
= intel_sdvo_read_response(intel_output
, &dtd
->part1
,
525 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
528 intel_sdvo_write_cmd(intel_output
, cmd
+ 1, NULL
, 0);
529 status
= intel_sdvo_read_response(intel_output
, &dtd
->part2
,
531 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
537 static bool intel_sdvo_get_input_timing(struct intel_output
*intel_output
,
538 struct intel_sdvo_dtd
*dtd
)
540 return intel_sdvo_get_timing(intel_output
,
541 SDVO_CMD_GET_INPUT_TIMINGS_PART1
, dtd
);
544 static bool intel_sdvo_get_output_timing(struct intel_output
*intel_output
,
545 struct intel_sdvo_dtd
*dtd
)
547 return intel_sdvo_get_timing(intel_output
,
548 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1
, dtd
);
551 static bool intel_sdvo_set_timing(struct intel_output
*intel_output
, u8 cmd
,
552 struct intel_sdvo_dtd
*dtd
)
556 intel_sdvo_write_cmd(intel_output
, cmd
, &dtd
->part1
, sizeof(dtd
->part1
));
557 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
558 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
561 intel_sdvo_write_cmd(intel_output
, cmd
+ 1, &dtd
->part2
, sizeof(dtd
->part2
));
562 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
563 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
569 static bool intel_sdvo_set_input_timing(struct intel_output
*intel_output
,
570 struct intel_sdvo_dtd
*dtd
)
572 return intel_sdvo_set_timing(intel_output
,
573 SDVO_CMD_SET_INPUT_TIMINGS_PART1
, dtd
);
576 static bool intel_sdvo_set_output_timing(struct intel_output
*intel_output
,
577 struct intel_sdvo_dtd
*dtd
)
579 return intel_sdvo_set_timing(intel_output
,
580 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1
, dtd
);
584 intel_sdvo_create_preferred_input_timing(struct intel_output
*output
,
589 struct intel_sdvo_preferred_input_timing_args args
;
592 memset(&args
, 0, sizeof(args
));
595 args
.height
= height
;
598 intel_sdvo_write_cmd(output
, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING
,
599 &args
, sizeof(args
));
600 status
= intel_sdvo_read_response(output
, NULL
, 0);
601 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
607 static bool intel_sdvo_get_preferred_input_timing(struct intel_output
*output
,
608 struct intel_sdvo_dtd
*dtd
)
612 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1
,
615 status
= intel_sdvo_read_response(output
, &dtd
->part1
,
617 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
620 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2
,
623 status
= intel_sdvo_read_response(output
, &dtd
->part2
,
625 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
631 static int intel_sdvo_get_clock_rate_mult(struct intel_output
*intel_output
)
635 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_CLOCK_RATE_MULT
, NULL
, 0);
636 status
= intel_sdvo_read_response(intel_output
, &response
, 1);
638 if (status
!= SDVO_CMD_STATUS_SUCCESS
) {
639 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
640 return SDVO_CLOCK_RATE_MULT_1X
;
642 DRM_DEBUG("Current clock rate multiplier: %d\n", response
);
648 static bool intel_sdvo_set_clock_rate_mult(struct intel_output
*intel_output
, u8 val
)
652 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_CLOCK_RATE_MULT
, &val
, 1);
653 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
654 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
660 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd
*dtd
,
661 struct drm_display_mode
*mode
)
663 uint16_t width
, height
;
664 uint16_t h_blank_len
, h_sync_len
, v_blank_len
, v_sync_len
;
665 uint16_t h_sync_offset
, v_sync_offset
;
667 width
= mode
->crtc_hdisplay
;
668 height
= mode
->crtc_vdisplay
;
670 /* do some mode translations */
671 h_blank_len
= mode
->crtc_hblank_end
- mode
->crtc_hblank_start
;
672 h_sync_len
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
674 v_blank_len
= mode
->crtc_vblank_end
- mode
->crtc_vblank_start
;
675 v_sync_len
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
677 h_sync_offset
= mode
->crtc_hsync_start
- mode
->crtc_hblank_start
;
678 v_sync_offset
= mode
->crtc_vsync_start
- mode
->crtc_vblank_start
;
680 dtd
->part1
.clock
= mode
->clock
/ 10;
681 dtd
->part1
.h_active
= width
& 0xff;
682 dtd
->part1
.h_blank
= h_blank_len
& 0xff;
683 dtd
->part1
.h_high
= (((width
>> 8) & 0xf) << 4) |
684 ((h_blank_len
>> 8) & 0xf);
685 dtd
->part1
.v_active
= height
& 0xff;
686 dtd
->part1
.v_blank
= v_blank_len
& 0xff;
687 dtd
->part1
.v_high
= (((height
>> 8) & 0xf) << 4) |
688 ((v_blank_len
>> 8) & 0xf);
690 dtd
->part2
.h_sync_off
= h_sync_offset
& 0xff;
691 dtd
->part2
.h_sync_width
= h_sync_len
& 0xff;
692 dtd
->part2
.v_sync_off_width
= (v_sync_offset
& 0xf) << 4 |
694 dtd
->part2
.sync_off_width_high
= ((h_sync_offset
& 0x300) >> 2) |
695 ((h_sync_len
& 0x300) >> 4) | ((v_sync_offset
& 0x30) >> 2) |
696 ((v_sync_len
& 0x30) >> 4);
698 dtd
->part2
.dtd_flags
= 0x18;
699 if (mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
700 dtd
->part2
.dtd_flags
|= 0x2;
701 if (mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
702 dtd
->part2
.dtd_flags
|= 0x4;
704 dtd
->part2
.sdvo_flags
= 0;
705 dtd
->part2
.v_sync_off_high
= v_sync_offset
& 0xc0;
706 dtd
->part2
.reserved
= 0;
709 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode
* mode
,
710 struct intel_sdvo_dtd
*dtd
)
712 mode
->hdisplay
= dtd
->part1
.h_active
;
713 mode
->hdisplay
+= ((dtd
->part1
.h_high
>> 4) & 0x0f) << 8;
714 mode
->hsync_start
= mode
->hdisplay
+ dtd
->part2
.h_sync_off
;
715 mode
->hsync_start
+= (dtd
->part2
.sync_off_width_high
& 0xc0) << 2;
716 mode
->hsync_end
= mode
->hsync_start
+ dtd
->part2
.h_sync_width
;
717 mode
->hsync_end
+= (dtd
->part2
.sync_off_width_high
& 0x30) << 4;
718 mode
->htotal
= mode
->hdisplay
+ dtd
->part1
.h_blank
;
719 mode
->htotal
+= (dtd
->part1
.h_high
& 0xf) << 8;
721 mode
->vdisplay
= dtd
->part1
.v_active
;
722 mode
->vdisplay
+= ((dtd
->part1
.v_high
>> 4) & 0x0f) << 8;
723 mode
->vsync_start
= mode
->vdisplay
;
724 mode
->vsync_start
+= (dtd
->part2
.v_sync_off_width
>> 4) & 0xf;
725 mode
->vsync_start
+= (dtd
->part2
.sync_off_width_high
& 0x0c) << 2;
726 mode
->vsync_start
+= dtd
->part2
.v_sync_off_high
& 0xc0;
727 mode
->vsync_end
= mode
->vsync_start
+
728 (dtd
->part2
.v_sync_off_width
& 0xf);
729 mode
->vsync_end
+= (dtd
->part2
.sync_off_width_high
& 0x3) << 4;
730 mode
->vtotal
= mode
->vdisplay
+ dtd
->part1
.v_blank
;
731 mode
->vtotal
+= (dtd
->part1
.v_high
& 0xf) << 8;
733 mode
->clock
= dtd
->part1
.clock
* 10;
735 mode
->flags
&= ~(DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
);
736 if (dtd
->part2
.dtd_flags
& 0x2)
737 mode
->flags
|= DRM_MODE_FLAG_PHSYNC
;
738 if (dtd
->part2
.dtd_flags
& 0x4)
739 mode
->flags
|= DRM_MODE_FLAG_PVSYNC
;
742 static bool intel_sdvo_get_supp_encode(struct intel_output
*output
,
743 struct intel_sdvo_encode
*encode
)
747 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_SUPP_ENCODE
, NULL
, 0);
748 status
= intel_sdvo_read_response(output
, encode
, sizeof(*encode
));
749 if (status
!= SDVO_CMD_STATUS_SUCCESS
) { /* non-support means DVI */
750 memset(encode
, 0, sizeof(*encode
));
757 static bool intel_sdvo_set_encode(struct intel_output
*output
, uint8_t mode
)
761 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_ENCODE
, &mode
, 1);
762 status
= intel_sdvo_read_response(output
, NULL
, 0);
764 return (status
== SDVO_CMD_STATUS_SUCCESS
);
767 static bool intel_sdvo_set_colorimetry(struct intel_output
*output
,
772 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_COLORIMETRY
, &mode
, 1);
773 status
= intel_sdvo_read_response(output
, NULL
, 0);
775 return (status
== SDVO_CMD_STATUS_SUCCESS
);
779 static void intel_sdvo_dump_hdmi_buf(struct intel_output
*output
)
782 uint8_t set_buf_index
[2];
788 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_HBUF_AV_SPLIT
, NULL
, 0);
789 intel_sdvo_read_response(output
, &av_split
, 1);
791 for (i
= 0; i
<= av_split
; i
++) {
792 set_buf_index
[0] = i
; set_buf_index
[1] = 0;
793 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_HBUF_INDEX
,
795 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_HBUF_INFO
, NULL
, 0);
796 intel_sdvo_read_response(output
, &buf_size
, 1);
799 for (j
= 0; j
<= buf_size
; j
+= 8) {
800 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_HBUF_DATA
,
802 intel_sdvo_read_response(output
, pos
, 8);
809 static void intel_sdvo_set_hdmi_buf(struct intel_output
*output
, int index
,
810 uint8_t *data
, int8_t size
, uint8_t tx_rate
)
812 uint8_t set_buf_index
[2];
814 set_buf_index
[0] = index
;
815 set_buf_index
[1] = 0;
817 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_HBUF_INDEX
, set_buf_index
, 2);
819 for (; size
> 0; size
-= 8) {
820 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_HBUF_DATA
, data
, 8);
824 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_HBUF_TXRATE
, &tx_rate
, 1);
827 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data
, uint8_t size
)
832 for (i
= 0; i
< size
; i
++)
838 #define DIP_TYPE_AVI 0x82
839 #define DIP_VERSION_AVI 0x2
840 #define DIP_LEN_AVI 13
842 struct dip_infoframe
{
870 /* Packet Byte #6~13 */
871 uint16_t top_bar_end
;
872 uint16_t bottom_bar_start
;
873 uint16_t left_bar_end
;
874 uint16_t right_bar_start
;
878 uint8_t channel_count
:3;
880 uint8_t coding_type
:4;
882 uint8_t sample_size
:2; /* SS0, SS1 */
883 uint8_t sample_frequency
:3;
886 uint8_t coding_type_private
:5;
889 uint8_t channel_allocation
;
892 uint8_t level_shift
:4;
893 uint8_t downmix_inhibit
:1;
896 } __attribute__ ((packed
)) u
;
897 } __attribute__((packed
));
899 static void intel_sdvo_set_avi_infoframe(struct intel_output
*output
,
900 struct drm_display_mode
* mode
)
902 struct dip_infoframe avi_if
= {
903 .type
= DIP_TYPE_AVI
,
904 .version
= DIP_VERSION_AVI
,
908 avi_if
.checksum
= intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if
,
910 intel_sdvo_set_hdmi_buf(output
, 1, (uint8_t *)&avi_if
, 4 + avi_if
.len
,
914 static void intel_sdvo_set_tv_format(struct intel_output
*output
)
916 struct intel_sdvo_priv
*sdvo_priv
= output
->dev_priv
;
917 struct intel_sdvo_tv_format
*format
, unset
;
920 format
= &sdvo_priv
->tv_format
;
921 memset(&unset
, 0, sizeof(unset
));
922 if (memcmp(format
, &unset
, sizeof(*format
))) {
923 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
924 SDVO_NAME(sdvo_priv
));
926 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_TV_FORMAT
, format
,
928 status
= intel_sdvo_read_response(output
, NULL
, 0);
929 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
930 DRM_DEBUG("%s: Failed to set TV format\n",
931 SDVO_NAME(sdvo_priv
));
935 static bool intel_sdvo_mode_fixup(struct drm_encoder
*encoder
,
936 struct drm_display_mode
*mode
,
937 struct drm_display_mode
*adjusted_mode
)
939 struct intel_output
*output
= enc_to_intel_output(encoder
);
940 struct intel_sdvo_priv
*dev_priv
= output
->dev_priv
;
942 if (!dev_priv
->is_tv
) {
943 /* Make the CRTC code factor in the SDVO pixel multiplier. The
944 * SDVO device will be told of the multiplier during mode_set.
946 adjusted_mode
->clock
*= intel_sdvo_get_pixel_multiplier(mode
);
948 struct intel_sdvo_dtd output_dtd
;
951 /* We need to construct preferred input timings based on our
952 * output timings. To do that, we have to set the output
953 * timings, even though this isn't really the right place in
954 * the sequence to do it. Oh well.
958 /* Set output timings */
959 intel_sdvo_get_dtd_from_mode(&output_dtd
, mode
);
960 intel_sdvo_set_target_output(output
,
961 dev_priv
->controlled_output
);
962 intel_sdvo_set_output_timing(output
, &output_dtd
);
964 /* Set the input timing to the screen. Assume always input 0. */
965 intel_sdvo_set_target_input(output
, true, false);
968 success
= intel_sdvo_create_preferred_input_timing(output
,
973 struct intel_sdvo_dtd input_dtd
;
975 intel_sdvo_get_preferred_input_timing(output
,
977 intel_sdvo_get_mode_from_dtd(adjusted_mode
, &input_dtd
);
979 drm_mode_set_crtcinfo(adjusted_mode
, 0);
981 mode
->clock
= adjusted_mode
->clock
;
983 adjusted_mode
->clock
*=
984 intel_sdvo_get_pixel_multiplier(mode
);
992 static void intel_sdvo_mode_set(struct drm_encoder
*encoder
,
993 struct drm_display_mode
*mode
,
994 struct drm_display_mode
*adjusted_mode
)
996 struct drm_device
*dev
= encoder
->dev
;
997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
998 struct drm_crtc
*crtc
= encoder
->crtc
;
999 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1000 struct intel_output
*output
= enc_to_intel_output(encoder
);
1001 struct intel_sdvo_priv
*sdvo_priv
= output
->dev_priv
;
1003 int sdvo_pixel_multiply
;
1004 struct intel_sdvo_in_out_map in_out
;
1005 struct intel_sdvo_dtd input_dtd
;
1011 /* First, set the input mapping for the first input to our controlled
1012 * output. This is only correct if we're a single-input device, in
1013 * which case the first input is the output from the appropriate SDVO
1014 * channel on the motherboard. In a two-input device, the first input
1015 * will be SDVOB and the second SDVOC.
1017 in_out
.in0
= sdvo_priv
->controlled_output
;
1020 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_IN_OUT_MAP
,
1021 &in_out
, sizeof(in_out
));
1022 status
= intel_sdvo_read_response(output
, NULL
, 0);
1024 if (sdvo_priv
->is_hdmi
) {
1025 intel_sdvo_set_avi_infoframe(output
, mode
);
1026 sdvox
|= SDVO_AUDIO_ENABLE
;
1029 /* We have tried to get input timing in mode_fixup, and filled into
1031 if (sdvo_priv
->is_tv
)
1032 intel_sdvo_get_dtd_from_mode(&input_dtd
, adjusted_mode
);
1034 intel_sdvo_get_dtd_from_mode(&input_dtd
, mode
);
1036 /* If it's a TV, we already set the output timing in mode_fixup.
1037 * Otherwise, the output timing is equal to the input timing.
1039 if (!sdvo_priv
->is_tv
) {
1040 /* Set the output timing to the screen */
1041 intel_sdvo_set_target_output(output
,
1042 sdvo_priv
->controlled_output
);
1043 intel_sdvo_set_output_timing(output
, &input_dtd
);
1046 /* Set the input timing to the screen. Assume always input 0. */
1047 intel_sdvo_set_target_input(output
, true, false);
1049 if (sdvo_priv
->is_tv
)
1050 intel_sdvo_set_tv_format(output
);
1052 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1053 * provide the device with a timing it can support, if it supports that
1054 * feature. However, presumably we would need to adjust the CRTC to
1055 * output the preferred timing, and we don't support that currently.
1058 success
= intel_sdvo_create_preferred_input_timing(output
, clock
,
1061 struct intel_sdvo_dtd
*input_dtd
;
1063 intel_sdvo_get_preferred_input_timing(output
, &input_dtd
);
1064 intel_sdvo_set_input_timing(output
, &input_dtd
);
1067 intel_sdvo_set_input_timing(output
, &input_dtd
);
1070 switch (intel_sdvo_get_pixel_multiplier(mode
)) {
1072 intel_sdvo_set_clock_rate_mult(output
,
1073 SDVO_CLOCK_RATE_MULT_1X
);
1076 intel_sdvo_set_clock_rate_mult(output
,
1077 SDVO_CLOCK_RATE_MULT_2X
);
1080 intel_sdvo_set_clock_rate_mult(output
,
1081 SDVO_CLOCK_RATE_MULT_4X
);
1085 /* Set the SDVO control regs. */
1086 if (IS_I965G(dev
)) {
1087 sdvox
|= SDVO_BORDER_ENABLE
|
1088 SDVO_VSYNC_ACTIVE_HIGH
|
1089 SDVO_HSYNC_ACTIVE_HIGH
;
1091 sdvox
|= I915_READ(sdvo_priv
->output_device
);
1092 switch (sdvo_priv
->output_device
) {
1094 sdvox
&= SDVOB_PRESERVE_MASK
;
1097 sdvox
&= SDVOC_PRESERVE_MASK
;
1100 sdvox
|= (9 << 19) | SDVO_BORDER_ENABLE
;
1102 if (intel_crtc
->pipe
== 1)
1103 sdvox
|= SDVO_PIPE_B_SELECT
;
1105 sdvo_pixel_multiply
= intel_sdvo_get_pixel_multiplier(mode
);
1106 if (IS_I965G(dev
)) {
1107 /* done in crtc_mode_set as the dpll_md reg must be written early */
1108 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
1109 /* done in crtc_mode_set as it lives inside the dpll register */
1111 sdvox
|= (sdvo_pixel_multiply
- 1) << SDVO_PORT_MULTIPLY_SHIFT
;
1114 intel_sdvo_write_sdvox(output
, sdvox
);
1117 static void intel_sdvo_dpms(struct drm_encoder
*encoder
, int mode
)
1119 struct drm_device
*dev
= encoder
->dev
;
1120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1121 struct intel_output
*intel_output
= enc_to_intel_output(encoder
);
1122 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
1125 if (mode
!= DRM_MODE_DPMS_ON
) {
1126 intel_sdvo_set_active_outputs(intel_output
, 0);
1128 intel_sdvo_set_encoder_power_state(intel_output
, mode
);
1130 if (mode
== DRM_MODE_DPMS_OFF
) {
1131 temp
= I915_READ(sdvo_priv
->output_device
);
1132 if ((temp
& SDVO_ENABLE
) != 0) {
1133 intel_sdvo_write_sdvox(intel_output
, temp
& ~SDVO_ENABLE
);
1137 bool input1
, input2
;
1141 temp
= I915_READ(sdvo_priv
->output_device
);
1142 if ((temp
& SDVO_ENABLE
) == 0)
1143 intel_sdvo_write_sdvox(intel_output
, temp
| SDVO_ENABLE
);
1144 for (i
= 0; i
< 2; i
++)
1145 intel_wait_for_vblank(dev
);
1147 status
= intel_sdvo_get_trained_inputs(intel_output
, &input1
,
1151 /* Warn if the device reported failure to sync.
1152 * A lot of SDVO devices fail to notify of sync, but it's
1153 * a given it the status is a success, we succeeded.
1155 if (status
== SDVO_CMD_STATUS_SUCCESS
&& !input1
) {
1156 DRM_DEBUG("First %s output reported failure to sync\n",
1157 SDVO_NAME(sdvo_priv
));
1161 intel_sdvo_set_encoder_power_state(intel_output
, mode
);
1162 intel_sdvo_set_active_outputs(intel_output
, sdvo_priv
->controlled_output
);
1167 static void intel_sdvo_save(struct drm_connector
*connector
)
1169 struct drm_device
*dev
= connector
->dev
;
1170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1171 struct intel_output
*intel_output
= to_intel_output(connector
);
1172 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
1175 sdvo_priv
->save_sdvo_mult
= intel_sdvo_get_clock_rate_mult(intel_output
);
1176 intel_sdvo_get_active_outputs(intel_output
, &sdvo_priv
->save_active_outputs
);
1178 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x1) {
1179 intel_sdvo_set_target_input(intel_output
, true, false);
1180 intel_sdvo_get_input_timing(intel_output
,
1181 &sdvo_priv
->save_input_dtd_1
);
1184 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x2) {
1185 intel_sdvo_set_target_input(intel_output
, false, true);
1186 intel_sdvo_get_input_timing(intel_output
,
1187 &sdvo_priv
->save_input_dtd_2
);
1190 for (o
= SDVO_OUTPUT_FIRST
; o
<= SDVO_OUTPUT_LAST
; o
++)
1192 u16 this_output
= (1 << o
);
1193 if (sdvo_priv
->caps
.output_flags
& this_output
)
1195 intel_sdvo_set_target_output(intel_output
, this_output
);
1196 intel_sdvo_get_output_timing(intel_output
,
1197 &sdvo_priv
->save_output_dtd
[o
]);
1200 if (sdvo_priv
->is_tv
) {
1201 /* XXX: Save TV format/enhancements. */
1204 sdvo_priv
->save_SDVOX
= I915_READ(sdvo_priv
->output_device
);
1207 static void intel_sdvo_restore(struct drm_connector
*connector
)
1209 struct drm_device
*dev
= connector
->dev
;
1210 struct intel_output
*intel_output
= to_intel_output(connector
);
1211 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
1214 bool input1
, input2
;
1217 intel_sdvo_set_active_outputs(intel_output
, 0);
1219 for (o
= SDVO_OUTPUT_FIRST
; o
<= SDVO_OUTPUT_LAST
; o
++)
1221 u16 this_output
= (1 << o
);
1222 if (sdvo_priv
->caps
.output_flags
& this_output
) {
1223 intel_sdvo_set_target_output(intel_output
, this_output
);
1224 intel_sdvo_set_output_timing(intel_output
, &sdvo_priv
->save_output_dtd
[o
]);
1228 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x1) {
1229 intel_sdvo_set_target_input(intel_output
, true, false);
1230 intel_sdvo_set_input_timing(intel_output
, &sdvo_priv
->save_input_dtd_1
);
1233 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x2) {
1234 intel_sdvo_set_target_input(intel_output
, false, true);
1235 intel_sdvo_set_input_timing(intel_output
, &sdvo_priv
->save_input_dtd_2
);
1238 intel_sdvo_set_clock_rate_mult(intel_output
, sdvo_priv
->save_sdvo_mult
);
1240 if (sdvo_priv
->is_tv
) {
1241 /* XXX: Restore TV format/enhancements. */
1244 intel_sdvo_write_sdvox(intel_output
, sdvo_priv
->save_SDVOX
);
1246 if (sdvo_priv
->save_SDVOX
& SDVO_ENABLE
)
1248 for (i
= 0; i
< 2; i
++)
1249 intel_wait_for_vblank(dev
);
1250 status
= intel_sdvo_get_trained_inputs(intel_output
, &input1
, &input2
);
1251 if (status
== SDVO_CMD_STATUS_SUCCESS
&& !input1
)
1252 DRM_DEBUG("First %s output reported failure to sync\n",
1253 SDVO_NAME(sdvo_priv
));
1256 intel_sdvo_set_active_outputs(intel_output
, sdvo_priv
->save_active_outputs
);
1259 static int intel_sdvo_mode_valid(struct drm_connector
*connector
,
1260 struct drm_display_mode
*mode
)
1262 struct intel_output
*intel_output
= to_intel_output(connector
);
1263 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
1265 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
1266 return MODE_NO_DBLESCAN
;
1268 if (sdvo_priv
->pixel_clock_min
> mode
->clock
)
1269 return MODE_CLOCK_LOW
;
1271 if (sdvo_priv
->pixel_clock_max
< mode
->clock
)
1272 return MODE_CLOCK_HIGH
;
1277 static bool intel_sdvo_get_capabilities(struct intel_output
*intel_output
, struct intel_sdvo_caps
*caps
)
1281 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_DEVICE_CAPS
, NULL
, 0);
1282 status
= intel_sdvo_read_response(intel_output
, caps
, sizeof(*caps
));
1283 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
1289 struct drm_connector
* intel_sdvo_find(struct drm_device
*dev
, int sdvoB
)
1291 struct drm_connector
*connector
= NULL
;
1292 struct intel_output
*iout
= NULL
;
1293 struct intel_sdvo_priv
*sdvo
;
1295 /* find the sdvo connector */
1296 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1297 iout
= to_intel_output(connector
);
1299 if (iout
->type
!= INTEL_OUTPUT_SDVO
)
1302 sdvo
= iout
->dev_priv
;
1304 if (sdvo
->output_device
== SDVOB
&& sdvoB
)
1307 if (sdvo
->output_device
== SDVOC
&& !sdvoB
)
1315 int intel_sdvo_supports_hotplug(struct drm_connector
*connector
)
1319 struct intel_output
*intel_output
;
1325 intel_output
= to_intel_output(connector
);
1327 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_HOT_PLUG_SUPPORT
, NULL
, 0);
1328 status
= intel_sdvo_read_response(intel_output
, &response
, 2);
1330 if (response
[0] !=0)
1336 void intel_sdvo_set_hotplug(struct drm_connector
*connector
, int on
)
1340 struct intel_output
*intel_output
= to_intel_output(connector
);
1342 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_ACTIVE_HOT_PLUG
, NULL
, 0);
1343 intel_sdvo_read_response(intel_output
, &response
, 2);
1346 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_HOT_PLUG_SUPPORT
, NULL
, 0);
1347 status
= intel_sdvo_read_response(intel_output
, &response
, 2);
1349 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_ACTIVE_HOT_PLUG
, &response
, 2);
1353 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_ACTIVE_HOT_PLUG
, &response
, 2);
1356 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_ACTIVE_HOT_PLUG
, NULL
, 0);
1357 intel_sdvo_read_response(intel_output
, &response
, 2);
1360 static enum drm_connector_status
intel_sdvo_detect(struct drm_connector
*connector
)
1364 struct intel_output
*intel_output
= to_intel_output(connector
);
1366 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_ATTACHED_DISPLAYS
, NULL
, 0);
1367 status
= intel_sdvo_read_response(intel_output
, &response
, 2);
1369 DRM_DEBUG("SDVO response %d %d\n", response
[0], response
[1]);
1371 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
1372 return connector_status_unknown
;
1374 if ((response
[0] != 0) || (response
[1] != 0))
1375 return connector_status_connected
;
1377 return connector_status_disconnected
;
1380 static void intel_sdvo_get_ddc_modes(struct drm_connector
*connector
)
1382 struct intel_output
*intel_output
= to_intel_output(connector
);
1383 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
1385 /* set the bus switch and get the modes */
1386 intel_sdvo_set_control_bus_switch(intel_output
, sdvo_priv
->ddc_bus
);
1387 intel_ddc_get_modes(intel_output
);
1390 struct drm_device
*dev
= encoder
->dev
;
1391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1392 /* Mac mini hack. On this device, I get DDC through the analog, which
1393 * load-detects as disconnected. I fail to DDC through the SDVO DDC,
1394 * but it does load-detect as connected. So, just steal the DDC bits
1395 * from analog when we fail at finding it the right way.
1397 crt
= xf86_config
->output
[0];
1398 intel_output
= crt
->driver_private
;
1399 if (intel_output
->type
== I830_OUTPUT_ANALOG
&&
1400 crt
->funcs
->detect(crt
) == XF86OutputStatusDisconnected
) {
1401 I830I2CInit(pScrn
, &intel_output
->pDDCBus
, GPIOA
, "CRTDDC_A");
1402 edid_mon
= xf86OutputGetEDID(crt
, intel_output
->pDDCBus
);
1403 xf86DestroyI2CBusRec(intel_output
->pDDCBus
, true, true);
1406 xf86OutputSetEDID(output
, edid_mon
);
1407 modes
= xf86OutputGetEDIDModes(output
);
1413 * This function checks the current TV format, and chooses a default if
1414 * it hasn't been set.
1417 intel_sdvo_check_tv_format(struct intel_output
*output
)
1419 struct intel_sdvo_priv
*dev_priv
= output
->dev_priv
;
1420 struct intel_sdvo_tv_format format
;
1423 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_TV_FORMAT
, NULL
, 0);
1424 status
= intel_sdvo_read_response(output
, &format
, sizeof(format
));
1425 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
1428 memcpy(&dev_priv
->tv_format
, &format
, sizeof(format
));
1432 * Set of SDVO TV modes.
1433 * Note! This is in reply order (see loop in get_tv_modes).
1434 * XXX: all 60Hz refresh?
1436 struct drm_display_mode sdvo_tv_modes
[] = {
1437 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER
, 5815, 320, 321, 384,
1438 416, 0, 200, 201, 232, 233, 0,
1439 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1440 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER
, 6814, 320, 321, 384,
1441 416, 0, 240, 241, 272, 273, 0,
1442 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1443 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER
, 9910, 400, 401, 464,
1444 496, 0, 300, 301, 332, 333, 0,
1445 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1446 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER
, 16913, 640, 641, 704,
1447 736, 0, 350, 351, 382, 383, 0,
1448 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1449 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER
, 19121, 640, 641, 704,
1450 736, 0, 400, 401, 432, 433, 0,
1451 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1452 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 22654, 640, 641, 704,
1453 736, 0, 480, 481, 512, 513, 0,
1454 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1455 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER
, 24624, 704, 705, 768,
1456 800, 0, 480, 481, 512, 513, 0,
1457 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1458 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER
, 29232, 704, 705, 768,
1459 800, 0, 576, 577, 608, 609, 0,
1460 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1461 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER
, 18751, 720, 721, 784,
1462 816, 0, 350, 351, 382, 383, 0,
1463 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1464 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER
, 21199, 720, 721, 784,
1465 816, 0, 400, 401, 432, 433, 0,
1466 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1467 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 25116, 720, 721, 784,
1468 816, 0, 480, 481, 512, 513, 0,
1469 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1470 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER
, 28054, 720, 721, 784,
1471 816, 0, 540, 541, 572, 573, 0,
1472 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1473 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 29816, 720, 721, 784,
1474 816, 0, 576, 577, 608, 609, 0,
1475 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1476 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER
, 31570, 768, 769, 832,
1477 864, 0, 576, 577, 608, 609, 0,
1478 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1479 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 34030, 800, 801, 864,
1480 896, 0, 600, 601, 632, 633, 0,
1481 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1482 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER
, 36581, 832, 833, 896,
1483 928, 0, 624, 625, 656, 657, 0,
1484 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1485 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER
, 48707, 920, 921, 984,
1486 1016, 0, 766, 767, 798, 799, 0,
1487 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1488 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 53827, 1024, 1025, 1088,
1489 1120, 0, 768, 769, 800, 801, 0,
1490 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1491 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER
, 87265, 1280, 1281, 1344,
1492 1376, 0, 1024, 1025, 1056, 1057, 0,
1493 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1496 static void intel_sdvo_get_tv_modes(struct drm_connector
*connector
)
1498 struct intel_output
*output
= to_intel_output(connector
);
1499 struct intel_sdvo_priv
*sdvo_priv
= output
->dev_priv
;
1500 struct intel_sdvo_sdtv_resolution_request tv_res
;
1505 intel_sdvo_check_tv_format(output
);
1507 /* Read the list of supported input resolutions for the selected TV
1510 memset(&tv_res
, 0, sizeof(tv_res
));
1511 memcpy(&tv_res
, &sdvo_priv
->tv_format
, sizeof(tv_res
));
1512 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT
,
1513 &tv_res
, sizeof(tv_res
));
1514 status
= intel_sdvo_read_response(output
, &reply
, 3);
1515 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
1518 for (i
= 0; i
< ARRAY_SIZE(sdvo_tv_modes
); i
++)
1519 if (reply
& (1 << i
)) {
1520 struct drm_display_mode
*nmode
;
1521 nmode
= drm_mode_duplicate(connector
->dev
,
1524 drm_mode_probed_add(connector
, nmode
);
1528 static int intel_sdvo_get_modes(struct drm_connector
*connector
)
1530 struct intel_output
*output
= to_intel_output(connector
);
1531 struct intel_sdvo_priv
*sdvo_priv
= output
->dev_priv
;
1533 if (sdvo_priv
->is_tv
)
1534 intel_sdvo_get_tv_modes(connector
);
1536 intel_sdvo_get_ddc_modes(connector
);
1538 if (list_empty(&connector
->probed_modes
))
1543 static void intel_sdvo_destroy(struct drm_connector
*connector
)
1545 struct intel_output
*intel_output
= to_intel_output(connector
);
1547 if (intel_output
->i2c_bus
)
1548 intel_i2c_destroy(intel_output
->i2c_bus
);
1549 drm_sysfs_connector_remove(connector
);
1550 drm_connector_cleanup(connector
);
1551 kfree(intel_output
);
1554 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs
= {
1555 .dpms
= intel_sdvo_dpms
,
1556 .mode_fixup
= intel_sdvo_mode_fixup
,
1557 .prepare
= intel_encoder_prepare
,
1558 .mode_set
= intel_sdvo_mode_set
,
1559 .commit
= intel_encoder_commit
,
1562 static const struct drm_connector_funcs intel_sdvo_connector_funcs
= {
1563 .save
= intel_sdvo_save
,
1564 .restore
= intel_sdvo_restore
,
1565 .detect
= intel_sdvo_detect
,
1566 .fill_modes
= drm_helper_probe_single_connector_modes
,
1567 .destroy
= intel_sdvo_destroy
,
1570 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs
= {
1571 .get_modes
= intel_sdvo_get_modes
,
1572 .mode_valid
= intel_sdvo_mode_valid
,
1573 .best_encoder
= intel_best_encoder
,
1576 static void intel_sdvo_enc_destroy(struct drm_encoder
*encoder
)
1578 drm_encoder_cleanup(encoder
);
1581 static const struct drm_encoder_funcs intel_sdvo_enc_funcs
= {
1582 .destroy
= intel_sdvo_enc_destroy
,
1587 * Choose the appropriate DDC bus for control bus switch command for this
1588 * SDVO output based on the controlled output.
1590 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1591 * outputs, then LVDS outputs.
1594 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv
*dev_priv
)
1597 unsigned int num_bits
;
1599 /* Make a mask of outputs less than or equal to our own priority in the
1602 switch (dev_priv
->controlled_output
) {
1603 case SDVO_OUTPUT_LVDS1
:
1604 mask
|= SDVO_OUTPUT_LVDS1
;
1605 case SDVO_OUTPUT_LVDS0
:
1606 mask
|= SDVO_OUTPUT_LVDS0
;
1607 case SDVO_OUTPUT_TMDS1
:
1608 mask
|= SDVO_OUTPUT_TMDS1
;
1609 case SDVO_OUTPUT_TMDS0
:
1610 mask
|= SDVO_OUTPUT_TMDS0
;
1611 case SDVO_OUTPUT_RGB1
:
1612 mask
|= SDVO_OUTPUT_RGB1
;
1613 case SDVO_OUTPUT_RGB0
:
1614 mask
|= SDVO_OUTPUT_RGB0
;
1618 /* Count bits to find what number we are in the priority list. */
1619 mask
&= dev_priv
->caps
.output_flags
;
1620 num_bits
= hweight16(mask
);
1622 /* if more than 3 outputs, default to DDC bus 3 for now */
1626 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1627 dev_priv
->ddc_bus
= 1 << num_bits
;
1631 intel_sdvo_get_digital_encoding_mode(struct intel_output
*output
)
1633 struct intel_sdvo_priv
*sdvo_priv
= output
->dev_priv
;
1636 intel_sdvo_set_target_output(output
, sdvo_priv
->controlled_output
);
1638 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_ENCODE
, NULL
, 0);
1639 status
= intel_sdvo_read_response(output
, &sdvo_priv
->is_hdmi
, 1);
1640 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
1645 bool intel_sdvo_init(struct drm_device
*dev
, int output_device
)
1647 struct drm_connector
*connector
;
1648 struct intel_output
*intel_output
;
1649 struct intel_sdvo_priv
*sdvo_priv
;
1650 struct intel_i2c_chan
*i2cbus
= NULL
;
1654 int encoder_type
, output_id
;
1656 intel_output
= kcalloc(sizeof(struct intel_output
)+sizeof(struct intel_sdvo_priv
), 1, GFP_KERNEL
);
1657 if (!intel_output
) {
1661 connector
= &intel_output
->base
;
1663 drm_connector_init(dev
, connector
, &intel_sdvo_connector_funcs
,
1664 DRM_MODE_CONNECTOR_Unknown
);
1665 drm_connector_helper_add(connector
, &intel_sdvo_connector_helper_funcs
);
1666 sdvo_priv
= (struct intel_sdvo_priv
*)(intel_output
+ 1);
1667 intel_output
->type
= INTEL_OUTPUT_SDVO
;
1669 connector
->interlace_allowed
= 0;
1670 connector
->doublescan_allowed
= 0;
1672 /* setup the DDC bus. */
1673 if (output_device
== SDVOB
)
1674 i2cbus
= intel_i2c_create(dev
, GPIOE
, "SDVOCTRL_E for SDVOB");
1676 i2cbus
= intel_i2c_create(dev
, GPIOE
, "SDVOCTRL_E for SDVOC");
1681 sdvo_priv
->i2c_bus
= i2cbus
;
1683 if (output_device
== SDVOB
) {
1685 sdvo_priv
->i2c_bus
->slave_addr
= 0x38;
1688 sdvo_priv
->i2c_bus
->slave_addr
= 0x39;
1691 sdvo_priv
->output_device
= output_device
;
1692 intel_output
->i2c_bus
= i2cbus
;
1693 intel_output
->dev_priv
= sdvo_priv
;
1696 /* Read the regs to test if we can talk to the device */
1697 for (i
= 0; i
< 0x40; i
++) {
1698 if (!intel_sdvo_read_byte(intel_output
, i
, &ch
[i
])) {
1699 DRM_DEBUG("No SDVO device found on SDVO%c\n",
1700 output_device
== SDVOB
? 'B' : 'C');
1705 intel_sdvo_get_capabilities(intel_output
, &sdvo_priv
->caps
);
1707 if (sdvo_priv
->caps
.output_flags
&
1708 (SDVO_OUTPUT_TMDS0
| SDVO_OUTPUT_TMDS1
)) {
1709 if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_TMDS0
)
1710 sdvo_priv
->controlled_output
= SDVO_OUTPUT_TMDS0
;
1712 sdvo_priv
->controlled_output
= SDVO_OUTPUT_TMDS1
;
1714 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
;
1715 encoder_type
= DRM_MODE_ENCODER_TMDS
;
1716 connector_type
= DRM_MODE_CONNECTOR_DVID
;
1718 if (intel_sdvo_get_supp_encode(intel_output
,
1719 &sdvo_priv
->encode
) &&
1720 intel_sdvo_get_digital_encoding_mode(intel_output
) &&
1721 sdvo_priv
->is_hdmi
) {
1722 /* enable hdmi encoding mode if supported */
1723 intel_sdvo_set_encode(intel_output
, SDVO_ENCODE_HDMI
);
1724 intel_sdvo_set_colorimetry(intel_output
,
1725 SDVO_COLORIMETRY_RGB256
);
1726 connector_type
= DRM_MODE_CONNECTOR_HDMIA
;
1729 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_SVID0
)
1731 sdvo_priv
->controlled_output
= SDVO_OUTPUT_SVID0
;
1732 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
;
1733 encoder_type
= DRM_MODE_ENCODER_TVDAC
;
1734 connector_type
= DRM_MODE_CONNECTOR_SVIDEO
;
1735 sdvo_priv
->is_tv
= true;
1736 intel_output
->needs_tv_clock
= true;
1738 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_RGB0
)
1740 sdvo_priv
->controlled_output
= SDVO_OUTPUT_RGB0
;
1741 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
;
1742 encoder_type
= DRM_MODE_ENCODER_DAC
;
1743 connector_type
= DRM_MODE_CONNECTOR_VGA
;
1745 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_RGB1
)
1747 sdvo_priv
->controlled_output
= SDVO_OUTPUT_RGB1
;
1748 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
;
1749 encoder_type
= DRM_MODE_ENCODER_DAC
;
1750 connector_type
= DRM_MODE_CONNECTOR_VGA
;
1752 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_LVDS0
)
1754 sdvo_priv
->controlled_output
= SDVO_OUTPUT_LVDS0
;
1755 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
;
1756 encoder_type
= DRM_MODE_ENCODER_LVDS
;
1757 connector_type
= DRM_MODE_CONNECTOR_LVDS
;
1759 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_LVDS1
)
1761 sdvo_priv
->controlled_output
= SDVO_OUTPUT_LVDS1
;
1762 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
;
1763 encoder_type
= DRM_MODE_ENCODER_LVDS
;
1764 connector_type
= DRM_MODE_CONNECTOR_LVDS
;
1768 unsigned char bytes
[2];
1770 sdvo_priv
->controlled_output
= 0;
1771 memcpy (bytes
, &sdvo_priv
->caps
.output_flags
, 2);
1772 DRM_DEBUG("%s: Unknown SDVO output type (0x%02x%02x)\n",
1773 SDVO_NAME(sdvo_priv
),
1774 bytes
[0], bytes
[1]);
1775 encoder_type
= DRM_MODE_ENCODER_NONE
;
1776 connector_type
= DRM_MODE_CONNECTOR_Unknown
;
1780 drm_encoder_init(dev
, &intel_output
->enc
, &intel_sdvo_enc_funcs
, encoder_type
);
1781 drm_encoder_helper_add(&intel_output
->enc
, &intel_sdvo_helper_funcs
);
1782 connector
->connector_type
= connector_type
;
1784 drm_mode_connector_attach_encoder(&intel_output
->base
, &intel_output
->enc
);
1785 drm_sysfs_connector_add(connector
);
1787 intel_sdvo_select_ddc_bus(sdvo_priv
);
1789 /* Set the input timing to the screen. Assume always input 0. */
1790 intel_sdvo_set_target_input(intel_output
, true, false);
1792 intel_sdvo_get_input_pixel_clock_range(intel_output
,
1793 &sdvo_priv
->pixel_clock_min
,
1794 &sdvo_priv
->pixel_clock_max
);
1797 DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, "
1798 "clock range %dMHz - %dMHz, "
1799 "input 1: %c, input 2: %c, "
1800 "output 1: %c, output 2: %c\n",
1801 SDVO_NAME(sdvo_priv
),
1802 sdvo_priv
->caps
.vendor_id
, sdvo_priv
->caps
.device_id
,
1803 sdvo_priv
->caps
.device_rev_id
,
1804 sdvo_priv
->pixel_clock_min
/ 1000,
1805 sdvo_priv
->pixel_clock_max
/ 1000,
1806 (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x1) ? 'Y' : 'N',
1807 (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x2) ? 'Y' : 'N',
1808 /* check currently supported outputs */
1809 sdvo_priv
->caps
.output_flags
&
1810 (SDVO_OUTPUT_TMDS0
| SDVO_OUTPUT_RGB0
) ? 'Y' : 'N',
1811 sdvo_priv
->caps
.output_flags
&
1812 (SDVO_OUTPUT_TMDS1
| SDVO_OUTPUT_RGB1
) ? 'Y' : 'N');
1814 intel_output
->ddc_bus
= i2cbus
;
1819 intel_i2c_destroy(intel_output
->i2c_bus
);
1821 drm_connector_cleanup(connector
);
1822 kfree(intel_output
);