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drm/i915: pixel multiplier readout support for pch ports
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/export.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38 #include "intel_sdvo_regs.h"
39
40 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
44
45 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
50 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
51 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
53
54
55 static const char *tv_format_names[] = {
56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63 };
64
65 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
67 struct intel_sdvo {
68 struct intel_encoder base;
69
70 struct i2c_adapter *i2c;
71 u8 slave_addr;
72
73 struct i2c_adapter ddc;
74
75 /* Register for the SDVO device: SDVOB or SDVOC */
76 uint32_t sdvo_reg;
77
78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
80
81 /*
82 * Capabilities of the SDVO device returned by
83 * intel_sdvo_get_capabilities()
84 */
85 struct intel_sdvo_caps caps;
86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
88 int pixel_clock_min, pixel_clock_max;
89
90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
96 /*
97 * Hotplug activation bits for this device
98 */
99 uint16_t hotplug_active;
100
101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
106 bool color_range_auto;
107
108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
120 /* This is for current tv format name */
121 int tv_format_index;
122
123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
129 bool rgb_quant_range_selectable;
130
131 /**
132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
134 */
135 bool is_lvds;
136
137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
142 /* DDC bus used by this SDVO encoder */
143 uint8_t ddc_bus;
144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
149 };
150
151 struct intel_sdvo_connector {
152 struct intel_connector base;
153
154 /* Mark the type of connector */
155 uint16_t output_flag;
156
157 enum hdmi_force_audio force_audio;
158
159 /* This contains all current supported TV format */
160 u8 tv_format_supported[TV_FORMAT_NUM];
161 int format_supported_num;
162 struct drm_property *tv_format;
163
164 /* add the property for the SDVO-TV */
165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
180 struct drm_property *dot_crawl;
181
182 /* add the property for the SDVO-TV/LVDS */
183 struct drm_property *brightness;
184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
187
188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
202 u32 cur_dot_crawl, max_dot_crawl;
203 };
204
205 static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
206 {
207 return container_of(encoder, struct intel_sdvo, base.base);
208 }
209
210 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211 {
212 return container_of(intel_attached_encoder(connector),
213 struct intel_sdvo, base);
214 }
215
216 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
217 {
218 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
219 }
220
221 static bool
222 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
223 static bool
224 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
225 struct intel_sdvo_connector *intel_sdvo_connector,
226 int type);
227 static bool
228 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
229 struct intel_sdvo_connector *intel_sdvo_connector);
230
231 /**
232 * Writes the SDVOB or SDVOC with the given value, but always writes both
233 * SDVOB and SDVOC to work around apparent hardware issues (according to
234 * comments in the BIOS).
235 */
236 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
237 {
238 struct drm_device *dev = intel_sdvo->base.base.dev;
239 struct drm_i915_private *dev_priv = dev->dev_private;
240 u32 bval = val, cval = val;
241 int i;
242
243 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
244 I915_WRITE(intel_sdvo->sdvo_reg, val);
245 I915_READ(intel_sdvo->sdvo_reg);
246 return;
247 }
248
249 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
250 cval = I915_READ(GEN3_SDVOC);
251 else
252 bval = I915_READ(GEN3_SDVOB);
253
254 /*
255 * Write the registers twice for luck. Sometimes,
256 * writing them only once doesn't appear to 'stick'.
257 * The BIOS does this too. Yay, magic
258 */
259 for (i = 0; i < 2; i++)
260 {
261 I915_WRITE(GEN3_SDVOB, bval);
262 I915_READ(GEN3_SDVOB);
263 I915_WRITE(GEN3_SDVOC, cval);
264 I915_READ(GEN3_SDVOC);
265 }
266 }
267
268 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
269 {
270 struct i2c_msg msgs[] = {
271 {
272 .addr = intel_sdvo->slave_addr,
273 .flags = 0,
274 .len = 1,
275 .buf = &addr,
276 },
277 {
278 .addr = intel_sdvo->slave_addr,
279 .flags = I2C_M_RD,
280 .len = 1,
281 .buf = ch,
282 }
283 };
284 int ret;
285
286 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
287 return true;
288
289 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
290 return false;
291 }
292
293 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
294 /** Mapping of command numbers to names, for debug output */
295 static const struct _sdvo_cmd_name {
296 u8 cmd;
297 const char *name;
298 } sdvo_cmd_names[] = {
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
342
343 /* Add the op code for SDVO enhancements */
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
388
389 /* HDMI op code */
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
410 };
411
412 #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
413
414 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
415 const void *args, int args_len)
416 {
417 int i;
418
419 DRM_DEBUG_KMS("%s: W: %02X ",
420 SDVO_NAME(intel_sdvo), cmd);
421 for (i = 0; i < args_len; i++)
422 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
423 for (; i < 8; i++)
424 DRM_LOG_KMS(" ");
425 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
426 if (cmd == sdvo_cmd_names[i].cmd) {
427 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
428 break;
429 }
430 }
431 if (i == ARRAY_SIZE(sdvo_cmd_names))
432 DRM_LOG_KMS("(%02X)", cmd);
433 DRM_LOG_KMS("\n");
434 }
435
436 static const char *cmd_status_names[] = {
437 "Power on",
438 "Success",
439 "Not supported",
440 "Invalid arg",
441 "Pending",
442 "Target not specified",
443 "Scaling not supported"
444 };
445
446 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
447 const void *args, int args_len)
448 {
449 u8 *buf, status;
450 struct i2c_msg *msgs;
451 int i, ret = true;
452
453 /* Would be simpler to allocate both in one go ? */
454 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
455 if (!buf)
456 return false;
457
458 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
459 if (!msgs) {
460 kfree(buf);
461 return false;
462 }
463
464 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
465
466 for (i = 0; i < args_len; i++) {
467 msgs[i].addr = intel_sdvo->slave_addr;
468 msgs[i].flags = 0;
469 msgs[i].len = 2;
470 msgs[i].buf = buf + 2 *i;
471 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
472 buf[2*i + 1] = ((u8*)args)[i];
473 }
474 msgs[i].addr = intel_sdvo->slave_addr;
475 msgs[i].flags = 0;
476 msgs[i].len = 2;
477 msgs[i].buf = buf + 2*i;
478 buf[2*i + 0] = SDVO_I2C_OPCODE;
479 buf[2*i + 1] = cmd;
480
481 /* the following two are to read the response */
482 status = SDVO_I2C_CMD_STATUS;
483 msgs[i+1].addr = intel_sdvo->slave_addr;
484 msgs[i+1].flags = 0;
485 msgs[i+1].len = 1;
486 msgs[i+1].buf = &status;
487
488 msgs[i+2].addr = intel_sdvo->slave_addr;
489 msgs[i+2].flags = I2C_M_RD;
490 msgs[i+2].len = 1;
491 msgs[i+2].buf = &status;
492
493 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
494 if (ret < 0) {
495 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
496 ret = false;
497 goto out;
498 }
499 if (ret != i+3) {
500 /* failure in I2C transfer */
501 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
502 ret = false;
503 }
504
505 out:
506 kfree(msgs);
507 kfree(buf);
508 return ret;
509 }
510
511 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
512 void *response, int response_len)
513 {
514 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
515 u8 status;
516 int i;
517
518 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
519
520 /*
521 * The documentation states that all commands will be
522 * processed within 15µs, and that we need only poll
523 * the status byte a maximum of 3 times in order for the
524 * command to be complete.
525 *
526 * Check 5 times in case the hardware failed to read the docs.
527 *
528 * Also beware that the first response by many devices is to
529 * reply PENDING and stall for time. TVs are notorious for
530 * requiring longer than specified to complete their replies.
531 * Originally (in the DDX long ago), the delay was only ever 15ms
532 * with an additional delay of 30ms applied for TVs added later after
533 * many experiments. To accommodate both sets of delays, we do a
534 * sequence of slow checks if the device is falling behind and fails
535 * to reply within 5*15µs.
536 */
537 if (!intel_sdvo_read_byte(intel_sdvo,
538 SDVO_I2C_CMD_STATUS,
539 &status))
540 goto log_fail;
541
542 while (status == SDVO_CMD_STATUS_PENDING && --retry) {
543 if (retry < 10)
544 msleep(15);
545 else
546 udelay(15);
547
548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
551 goto log_fail;
552 }
553
554 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
555 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
556 else
557 DRM_LOG_KMS("(??? %d)", status);
558
559 if (status != SDVO_CMD_STATUS_SUCCESS)
560 goto log_fail;
561
562 /* Read the command response */
563 for (i = 0; i < response_len; i++) {
564 if (!intel_sdvo_read_byte(intel_sdvo,
565 SDVO_I2C_RETURN_0 + i,
566 &((u8 *)response)[i]))
567 goto log_fail;
568 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
569 }
570 DRM_LOG_KMS("\n");
571 return true;
572
573 log_fail:
574 DRM_LOG_KMS("... failed\n");
575 return false;
576 }
577
578 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
579 {
580 if (mode->clock >= 100000)
581 return 1;
582 else if (mode->clock >= 50000)
583 return 2;
584 else
585 return 4;
586 }
587
588 static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
589 u8 ddc_bus)
590 {
591 /* This must be the immediately preceding write before the i2c xfer */
592 return intel_sdvo_write_cmd(intel_sdvo,
593 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
594 &ddc_bus, 1);
595 }
596
597 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
598 {
599 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
600 return false;
601
602 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
603 }
604
605 static bool
606 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
607 {
608 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
609 return false;
610
611 return intel_sdvo_read_response(intel_sdvo, value, len);
612 }
613
614 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
615 {
616 struct intel_sdvo_set_target_input_args targets = {0};
617 return intel_sdvo_set_value(intel_sdvo,
618 SDVO_CMD_SET_TARGET_INPUT,
619 &targets, sizeof(targets));
620 }
621
622 /**
623 * Return whether each input is trained.
624 *
625 * This function is making an assumption about the layout of the response,
626 * which should be checked against the docs.
627 */
628 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
629 {
630 struct intel_sdvo_get_trained_inputs_response response;
631
632 BUILD_BUG_ON(sizeof(response) != 1);
633 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
634 &response, sizeof(response)))
635 return false;
636
637 *input_1 = response.input0_trained;
638 *input_2 = response.input1_trained;
639 return true;
640 }
641
642 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
643 u16 outputs)
644 {
645 return intel_sdvo_set_value(intel_sdvo,
646 SDVO_CMD_SET_ACTIVE_OUTPUTS,
647 &outputs, sizeof(outputs));
648 }
649
650 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
651 u16 *outputs)
652 {
653 return intel_sdvo_get_value(intel_sdvo,
654 SDVO_CMD_GET_ACTIVE_OUTPUTS,
655 outputs, sizeof(*outputs));
656 }
657
658 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
659 int mode)
660 {
661 u8 state = SDVO_ENCODER_STATE_ON;
662
663 switch (mode) {
664 case DRM_MODE_DPMS_ON:
665 state = SDVO_ENCODER_STATE_ON;
666 break;
667 case DRM_MODE_DPMS_STANDBY:
668 state = SDVO_ENCODER_STATE_STANDBY;
669 break;
670 case DRM_MODE_DPMS_SUSPEND:
671 state = SDVO_ENCODER_STATE_SUSPEND;
672 break;
673 case DRM_MODE_DPMS_OFF:
674 state = SDVO_ENCODER_STATE_OFF;
675 break;
676 }
677
678 return intel_sdvo_set_value(intel_sdvo,
679 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
680 }
681
682 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
683 int *clock_min,
684 int *clock_max)
685 {
686 struct intel_sdvo_pixel_clock_range clocks;
687
688 BUILD_BUG_ON(sizeof(clocks) != 4);
689 if (!intel_sdvo_get_value(intel_sdvo,
690 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
691 &clocks, sizeof(clocks)))
692 return false;
693
694 /* Convert the values from units of 10 kHz to kHz. */
695 *clock_min = clocks.min * 10;
696 *clock_max = clocks.max * 10;
697 return true;
698 }
699
700 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
701 u16 outputs)
702 {
703 return intel_sdvo_set_value(intel_sdvo,
704 SDVO_CMD_SET_TARGET_OUTPUT,
705 &outputs, sizeof(outputs));
706 }
707
708 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
709 struct intel_sdvo_dtd *dtd)
710 {
711 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
712 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
713 }
714
715 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
716 struct intel_sdvo_dtd *dtd)
717 {
718 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
719 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
720 }
721
722 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
723 struct intel_sdvo_dtd *dtd)
724 {
725 return intel_sdvo_set_timing(intel_sdvo,
726 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
727 }
728
729 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
730 struct intel_sdvo_dtd *dtd)
731 {
732 return intel_sdvo_set_timing(intel_sdvo,
733 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
734 }
735
736 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
737 struct intel_sdvo_dtd *dtd)
738 {
739 return intel_sdvo_get_timing(intel_sdvo,
740 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
741 }
742
743 static bool
744 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
745 uint16_t clock,
746 uint16_t width,
747 uint16_t height)
748 {
749 struct intel_sdvo_preferred_input_timing_args args;
750
751 memset(&args, 0, sizeof(args));
752 args.clock = clock;
753 args.width = width;
754 args.height = height;
755 args.interlace = 0;
756
757 if (intel_sdvo->is_lvds &&
758 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
759 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
760 args.scaled = 1;
761
762 return intel_sdvo_set_value(intel_sdvo,
763 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
764 &args, sizeof(args));
765 }
766
767 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
768 struct intel_sdvo_dtd *dtd)
769 {
770 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
771 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
772 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
773 &dtd->part1, sizeof(dtd->part1)) &&
774 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
775 &dtd->part2, sizeof(dtd->part2));
776 }
777
778 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
779 {
780 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
781 }
782
783 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
784 const struct drm_display_mode *mode)
785 {
786 uint16_t width, height;
787 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
788 uint16_t h_sync_offset, v_sync_offset;
789 int mode_clock;
790
791 width = mode->hdisplay;
792 height = mode->vdisplay;
793
794 /* do some mode translations */
795 h_blank_len = mode->htotal - mode->hdisplay;
796 h_sync_len = mode->hsync_end - mode->hsync_start;
797
798 v_blank_len = mode->vtotal - mode->vdisplay;
799 v_sync_len = mode->vsync_end - mode->vsync_start;
800
801 h_sync_offset = mode->hsync_start - mode->hdisplay;
802 v_sync_offset = mode->vsync_start - mode->vdisplay;
803
804 mode_clock = mode->clock;
805 mode_clock /= 10;
806 dtd->part1.clock = mode_clock;
807
808 dtd->part1.h_active = width & 0xff;
809 dtd->part1.h_blank = h_blank_len & 0xff;
810 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
811 ((h_blank_len >> 8) & 0xf);
812 dtd->part1.v_active = height & 0xff;
813 dtd->part1.v_blank = v_blank_len & 0xff;
814 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
815 ((v_blank_len >> 8) & 0xf);
816
817 dtd->part2.h_sync_off = h_sync_offset & 0xff;
818 dtd->part2.h_sync_width = h_sync_len & 0xff;
819 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
820 (v_sync_len & 0xf);
821 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
822 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
823 ((v_sync_len & 0x30) >> 4);
824
825 dtd->part2.dtd_flags = 0x18;
826 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
827 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
828 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
829 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
830 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
831 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
832
833 dtd->part2.sdvo_flags = 0;
834 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
835 dtd->part2.reserved = 0;
836 }
837
838 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
839 const struct intel_sdvo_dtd *dtd)
840 {
841 mode->hdisplay = dtd->part1.h_active;
842 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
843 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
844 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
845 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
846 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
847 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
848 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
849
850 mode->vdisplay = dtd->part1.v_active;
851 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
852 mode->vsync_start = mode->vdisplay;
853 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
854 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
855 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
856 mode->vsync_end = mode->vsync_start +
857 (dtd->part2.v_sync_off_width & 0xf);
858 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
859 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
860 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
861
862 mode->clock = dtd->part1.clock * 10;
863
864 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
865 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
866 mode->flags |= DRM_MODE_FLAG_INTERLACE;
867 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
868 mode->flags |= DRM_MODE_FLAG_PHSYNC;
869 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
870 mode->flags |= DRM_MODE_FLAG_PVSYNC;
871 }
872
873 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
874 {
875 struct intel_sdvo_encode encode;
876
877 BUILD_BUG_ON(sizeof(encode) != 2);
878 return intel_sdvo_get_value(intel_sdvo,
879 SDVO_CMD_GET_SUPP_ENCODE,
880 &encode, sizeof(encode));
881 }
882
883 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
884 uint8_t mode)
885 {
886 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
887 }
888
889 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
890 uint8_t mode)
891 {
892 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
893 }
894
895 #if 0
896 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
897 {
898 int i, j;
899 uint8_t set_buf_index[2];
900 uint8_t av_split;
901 uint8_t buf_size;
902 uint8_t buf[48];
903 uint8_t *pos;
904
905 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
906
907 for (i = 0; i <= av_split; i++) {
908 set_buf_index[0] = i; set_buf_index[1] = 0;
909 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
910 set_buf_index, 2);
911 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
912 intel_sdvo_read_response(encoder, &buf_size, 1);
913
914 pos = buf;
915 for (j = 0; j <= buf_size; j += 8) {
916 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
917 NULL, 0);
918 intel_sdvo_read_response(encoder, pos, 8);
919 pos += 8;
920 }
921 }
922 }
923 #endif
924
925 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
926 unsigned if_index, uint8_t tx_rate,
927 uint8_t *data, unsigned length)
928 {
929 uint8_t set_buf_index[2] = { if_index, 0 };
930 uint8_t hbuf_size, tmp[8];
931 int i;
932
933 if (!intel_sdvo_set_value(intel_sdvo,
934 SDVO_CMD_SET_HBUF_INDEX,
935 set_buf_index, 2))
936 return false;
937
938 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
939 &hbuf_size, 1))
940 return false;
941
942 /* Buffer size is 0 based, hooray! */
943 hbuf_size++;
944
945 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
946 if_index, length, hbuf_size);
947
948 for (i = 0; i < hbuf_size; i += 8) {
949 memset(tmp, 0, 8);
950 if (i < length)
951 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
952
953 if (!intel_sdvo_set_value(intel_sdvo,
954 SDVO_CMD_SET_HBUF_DATA,
955 tmp, 8))
956 return false;
957 }
958
959 return intel_sdvo_set_value(intel_sdvo,
960 SDVO_CMD_SET_HBUF_TXRATE,
961 &tx_rate, 1);
962 }
963
964 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
965 const struct drm_display_mode *adjusted_mode)
966 {
967 struct dip_infoframe avi_if = {
968 .type = DIP_TYPE_AVI,
969 .ver = DIP_VERSION_AVI,
970 .len = DIP_LEN_AVI,
971 };
972 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
973 struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc);
974
975 if (intel_sdvo->rgb_quant_range_selectable) {
976 if (intel_crtc->config.limited_color_range)
977 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
978 else
979 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
980 }
981
982 avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
983
984 intel_dip_infoframe_csum(&avi_if);
985
986 /* sdvo spec says that the ecc is handled by the hw, and it looks like
987 * we must not send the ecc field, either. */
988 memcpy(sdvo_data, &avi_if, 3);
989 sdvo_data[3] = avi_if.checksum;
990 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
991
992 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
993 SDVO_HBUF_TX_VSYNC,
994 sdvo_data, sizeof(sdvo_data));
995 }
996
997 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
998 {
999 struct intel_sdvo_tv_format format;
1000 uint32_t format_map;
1001
1002 format_map = 1 << intel_sdvo->tv_format_index;
1003 memset(&format, 0, sizeof(format));
1004 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1005
1006 BUILD_BUG_ON(sizeof(format) != 6);
1007 return intel_sdvo_set_value(intel_sdvo,
1008 SDVO_CMD_SET_TV_FORMAT,
1009 &format, sizeof(format));
1010 }
1011
1012 static bool
1013 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1014 const struct drm_display_mode *mode)
1015 {
1016 struct intel_sdvo_dtd output_dtd;
1017
1018 if (!intel_sdvo_set_target_output(intel_sdvo,
1019 intel_sdvo->attached_output))
1020 return false;
1021
1022 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1023 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1024 return false;
1025
1026 return true;
1027 }
1028
1029 /* Asks the sdvo controller for the preferred input mode given the output mode.
1030 * Unfortunately we have to set up the full output mode to do that. */
1031 static bool
1032 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1033 const struct drm_display_mode *mode,
1034 struct drm_display_mode *adjusted_mode)
1035 {
1036 struct intel_sdvo_dtd input_dtd;
1037
1038 /* Reset the input timing to the screen. Assume always input 0. */
1039 if (!intel_sdvo_set_target_input(intel_sdvo))
1040 return false;
1041
1042 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1043 mode->clock / 10,
1044 mode->hdisplay,
1045 mode->vdisplay))
1046 return false;
1047
1048 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1049 &input_dtd))
1050 return false;
1051
1052 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1053 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1054
1055 return true;
1056 }
1057
1058 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
1059 {
1060 unsigned dotclock = pipe_config->adjusted_mode.clock;
1061 struct dpll *clock = &pipe_config->dpll;
1062
1063 /* SDVO TV has fixed PLL values depend on its clock range,
1064 this mirrors vbios setting. */
1065 if (dotclock >= 100000 && dotclock < 140500) {
1066 clock->p1 = 2;
1067 clock->p2 = 10;
1068 clock->n = 3;
1069 clock->m1 = 16;
1070 clock->m2 = 8;
1071 } else if (dotclock >= 140500 && dotclock <= 200000) {
1072 clock->p1 = 1;
1073 clock->p2 = 10;
1074 clock->n = 6;
1075 clock->m1 = 12;
1076 clock->m2 = 8;
1077 } else {
1078 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1079 }
1080
1081 pipe_config->clock_set = true;
1082 }
1083
1084 static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1085 struct intel_crtc_config *pipe_config)
1086 {
1087 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1088 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1089 struct drm_display_mode *mode = &pipe_config->requested_mode;
1090
1091 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1092 pipe_config->pipe_bpp = 8*3;
1093
1094 if (HAS_PCH_SPLIT(encoder->base.dev))
1095 pipe_config->has_pch_encoder = true;
1096
1097 /* We need to construct preferred input timings based on our
1098 * output timings. To do that, we have to set the output
1099 * timings, even though this isn't really the right place in
1100 * the sequence to do it. Oh well.
1101 */
1102 if (intel_sdvo->is_tv) {
1103 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1104 return false;
1105
1106 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1107 mode,
1108 adjusted_mode);
1109 pipe_config->sdvo_tv_clock = true;
1110 } else if (intel_sdvo->is_lvds) {
1111 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1112 intel_sdvo->sdvo_lvds_fixed_mode))
1113 return false;
1114
1115 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1116 mode,
1117 adjusted_mode);
1118 }
1119
1120 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1121 * SDVO device will factor out the multiplier during mode_set.
1122 */
1123 pipe_config->pixel_multiplier =
1124 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1125 adjusted_mode->clock *= pipe_config->pixel_multiplier;
1126
1127 if (intel_sdvo->color_range_auto) {
1128 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1129 /* FIXME: This bit is only valid when using TMDS encoding and 8
1130 * bit per color mode. */
1131 if (intel_sdvo->has_hdmi_monitor &&
1132 drm_match_cea_mode(adjusted_mode) > 1)
1133 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
1134 else
1135 intel_sdvo->color_range = 0;
1136 }
1137
1138 if (intel_sdvo->color_range)
1139 pipe_config->limited_color_range = true;
1140
1141 /* Clock computation needs to happen after pixel multiplier. */
1142 if (intel_sdvo->is_tv)
1143 i9xx_adjust_sdvo_tv_clock(pipe_config);
1144
1145 return true;
1146 }
1147
1148 static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
1149 {
1150 struct drm_device *dev = intel_encoder->base.dev;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 struct drm_crtc *crtc = intel_encoder->base.crtc;
1153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1154 struct drm_display_mode *adjusted_mode =
1155 &intel_crtc->config.adjusted_mode;
1156 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
1157 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&intel_encoder->base);
1158 u32 sdvox;
1159 struct intel_sdvo_in_out_map in_out;
1160 struct intel_sdvo_dtd input_dtd, output_dtd;
1161 int rate;
1162
1163 if (!mode)
1164 return;
1165
1166 /* First, set the input mapping for the first input to our controlled
1167 * output. This is only correct if we're a single-input device, in
1168 * which case the first input is the output from the appropriate SDVO
1169 * channel on the motherboard. In a two-input device, the first input
1170 * will be SDVOB and the second SDVOC.
1171 */
1172 in_out.in0 = intel_sdvo->attached_output;
1173 in_out.in1 = 0;
1174
1175 intel_sdvo_set_value(intel_sdvo,
1176 SDVO_CMD_SET_IN_OUT_MAP,
1177 &in_out, sizeof(in_out));
1178
1179 /* Set the output timings to the screen */
1180 if (!intel_sdvo_set_target_output(intel_sdvo,
1181 intel_sdvo->attached_output))
1182 return;
1183
1184 /* lvds has a special fixed output timing. */
1185 if (intel_sdvo->is_lvds)
1186 intel_sdvo_get_dtd_from_mode(&output_dtd,
1187 intel_sdvo->sdvo_lvds_fixed_mode);
1188 else
1189 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1190 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1191 DRM_INFO("Setting output timings on %s failed\n",
1192 SDVO_NAME(intel_sdvo));
1193
1194 /* Set the input timing to the screen. Assume always input 0. */
1195 if (!intel_sdvo_set_target_input(intel_sdvo))
1196 return;
1197
1198 if (intel_sdvo->has_hdmi_monitor) {
1199 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1200 intel_sdvo_set_colorimetry(intel_sdvo,
1201 SDVO_COLORIMETRY_RGB256);
1202 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
1203 } else
1204 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1205
1206 if (intel_sdvo->is_tv &&
1207 !intel_sdvo_set_tv_format(intel_sdvo))
1208 return;
1209
1210 /* We have tried to get input timing in mode_fixup, and filled into
1211 * adjusted_mode.
1212 */
1213 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1214 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1215 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1216 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1217 DRM_INFO("Setting input timings on %s failed\n",
1218 SDVO_NAME(intel_sdvo));
1219
1220 switch (intel_crtc->config.pixel_multiplier) {
1221 default:
1222 WARN(1, "unknown pixel mutlipler specified\n");
1223 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1224 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1225 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1226 }
1227 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1228 return;
1229
1230 /* Set the SDVO control regs. */
1231 if (INTEL_INFO(dev)->gen >= 4) {
1232 /* The real mode polarity is set by the SDVO commands, using
1233 * struct intel_sdvo_dtd. */
1234 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1235 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
1236 sdvox |= intel_sdvo->color_range;
1237 if (INTEL_INFO(dev)->gen < 5)
1238 sdvox |= SDVO_BORDER_ENABLE;
1239 } else {
1240 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1241 switch (intel_sdvo->sdvo_reg) {
1242 case GEN3_SDVOB:
1243 sdvox &= SDVOB_PRESERVE_MASK;
1244 break;
1245 case GEN3_SDVOC:
1246 sdvox &= SDVOC_PRESERVE_MASK;
1247 break;
1248 }
1249 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1250 }
1251
1252 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1253 sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
1254 else
1255 sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe);
1256
1257 if (intel_sdvo->has_hdmi_audio)
1258 sdvox |= SDVO_AUDIO_ENABLE;
1259
1260 if (INTEL_INFO(dev)->gen >= 4) {
1261 /* done in crtc_mode_set as the dpll_md reg must be written early */
1262 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1263 /* done in crtc_mode_set as it lives inside the dpll register */
1264 } else {
1265 sdvox |= (intel_crtc->config.pixel_multiplier - 1)
1266 << SDVO_PORT_MULTIPLY_SHIFT;
1267 }
1268
1269 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1270 INTEL_INFO(dev)->gen < 5)
1271 sdvox |= SDVO_STALL_SELECT;
1272 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1273 }
1274
1275 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1276 {
1277 struct intel_sdvo_connector *intel_sdvo_connector =
1278 to_intel_sdvo_connector(&connector->base);
1279 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1280 u16 active_outputs = 0;
1281
1282 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1283
1284 if (active_outputs & intel_sdvo_connector->output_flag)
1285 return true;
1286 else
1287 return false;
1288 }
1289
1290 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1291 enum pipe *pipe)
1292 {
1293 struct drm_device *dev = encoder->base.dev;
1294 struct drm_i915_private *dev_priv = dev->dev_private;
1295 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1296 u16 active_outputs = 0;
1297 u32 tmp;
1298
1299 tmp = I915_READ(intel_sdvo->sdvo_reg);
1300 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1301
1302 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
1303 return false;
1304
1305 if (HAS_PCH_CPT(dev))
1306 *pipe = PORT_TO_PIPE_CPT(tmp);
1307 else
1308 *pipe = PORT_TO_PIPE(tmp);
1309
1310 return true;
1311 }
1312
1313 static void intel_sdvo_get_config(struct intel_encoder *encoder,
1314 struct intel_crtc_config *pipe_config)
1315 {
1316 struct drm_device *dev = encoder->base.dev;
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1318 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1319 struct intel_sdvo_dtd dtd;
1320 int encoder_pixel_multiplier = 0;
1321 u32 flags = 0, sdvox;
1322 u8 val;
1323 bool ret;
1324
1325 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1326 if (!ret) {
1327 /* Some sdvo encoders are not spec compliant and don't
1328 * implement the mandatory get_timings function. */
1329 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
1330 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1331 } else {
1332 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1333 flags |= DRM_MODE_FLAG_PHSYNC;
1334 else
1335 flags |= DRM_MODE_FLAG_NHSYNC;
1336
1337 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1338 flags |= DRM_MODE_FLAG_PVSYNC;
1339 else
1340 flags |= DRM_MODE_FLAG_NVSYNC;
1341 }
1342
1343 pipe_config->adjusted_mode.flags |= flags;
1344
1345 /*
1346 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1347 * the sdvo port register, on all other platforms it is part of the dpll
1348 * state. Since the general pipe state readout happens before the
1349 * encoder->get_config we so already have a valid pixel multplier on all
1350 * other platfroms.
1351 */
1352 if (IS_I915G(dev) || IS_I915GM(dev)) {
1353 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1354 pipe_config->pixel_multiplier =
1355 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1356 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1357 }
1358
1359 /* Cross check the port pixel multiplier with the sdvo encoder state. */
1360 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
1361 switch (val) {
1362 case SDVO_CLOCK_RATE_MULT_1X:
1363 encoder_pixel_multiplier = 1;
1364 break;
1365 case SDVO_CLOCK_RATE_MULT_2X:
1366 encoder_pixel_multiplier = 2;
1367 break;
1368 case SDVO_CLOCK_RATE_MULT_4X:
1369 encoder_pixel_multiplier = 4;
1370 break;
1371 }
1372
1373 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1374 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1375 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1376 }
1377
1378 static void intel_disable_sdvo(struct intel_encoder *encoder)
1379 {
1380 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1381 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1382 u32 temp;
1383
1384 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1385 if (0)
1386 intel_sdvo_set_encoder_power_state(intel_sdvo,
1387 DRM_MODE_DPMS_OFF);
1388
1389 temp = I915_READ(intel_sdvo->sdvo_reg);
1390 if ((temp & SDVO_ENABLE) != 0) {
1391 /* HW workaround for IBX, we need to move the port to
1392 * transcoder A before disabling it. */
1393 if (HAS_PCH_IBX(encoder->base.dev)) {
1394 struct drm_crtc *crtc = encoder->base.crtc;
1395 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1396
1397 if (temp & SDVO_PIPE_B_SELECT) {
1398 temp &= ~SDVO_PIPE_B_SELECT;
1399 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1400 POSTING_READ(intel_sdvo->sdvo_reg);
1401
1402 /* Again we need to write this twice. */
1403 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1404 POSTING_READ(intel_sdvo->sdvo_reg);
1405
1406 /* Transcoder selection bits only update
1407 * effectively on vblank. */
1408 if (crtc)
1409 intel_wait_for_vblank(encoder->base.dev, pipe);
1410 else
1411 msleep(50);
1412 }
1413 }
1414
1415 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1416 }
1417 }
1418
1419 static void intel_enable_sdvo(struct intel_encoder *encoder)
1420 {
1421 struct drm_device *dev = encoder->base.dev;
1422 struct drm_i915_private *dev_priv = dev->dev_private;
1423 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1424 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1425 u32 temp;
1426 bool input1, input2;
1427 int i;
1428 u8 status;
1429
1430 temp = I915_READ(intel_sdvo->sdvo_reg);
1431 if ((temp & SDVO_ENABLE) == 0) {
1432 /* HW workaround for IBX, we need to move the port
1433 * to transcoder A before disabling it, so restore it here. */
1434 if (HAS_PCH_IBX(dev))
1435 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
1436
1437 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
1438 }
1439 for (i = 0; i < 2; i++)
1440 intel_wait_for_vblank(dev, intel_crtc->pipe);
1441
1442 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1443 /* Warn if the device reported failure to sync.
1444 * A lot of SDVO devices fail to notify of sync, but it's
1445 * a given it the status is a success, we succeeded.
1446 */
1447 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1448 DRM_DEBUG_KMS("First %s output reported failure to "
1449 "sync\n", SDVO_NAME(intel_sdvo));
1450 }
1451
1452 if (0)
1453 intel_sdvo_set_encoder_power_state(intel_sdvo,
1454 DRM_MODE_DPMS_ON);
1455 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1456 }
1457
1458 /* Special dpms function to support cloning between dvo/sdvo/crt. */
1459 static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
1460 {
1461 struct drm_crtc *crtc;
1462 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1463
1464 /* dvo supports only 2 dpms states. */
1465 if (mode != DRM_MODE_DPMS_ON)
1466 mode = DRM_MODE_DPMS_OFF;
1467
1468 if (mode == connector->dpms)
1469 return;
1470
1471 connector->dpms = mode;
1472
1473 /* Only need to change hw state when actually enabled */
1474 crtc = intel_sdvo->base.base.crtc;
1475 if (!crtc) {
1476 intel_sdvo->base.connectors_active = false;
1477 return;
1478 }
1479
1480 /* We set active outputs manually below in case pipe dpms doesn't change
1481 * due to cloning. */
1482 if (mode != DRM_MODE_DPMS_ON) {
1483 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1484 if (0)
1485 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1486
1487 intel_sdvo->base.connectors_active = false;
1488
1489 intel_crtc_update_dpms(crtc);
1490 } else {
1491 intel_sdvo->base.connectors_active = true;
1492
1493 intel_crtc_update_dpms(crtc);
1494
1495 if (0)
1496 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1497 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1498 }
1499
1500 intel_modeset_check_state(connector->dev);
1501 }
1502
1503 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1504 struct drm_display_mode *mode)
1505 {
1506 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1507
1508 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1509 return MODE_NO_DBLESCAN;
1510
1511 if (intel_sdvo->pixel_clock_min > mode->clock)
1512 return MODE_CLOCK_LOW;
1513
1514 if (intel_sdvo->pixel_clock_max < mode->clock)
1515 return MODE_CLOCK_HIGH;
1516
1517 if (intel_sdvo->is_lvds) {
1518 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1519 return MODE_PANEL;
1520
1521 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1522 return MODE_PANEL;
1523 }
1524
1525 return MODE_OK;
1526 }
1527
1528 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1529 {
1530 BUILD_BUG_ON(sizeof(*caps) != 8);
1531 if (!intel_sdvo_get_value(intel_sdvo,
1532 SDVO_CMD_GET_DEVICE_CAPS,
1533 caps, sizeof(*caps)))
1534 return false;
1535
1536 DRM_DEBUG_KMS("SDVO capabilities:\n"
1537 " vendor_id: %d\n"
1538 " device_id: %d\n"
1539 " device_rev_id: %d\n"
1540 " sdvo_version_major: %d\n"
1541 " sdvo_version_minor: %d\n"
1542 " sdvo_inputs_mask: %d\n"
1543 " smooth_scaling: %d\n"
1544 " sharp_scaling: %d\n"
1545 " up_scaling: %d\n"
1546 " down_scaling: %d\n"
1547 " stall_support: %d\n"
1548 " output_flags: %d\n",
1549 caps->vendor_id,
1550 caps->device_id,
1551 caps->device_rev_id,
1552 caps->sdvo_version_major,
1553 caps->sdvo_version_minor,
1554 caps->sdvo_inputs_mask,
1555 caps->smooth_scaling,
1556 caps->sharp_scaling,
1557 caps->up_scaling,
1558 caps->down_scaling,
1559 caps->stall_support,
1560 caps->output_flags);
1561
1562 return true;
1563 }
1564
1565 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
1566 {
1567 struct drm_device *dev = intel_sdvo->base.base.dev;
1568 uint16_t hotplug;
1569
1570 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1571 * on the line. */
1572 if (IS_I945G(dev) || IS_I945GM(dev))
1573 return 0;
1574
1575 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1576 &hotplug, sizeof(hotplug)))
1577 return 0;
1578
1579 return hotplug;
1580 }
1581
1582 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
1583 {
1584 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1585
1586 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1587 &intel_sdvo->hotplug_active, 2);
1588 }
1589
1590 static bool
1591 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1592 {
1593 /* Is there more than one type of output? */
1594 return hweight16(intel_sdvo->caps.output_flags) > 1;
1595 }
1596
1597 static struct edid *
1598 intel_sdvo_get_edid(struct drm_connector *connector)
1599 {
1600 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1601 return drm_get_edid(connector, &sdvo->ddc);
1602 }
1603
1604 /* Mac mini hack -- use the same DDC as the analog connector */
1605 static struct edid *
1606 intel_sdvo_get_analog_edid(struct drm_connector *connector)
1607 {
1608 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1609
1610 return drm_get_edid(connector,
1611 intel_gmbus_get_adapter(dev_priv,
1612 dev_priv->vbt.crt_ddc_pin));
1613 }
1614
1615 static enum drm_connector_status
1616 intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
1617 {
1618 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1619 enum drm_connector_status status;
1620 struct edid *edid;
1621
1622 edid = intel_sdvo_get_edid(connector);
1623
1624 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
1625 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
1626
1627 /*
1628 * Don't use the 1 as the argument of DDC bus switch to get
1629 * the EDID. It is used for SDVO SPD ROM.
1630 */
1631 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1632 intel_sdvo->ddc_bus = ddc;
1633 edid = intel_sdvo_get_edid(connector);
1634 if (edid)
1635 break;
1636 }
1637 /*
1638 * If we found the EDID on the other bus,
1639 * assume that is the correct DDC bus.
1640 */
1641 if (edid == NULL)
1642 intel_sdvo->ddc_bus = saved_ddc;
1643 }
1644
1645 /*
1646 * When there is no edid and no monitor is connected with VGA
1647 * port, try to use the CRT ddc to read the EDID for DVI-connector.
1648 */
1649 if (edid == NULL)
1650 edid = intel_sdvo_get_analog_edid(connector);
1651
1652 status = connector_status_unknown;
1653 if (edid != NULL) {
1654 /* DDC bus is shared, match EDID to connector type */
1655 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1656 status = connector_status_connected;
1657 if (intel_sdvo->is_hdmi) {
1658 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1659 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1660 intel_sdvo->rgb_quant_range_selectable =
1661 drm_rgb_quant_range_selectable(edid);
1662 }
1663 } else
1664 status = connector_status_disconnected;
1665 kfree(edid);
1666 }
1667
1668 if (status == connector_status_connected) {
1669 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1670 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1671 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
1672 }
1673
1674 return status;
1675 }
1676
1677 static bool
1678 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1679 struct edid *edid)
1680 {
1681 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1682 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1683
1684 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1685 connector_is_digital, monitor_is_digital);
1686 return connector_is_digital == monitor_is_digital;
1687 }
1688
1689 static enum drm_connector_status
1690 intel_sdvo_detect(struct drm_connector *connector, bool force)
1691 {
1692 uint16_t response;
1693 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1694 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1695 enum drm_connector_status ret;
1696
1697 if (!intel_sdvo_get_value(intel_sdvo,
1698 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1699 &response, 2))
1700 return connector_status_unknown;
1701
1702 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1703 response & 0xff, response >> 8,
1704 intel_sdvo_connector->output_flag);
1705
1706 if (response == 0)
1707 return connector_status_disconnected;
1708
1709 intel_sdvo->attached_output = response;
1710
1711 intel_sdvo->has_hdmi_monitor = false;
1712 intel_sdvo->has_hdmi_audio = false;
1713 intel_sdvo->rgb_quant_range_selectable = false;
1714
1715 if ((intel_sdvo_connector->output_flag & response) == 0)
1716 ret = connector_status_disconnected;
1717 else if (IS_TMDS(intel_sdvo_connector))
1718 ret = intel_sdvo_tmds_sink_detect(connector);
1719 else {
1720 struct edid *edid;
1721
1722 /* if we have an edid check it matches the connection */
1723 edid = intel_sdvo_get_edid(connector);
1724 if (edid == NULL)
1725 edid = intel_sdvo_get_analog_edid(connector);
1726 if (edid != NULL) {
1727 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1728 edid))
1729 ret = connector_status_connected;
1730 else
1731 ret = connector_status_disconnected;
1732
1733 kfree(edid);
1734 } else
1735 ret = connector_status_connected;
1736 }
1737
1738 /* May update encoder flag for like clock for SDVO TV, etc.*/
1739 if (ret == connector_status_connected) {
1740 intel_sdvo->is_tv = false;
1741 intel_sdvo->is_lvds = false;
1742
1743 if (response & SDVO_TV_MASK)
1744 intel_sdvo->is_tv = true;
1745 if (response & SDVO_LVDS_MASK)
1746 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
1747 }
1748
1749 return ret;
1750 }
1751
1752 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1753 {
1754 struct edid *edid;
1755
1756 /* set the bus switch and get the modes */
1757 edid = intel_sdvo_get_edid(connector);
1758
1759 /*
1760 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1761 * link between analog and digital outputs. So, if the regular SDVO
1762 * DDC fails, check to see if the analog output is disconnected, in
1763 * which case we'll look there for the digital DDC data.
1764 */
1765 if (edid == NULL)
1766 edid = intel_sdvo_get_analog_edid(connector);
1767
1768 if (edid != NULL) {
1769 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1770 edid)) {
1771 drm_mode_connector_update_edid_property(connector, edid);
1772 drm_add_edid_modes(connector, edid);
1773 }
1774
1775 kfree(edid);
1776 }
1777 }
1778
1779 /*
1780 * Set of SDVO TV modes.
1781 * Note! This is in reply order (see loop in get_tv_modes).
1782 * XXX: all 60Hz refresh?
1783 */
1784 static const struct drm_display_mode sdvo_tv_modes[] = {
1785 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1786 416, 0, 200, 201, 232, 233, 0,
1787 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1788 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1789 416, 0, 240, 241, 272, 273, 0,
1790 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1791 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1792 496, 0, 300, 301, 332, 333, 0,
1793 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1794 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1795 736, 0, 350, 351, 382, 383, 0,
1796 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1797 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1798 736, 0, 400, 401, 432, 433, 0,
1799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1800 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1801 736, 0, 480, 481, 512, 513, 0,
1802 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1803 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1804 800, 0, 480, 481, 512, 513, 0,
1805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1806 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1807 800, 0, 576, 577, 608, 609, 0,
1808 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1809 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1810 816, 0, 350, 351, 382, 383, 0,
1811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1812 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1813 816, 0, 400, 401, 432, 433, 0,
1814 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1815 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1816 816, 0, 480, 481, 512, 513, 0,
1817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1818 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1819 816, 0, 540, 541, 572, 573, 0,
1820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1821 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1822 816, 0, 576, 577, 608, 609, 0,
1823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1824 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1825 864, 0, 576, 577, 608, 609, 0,
1826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1827 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1828 896, 0, 600, 601, 632, 633, 0,
1829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1830 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1831 928, 0, 624, 625, 656, 657, 0,
1832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1833 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1834 1016, 0, 766, 767, 798, 799, 0,
1835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1836 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1837 1120, 0, 768, 769, 800, 801, 0,
1838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1839 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1840 1376, 0, 1024, 1025, 1056, 1057, 0,
1841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1842 };
1843
1844 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1845 {
1846 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1847 struct intel_sdvo_sdtv_resolution_request tv_res;
1848 uint32_t reply = 0, format_map = 0;
1849 int i;
1850
1851 /* Read the list of supported input resolutions for the selected TV
1852 * format.
1853 */
1854 format_map = 1 << intel_sdvo->tv_format_index;
1855 memcpy(&tv_res, &format_map,
1856 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
1857
1858 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1859 return;
1860
1861 BUILD_BUG_ON(sizeof(tv_res) != 3);
1862 if (!intel_sdvo_write_cmd(intel_sdvo,
1863 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1864 &tv_res, sizeof(tv_res)))
1865 return;
1866 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
1867 return;
1868
1869 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1870 if (reply & (1 << i)) {
1871 struct drm_display_mode *nmode;
1872 nmode = drm_mode_duplicate(connector->dev,
1873 &sdvo_tv_modes[i]);
1874 if (nmode)
1875 drm_mode_probed_add(connector, nmode);
1876 }
1877 }
1878
1879 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1880 {
1881 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1882 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1883 struct drm_display_mode *newmode;
1884
1885 /*
1886 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
1887 * SDVO->LVDS transcoders can't cope with the EDID mode.
1888 */
1889 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
1890 newmode = drm_mode_duplicate(connector->dev,
1891 dev_priv->vbt.sdvo_lvds_vbt_mode);
1892 if (newmode != NULL) {
1893 /* Guarantee the mode is preferred */
1894 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1895 DRM_MODE_TYPE_DRIVER);
1896 drm_mode_probed_add(connector, newmode);
1897 }
1898 }
1899
1900 /*
1901 * Attempt to get the mode list from DDC.
1902 * Assume that the preferred modes are
1903 * arranged in priority order.
1904 */
1905 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1906
1907 list_for_each_entry(newmode, &connector->probed_modes, head) {
1908 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1909 intel_sdvo->sdvo_lvds_fixed_mode =
1910 drm_mode_duplicate(connector->dev, newmode);
1911
1912 intel_sdvo->is_lvds = true;
1913 break;
1914 }
1915 }
1916
1917 }
1918
1919 static int intel_sdvo_get_modes(struct drm_connector *connector)
1920 {
1921 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1922
1923 if (IS_TV(intel_sdvo_connector))
1924 intel_sdvo_get_tv_modes(connector);
1925 else if (IS_LVDS(intel_sdvo_connector))
1926 intel_sdvo_get_lvds_modes(connector);
1927 else
1928 intel_sdvo_get_ddc_modes(connector);
1929
1930 return !list_empty(&connector->probed_modes);
1931 }
1932
1933 static void
1934 intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1935 {
1936 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1937 struct drm_device *dev = connector->dev;
1938
1939 if (intel_sdvo_connector->left)
1940 drm_property_destroy(dev, intel_sdvo_connector->left);
1941 if (intel_sdvo_connector->right)
1942 drm_property_destroy(dev, intel_sdvo_connector->right);
1943 if (intel_sdvo_connector->top)
1944 drm_property_destroy(dev, intel_sdvo_connector->top);
1945 if (intel_sdvo_connector->bottom)
1946 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1947 if (intel_sdvo_connector->hpos)
1948 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1949 if (intel_sdvo_connector->vpos)
1950 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1951 if (intel_sdvo_connector->saturation)
1952 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1953 if (intel_sdvo_connector->contrast)
1954 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1955 if (intel_sdvo_connector->hue)
1956 drm_property_destroy(dev, intel_sdvo_connector->hue);
1957 if (intel_sdvo_connector->sharpness)
1958 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1959 if (intel_sdvo_connector->flicker_filter)
1960 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1961 if (intel_sdvo_connector->flicker_filter_2d)
1962 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1963 if (intel_sdvo_connector->flicker_filter_adaptive)
1964 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1965 if (intel_sdvo_connector->tv_luma_filter)
1966 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1967 if (intel_sdvo_connector->tv_chroma_filter)
1968 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
1969 if (intel_sdvo_connector->dot_crawl)
1970 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
1971 if (intel_sdvo_connector->brightness)
1972 drm_property_destroy(dev, intel_sdvo_connector->brightness);
1973 }
1974
1975 static void intel_sdvo_destroy(struct drm_connector *connector)
1976 {
1977 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1978
1979 if (intel_sdvo_connector->tv_format)
1980 drm_property_destroy(connector->dev,
1981 intel_sdvo_connector->tv_format);
1982
1983 intel_sdvo_destroy_enhance_property(connector);
1984 drm_sysfs_connector_remove(connector);
1985 drm_connector_cleanup(connector);
1986 kfree(intel_sdvo_connector);
1987 }
1988
1989 static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1990 {
1991 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1992 struct edid *edid;
1993 bool has_audio = false;
1994
1995 if (!intel_sdvo->is_hdmi)
1996 return false;
1997
1998 edid = intel_sdvo_get_edid(connector);
1999 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
2000 has_audio = drm_detect_monitor_audio(edid);
2001 kfree(edid);
2002
2003 return has_audio;
2004 }
2005
2006 static int
2007 intel_sdvo_set_property(struct drm_connector *connector,
2008 struct drm_property *property,
2009 uint64_t val)
2010 {
2011 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2012 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2013 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2014 uint16_t temp_value;
2015 uint8_t cmd;
2016 int ret;
2017
2018 ret = drm_object_property_set_value(&connector->base, property, val);
2019 if (ret)
2020 return ret;
2021
2022 if (property == dev_priv->force_audio_property) {
2023 int i = val;
2024 bool has_audio;
2025
2026 if (i == intel_sdvo_connector->force_audio)
2027 return 0;
2028
2029 intel_sdvo_connector->force_audio = i;
2030
2031 if (i == HDMI_AUDIO_AUTO)
2032 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2033 else
2034 has_audio = (i == HDMI_AUDIO_ON);
2035
2036 if (has_audio == intel_sdvo->has_hdmi_audio)
2037 return 0;
2038
2039 intel_sdvo->has_hdmi_audio = has_audio;
2040 goto done;
2041 }
2042
2043 if (property == dev_priv->broadcast_rgb_property) {
2044 bool old_auto = intel_sdvo->color_range_auto;
2045 uint32_t old_range = intel_sdvo->color_range;
2046
2047 switch (val) {
2048 case INTEL_BROADCAST_RGB_AUTO:
2049 intel_sdvo->color_range_auto = true;
2050 break;
2051 case INTEL_BROADCAST_RGB_FULL:
2052 intel_sdvo->color_range_auto = false;
2053 intel_sdvo->color_range = 0;
2054 break;
2055 case INTEL_BROADCAST_RGB_LIMITED:
2056 intel_sdvo->color_range_auto = false;
2057 /* FIXME: this bit is only valid when using TMDS
2058 * encoding and 8 bit per color mode. */
2059 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
2060 break;
2061 default:
2062 return -EINVAL;
2063 }
2064
2065 if (old_auto == intel_sdvo->color_range_auto &&
2066 old_range == intel_sdvo->color_range)
2067 return 0;
2068
2069 goto done;
2070 }
2071
2072 #define CHECK_PROPERTY(name, NAME) \
2073 if (intel_sdvo_connector->name == property) { \
2074 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2075 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2076 cmd = SDVO_CMD_SET_##NAME; \
2077 intel_sdvo_connector->cur_##name = temp_value; \
2078 goto set_value; \
2079 }
2080
2081 if (property == intel_sdvo_connector->tv_format) {
2082 if (val >= TV_FORMAT_NUM)
2083 return -EINVAL;
2084
2085 if (intel_sdvo->tv_format_index ==
2086 intel_sdvo_connector->tv_format_supported[val])
2087 return 0;
2088
2089 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
2090 goto done;
2091 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
2092 temp_value = val;
2093 if (intel_sdvo_connector->left == property) {
2094 drm_object_property_set_value(&connector->base,
2095 intel_sdvo_connector->right, val);
2096 if (intel_sdvo_connector->left_margin == temp_value)
2097 return 0;
2098
2099 intel_sdvo_connector->left_margin = temp_value;
2100 intel_sdvo_connector->right_margin = temp_value;
2101 temp_value = intel_sdvo_connector->max_hscan -
2102 intel_sdvo_connector->left_margin;
2103 cmd = SDVO_CMD_SET_OVERSCAN_H;
2104 goto set_value;
2105 } else if (intel_sdvo_connector->right == property) {
2106 drm_object_property_set_value(&connector->base,
2107 intel_sdvo_connector->left, val);
2108 if (intel_sdvo_connector->right_margin == temp_value)
2109 return 0;
2110
2111 intel_sdvo_connector->left_margin = temp_value;
2112 intel_sdvo_connector->right_margin = temp_value;
2113 temp_value = intel_sdvo_connector->max_hscan -
2114 intel_sdvo_connector->left_margin;
2115 cmd = SDVO_CMD_SET_OVERSCAN_H;
2116 goto set_value;
2117 } else if (intel_sdvo_connector->top == property) {
2118 drm_object_property_set_value(&connector->base,
2119 intel_sdvo_connector->bottom, val);
2120 if (intel_sdvo_connector->top_margin == temp_value)
2121 return 0;
2122
2123 intel_sdvo_connector->top_margin = temp_value;
2124 intel_sdvo_connector->bottom_margin = temp_value;
2125 temp_value = intel_sdvo_connector->max_vscan -
2126 intel_sdvo_connector->top_margin;
2127 cmd = SDVO_CMD_SET_OVERSCAN_V;
2128 goto set_value;
2129 } else if (intel_sdvo_connector->bottom == property) {
2130 drm_object_property_set_value(&connector->base,
2131 intel_sdvo_connector->top, val);
2132 if (intel_sdvo_connector->bottom_margin == temp_value)
2133 return 0;
2134
2135 intel_sdvo_connector->top_margin = temp_value;
2136 intel_sdvo_connector->bottom_margin = temp_value;
2137 temp_value = intel_sdvo_connector->max_vscan -
2138 intel_sdvo_connector->top_margin;
2139 cmd = SDVO_CMD_SET_OVERSCAN_V;
2140 goto set_value;
2141 }
2142 CHECK_PROPERTY(hpos, HPOS)
2143 CHECK_PROPERTY(vpos, VPOS)
2144 CHECK_PROPERTY(saturation, SATURATION)
2145 CHECK_PROPERTY(contrast, CONTRAST)
2146 CHECK_PROPERTY(hue, HUE)
2147 CHECK_PROPERTY(brightness, BRIGHTNESS)
2148 CHECK_PROPERTY(sharpness, SHARPNESS)
2149 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2150 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2151 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2152 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2153 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
2154 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
2155 }
2156
2157 return -EINVAL; /* unknown property */
2158
2159 set_value:
2160 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2161 return -EIO;
2162
2163
2164 done:
2165 if (intel_sdvo->base.base.crtc)
2166 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
2167
2168 return 0;
2169 #undef CHECK_PROPERTY
2170 }
2171
2172 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2173 .dpms = intel_sdvo_dpms,
2174 .detect = intel_sdvo_detect,
2175 .fill_modes = drm_helper_probe_single_connector_modes,
2176 .set_property = intel_sdvo_set_property,
2177 .destroy = intel_sdvo_destroy,
2178 };
2179
2180 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2181 .get_modes = intel_sdvo_get_modes,
2182 .mode_valid = intel_sdvo_mode_valid,
2183 .best_encoder = intel_best_encoder,
2184 };
2185
2186 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2187 {
2188 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
2189
2190 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
2191 drm_mode_destroy(encoder->dev,
2192 intel_sdvo->sdvo_lvds_fixed_mode);
2193
2194 i2c_del_adapter(&intel_sdvo->ddc);
2195 intel_encoder_destroy(encoder);
2196 }
2197
2198 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2199 .destroy = intel_sdvo_enc_destroy,
2200 };
2201
2202 static void
2203 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2204 {
2205 uint16_t mask = 0;
2206 unsigned int num_bits;
2207
2208 /* Make a mask of outputs less than or equal to our own priority in the
2209 * list.
2210 */
2211 switch (sdvo->controlled_output) {
2212 case SDVO_OUTPUT_LVDS1:
2213 mask |= SDVO_OUTPUT_LVDS1;
2214 case SDVO_OUTPUT_LVDS0:
2215 mask |= SDVO_OUTPUT_LVDS0;
2216 case SDVO_OUTPUT_TMDS1:
2217 mask |= SDVO_OUTPUT_TMDS1;
2218 case SDVO_OUTPUT_TMDS0:
2219 mask |= SDVO_OUTPUT_TMDS0;
2220 case SDVO_OUTPUT_RGB1:
2221 mask |= SDVO_OUTPUT_RGB1;
2222 case SDVO_OUTPUT_RGB0:
2223 mask |= SDVO_OUTPUT_RGB0;
2224 break;
2225 }
2226
2227 /* Count bits to find what number we are in the priority list. */
2228 mask &= sdvo->caps.output_flags;
2229 num_bits = hweight16(mask);
2230 /* If more than 3 outputs, default to DDC bus 3 for now. */
2231 if (num_bits > 3)
2232 num_bits = 3;
2233
2234 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2235 sdvo->ddc_bus = 1 << num_bits;
2236 }
2237
2238 /**
2239 * Choose the appropriate DDC bus for control bus switch command for this
2240 * SDVO output based on the controlled output.
2241 *
2242 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2243 * outputs, then LVDS outputs.
2244 */
2245 static void
2246 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2247 struct intel_sdvo *sdvo, u32 reg)
2248 {
2249 struct sdvo_device_mapping *mapping;
2250
2251 if (sdvo->is_sdvob)
2252 mapping = &(dev_priv->sdvo_mappings[0]);
2253 else
2254 mapping = &(dev_priv->sdvo_mappings[1]);
2255
2256 if (mapping->initialized)
2257 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2258 else
2259 intel_sdvo_guess_ddc_bus(sdvo);
2260 }
2261
2262 static void
2263 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2264 struct intel_sdvo *sdvo, u32 reg)
2265 {
2266 struct sdvo_device_mapping *mapping;
2267 u8 pin;
2268
2269 if (sdvo->is_sdvob)
2270 mapping = &dev_priv->sdvo_mappings[0];
2271 else
2272 mapping = &dev_priv->sdvo_mappings[1];
2273
2274 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
2275 pin = mapping->i2c_pin;
2276 else
2277 pin = GMBUS_PORT_DPB;
2278
2279 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2280
2281 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2282 * our code totally fails once we start using gmbus. Hence fall back to
2283 * bit banging for now. */
2284 intel_gmbus_force_bit(sdvo->i2c, true);
2285 }
2286
2287 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2288 static void
2289 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2290 {
2291 intel_gmbus_force_bit(sdvo->i2c, false);
2292 }
2293
2294 static bool
2295 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
2296 {
2297 return intel_sdvo_check_supp_encode(intel_sdvo);
2298 }
2299
2300 static u8
2301 intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
2302 {
2303 struct drm_i915_private *dev_priv = dev->dev_private;
2304 struct sdvo_device_mapping *my_mapping, *other_mapping;
2305
2306 if (sdvo->is_sdvob) {
2307 my_mapping = &dev_priv->sdvo_mappings[0];
2308 other_mapping = &dev_priv->sdvo_mappings[1];
2309 } else {
2310 my_mapping = &dev_priv->sdvo_mappings[1];
2311 other_mapping = &dev_priv->sdvo_mappings[0];
2312 }
2313
2314 /* If the BIOS described our SDVO device, take advantage of it. */
2315 if (my_mapping->slave_addr)
2316 return my_mapping->slave_addr;
2317
2318 /* If the BIOS only described a different SDVO device, use the
2319 * address that it isn't using.
2320 */
2321 if (other_mapping->slave_addr) {
2322 if (other_mapping->slave_addr == 0x70)
2323 return 0x72;
2324 else
2325 return 0x70;
2326 }
2327
2328 /* No SDVO device info is found for another DVO port,
2329 * so use mapping assumption we had before BIOS parsing.
2330 */
2331 if (sdvo->is_sdvob)
2332 return 0x70;
2333 else
2334 return 0x72;
2335 }
2336
2337 static void
2338 intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2339 struct intel_sdvo *encoder)
2340 {
2341 drm_connector_init(encoder->base.base.dev,
2342 &connector->base.base,
2343 &intel_sdvo_connector_funcs,
2344 connector->base.base.connector_type);
2345
2346 drm_connector_helper_add(&connector->base.base,
2347 &intel_sdvo_connector_helper_funcs);
2348
2349 connector->base.base.interlace_allowed = 1;
2350 connector->base.base.doublescan_allowed = 0;
2351 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2352 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2353
2354 intel_connector_attach_encoder(&connector->base, &encoder->base);
2355 drm_sysfs_connector_add(&connector->base.base);
2356 }
2357
2358 static void
2359 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2360 struct intel_sdvo_connector *connector)
2361 {
2362 struct drm_device *dev = connector->base.base.dev;
2363
2364 intel_attach_force_audio_property(&connector->base.base);
2365 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
2366 intel_attach_broadcast_rgb_property(&connector->base.base);
2367 intel_sdvo->color_range_auto = true;
2368 }
2369 }
2370
2371 static bool
2372 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2373 {
2374 struct drm_encoder *encoder = &intel_sdvo->base.base;
2375 struct drm_connector *connector;
2376 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2377 struct intel_connector *intel_connector;
2378 struct intel_sdvo_connector *intel_sdvo_connector;
2379
2380 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2381 if (!intel_sdvo_connector)
2382 return false;
2383
2384 if (device == 0) {
2385 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2386 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2387 } else if (device == 1) {
2388 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2389 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2390 }
2391
2392 intel_connector = &intel_sdvo_connector->base;
2393 connector = &intel_connector->base;
2394 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2395 intel_sdvo_connector->output_flag) {
2396 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2397 /* Some SDVO devices have one-shot hotplug interrupts.
2398 * Ensure that they get re-enabled when an interrupt happens.
2399 */
2400 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2401 intel_sdvo_enable_hotplug(intel_encoder);
2402 } else {
2403 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2404 }
2405 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2406 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2407
2408 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2409 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2410 intel_sdvo->is_hdmi = true;
2411 }
2412
2413 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2414 if (intel_sdvo->is_hdmi)
2415 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2416
2417 return true;
2418 }
2419
2420 static bool
2421 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2422 {
2423 struct drm_encoder *encoder = &intel_sdvo->base.base;
2424 struct drm_connector *connector;
2425 struct intel_connector *intel_connector;
2426 struct intel_sdvo_connector *intel_sdvo_connector;
2427
2428 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2429 if (!intel_sdvo_connector)
2430 return false;
2431
2432 intel_connector = &intel_sdvo_connector->base;
2433 connector = &intel_connector->base;
2434 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2435 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2436
2437 intel_sdvo->controlled_output |= type;
2438 intel_sdvo_connector->output_flag = type;
2439
2440 intel_sdvo->is_tv = true;
2441
2442 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2443
2444 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2445 goto err;
2446
2447 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2448 goto err;
2449
2450 return true;
2451
2452 err:
2453 intel_sdvo_destroy(connector);
2454 return false;
2455 }
2456
2457 static bool
2458 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2459 {
2460 struct drm_encoder *encoder = &intel_sdvo->base.base;
2461 struct drm_connector *connector;
2462 struct intel_connector *intel_connector;
2463 struct intel_sdvo_connector *intel_sdvo_connector;
2464
2465 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2466 if (!intel_sdvo_connector)
2467 return false;
2468
2469 intel_connector = &intel_sdvo_connector->base;
2470 connector = &intel_connector->base;
2471 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2472 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2473 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2474
2475 if (device == 0) {
2476 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2477 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2478 } else if (device == 1) {
2479 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2480 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2481 }
2482
2483 intel_sdvo_connector_init(intel_sdvo_connector,
2484 intel_sdvo);
2485 return true;
2486 }
2487
2488 static bool
2489 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2490 {
2491 struct drm_encoder *encoder = &intel_sdvo->base.base;
2492 struct drm_connector *connector;
2493 struct intel_connector *intel_connector;
2494 struct intel_sdvo_connector *intel_sdvo_connector;
2495
2496 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2497 if (!intel_sdvo_connector)
2498 return false;
2499
2500 intel_connector = &intel_sdvo_connector->base;
2501 connector = &intel_connector->base;
2502 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2503 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2504
2505 if (device == 0) {
2506 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2507 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2508 } else if (device == 1) {
2509 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2510 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2511 }
2512
2513 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2514 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2515 goto err;
2516
2517 return true;
2518
2519 err:
2520 intel_sdvo_destroy(connector);
2521 return false;
2522 }
2523
2524 static bool
2525 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
2526 {
2527 intel_sdvo->is_tv = false;
2528 intel_sdvo->is_lvds = false;
2529
2530 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2531
2532 if (flags & SDVO_OUTPUT_TMDS0)
2533 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2534 return false;
2535
2536 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2537 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2538 return false;
2539
2540 /* TV has no XXX1 function block */
2541 if (flags & SDVO_OUTPUT_SVID0)
2542 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2543 return false;
2544
2545 if (flags & SDVO_OUTPUT_CVBS0)
2546 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2547 return false;
2548
2549 if (flags & SDVO_OUTPUT_YPRPB0)
2550 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2551 return false;
2552
2553 if (flags & SDVO_OUTPUT_RGB0)
2554 if (!intel_sdvo_analog_init(intel_sdvo, 0))
2555 return false;
2556
2557 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2558 if (!intel_sdvo_analog_init(intel_sdvo, 1))
2559 return false;
2560
2561 if (flags & SDVO_OUTPUT_LVDS0)
2562 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2563 return false;
2564
2565 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2566 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2567 return false;
2568
2569 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2570 unsigned char bytes[2];
2571
2572 intel_sdvo->controlled_output = 0;
2573 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2574 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2575 SDVO_NAME(intel_sdvo),
2576 bytes[0], bytes[1]);
2577 return false;
2578 }
2579 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2580
2581 return true;
2582 }
2583
2584 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2585 {
2586 struct drm_device *dev = intel_sdvo->base.base.dev;
2587 struct drm_connector *connector, *tmp;
2588
2589 list_for_each_entry_safe(connector, tmp,
2590 &dev->mode_config.connector_list, head) {
2591 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2592 intel_sdvo_destroy(connector);
2593 }
2594 }
2595
2596 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2597 struct intel_sdvo_connector *intel_sdvo_connector,
2598 int type)
2599 {
2600 struct drm_device *dev = intel_sdvo->base.base.dev;
2601 struct intel_sdvo_tv_format format;
2602 uint32_t format_map, i;
2603
2604 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2605 return false;
2606
2607 BUILD_BUG_ON(sizeof(format) != 6);
2608 if (!intel_sdvo_get_value(intel_sdvo,
2609 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2610 &format, sizeof(format)))
2611 return false;
2612
2613 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2614
2615 if (format_map == 0)
2616 return false;
2617
2618 intel_sdvo_connector->format_supported_num = 0;
2619 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2620 if (format_map & (1 << i))
2621 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
2622
2623
2624 intel_sdvo_connector->tv_format =
2625 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2626 "mode", intel_sdvo_connector->format_supported_num);
2627 if (!intel_sdvo_connector->tv_format)
2628 return false;
2629
2630 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2631 drm_property_add_enum(
2632 intel_sdvo_connector->tv_format, i,
2633 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2634
2635 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
2636 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2637 intel_sdvo_connector->tv_format, 0);
2638 return true;
2639
2640 }
2641
2642 #define ENHANCEMENT(name, NAME) do { \
2643 if (enhancements.name) { \
2644 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2645 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2646 return false; \
2647 intel_sdvo_connector->max_##name = data_value[0]; \
2648 intel_sdvo_connector->cur_##name = response; \
2649 intel_sdvo_connector->name = \
2650 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
2651 if (!intel_sdvo_connector->name) return false; \
2652 drm_object_attach_property(&connector->base, \
2653 intel_sdvo_connector->name, \
2654 intel_sdvo_connector->cur_##name); \
2655 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2656 data_value[0], data_value[1], response); \
2657 } \
2658 } while (0)
2659
2660 static bool
2661 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2662 struct intel_sdvo_connector *intel_sdvo_connector,
2663 struct intel_sdvo_enhancements_reply enhancements)
2664 {
2665 struct drm_device *dev = intel_sdvo->base.base.dev;
2666 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2667 uint16_t response, data_value[2];
2668
2669 /* when horizontal overscan is supported, Add the left/right property */
2670 if (enhancements.overscan_h) {
2671 if (!intel_sdvo_get_value(intel_sdvo,
2672 SDVO_CMD_GET_MAX_OVERSCAN_H,
2673 &data_value, 4))
2674 return false;
2675
2676 if (!intel_sdvo_get_value(intel_sdvo,
2677 SDVO_CMD_GET_OVERSCAN_H,
2678 &response, 2))
2679 return false;
2680
2681 intel_sdvo_connector->max_hscan = data_value[0];
2682 intel_sdvo_connector->left_margin = data_value[0] - response;
2683 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2684 intel_sdvo_connector->left =
2685 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
2686 if (!intel_sdvo_connector->left)
2687 return false;
2688
2689 drm_object_attach_property(&connector->base,
2690 intel_sdvo_connector->left,
2691 intel_sdvo_connector->left_margin);
2692
2693 intel_sdvo_connector->right =
2694 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
2695 if (!intel_sdvo_connector->right)
2696 return false;
2697
2698 drm_object_attach_property(&connector->base,
2699 intel_sdvo_connector->right,
2700 intel_sdvo_connector->right_margin);
2701 DRM_DEBUG_KMS("h_overscan: max %d, "
2702 "default %d, current %d\n",
2703 data_value[0], data_value[1], response);
2704 }
2705
2706 if (enhancements.overscan_v) {
2707 if (!intel_sdvo_get_value(intel_sdvo,
2708 SDVO_CMD_GET_MAX_OVERSCAN_V,
2709 &data_value, 4))
2710 return false;
2711
2712 if (!intel_sdvo_get_value(intel_sdvo,
2713 SDVO_CMD_GET_OVERSCAN_V,
2714 &response, 2))
2715 return false;
2716
2717 intel_sdvo_connector->max_vscan = data_value[0];
2718 intel_sdvo_connector->top_margin = data_value[0] - response;
2719 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2720 intel_sdvo_connector->top =
2721 drm_property_create_range(dev, 0,
2722 "top_margin", 0, data_value[0]);
2723 if (!intel_sdvo_connector->top)
2724 return false;
2725
2726 drm_object_attach_property(&connector->base,
2727 intel_sdvo_connector->top,
2728 intel_sdvo_connector->top_margin);
2729
2730 intel_sdvo_connector->bottom =
2731 drm_property_create_range(dev, 0,
2732 "bottom_margin", 0, data_value[0]);
2733 if (!intel_sdvo_connector->bottom)
2734 return false;
2735
2736 drm_object_attach_property(&connector->base,
2737 intel_sdvo_connector->bottom,
2738 intel_sdvo_connector->bottom_margin);
2739 DRM_DEBUG_KMS("v_overscan: max %d, "
2740 "default %d, current %d\n",
2741 data_value[0], data_value[1], response);
2742 }
2743
2744 ENHANCEMENT(hpos, HPOS);
2745 ENHANCEMENT(vpos, VPOS);
2746 ENHANCEMENT(saturation, SATURATION);
2747 ENHANCEMENT(contrast, CONTRAST);
2748 ENHANCEMENT(hue, HUE);
2749 ENHANCEMENT(sharpness, SHARPNESS);
2750 ENHANCEMENT(brightness, BRIGHTNESS);
2751 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2752 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2753 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2754 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2755 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
2756
2757 if (enhancements.dot_crawl) {
2758 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2759 return false;
2760
2761 intel_sdvo_connector->max_dot_crawl = 1;
2762 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2763 intel_sdvo_connector->dot_crawl =
2764 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
2765 if (!intel_sdvo_connector->dot_crawl)
2766 return false;
2767
2768 drm_object_attach_property(&connector->base,
2769 intel_sdvo_connector->dot_crawl,
2770 intel_sdvo_connector->cur_dot_crawl);
2771 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2772 }
2773
2774 return true;
2775 }
2776
2777 static bool
2778 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2779 struct intel_sdvo_connector *intel_sdvo_connector,
2780 struct intel_sdvo_enhancements_reply enhancements)
2781 {
2782 struct drm_device *dev = intel_sdvo->base.base.dev;
2783 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2784 uint16_t response, data_value[2];
2785
2786 ENHANCEMENT(brightness, BRIGHTNESS);
2787
2788 return true;
2789 }
2790 #undef ENHANCEMENT
2791
2792 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2793 struct intel_sdvo_connector *intel_sdvo_connector)
2794 {
2795 union {
2796 struct intel_sdvo_enhancements_reply reply;
2797 uint16_t response;
2798 } enhancements;
2799
2800 BUILD_BUG_ON(sizeof(enhancements) != 2);
2801
2802 enhancements.response = 0;
2803 intel_sdvo_get_value(intel_sdvo,
2804 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2805 &enhancements, sizeof(enhancements));
2806 if (enhancements.response == 0) {
2807 DRM_DEBUG_KMS("No enhancement is supported\n");
2808 return true;
2809 }
2810
2811 if (IS_TV(intel_sdvo_connector))
2812 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2813 else if (IS_LVDS(intel_sdvo_connector))
2814 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2815 else
2816 return true;
2817 }
2818
2819 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2820 struct i2c_msg *msgs,
2821 int num)
2822 {
2823 struct intel_sdvo *sdvo = adapter->algo_data;
2824
2825 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2826 return -EIO;
2827
2828 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2829 }
2830
2831 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2832 {
2833 struct intel_sdvo *sdvo = adapter->algo_data;
2834 return sdvo->i2c->algo->functionality(sdvo->i2c);
2835 }
2836
2837 static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2838 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2839 .functionality = intel_sdvo_ddc_proxy_func
2840 };
2841
2842 static bool
2843 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2844 struct drm_device *dev)
2845 {
2846 sdvo->ddc.owner = THIS_MODULE;
2847 sdvo->ddc.class = I2C_CLASS_DDC;
2848 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2849 sdvo->ddc.dev.parent = &dev->pdev->dev;
2850 sdvo->ddc.algo_data = sdvo;
2851 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2852
2853 return i2c_add_adapter(&sdvo->ddc) == 0;
2854 }
2855
2856 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2857 {
2858 struct drm_i915_private *dev_priv = dev->dev_private;
2859 struct intel_encoder *intel_encoder;
2860 struct intel_sdvo *intel_sdvo;
2861 int i;
2862 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2863 if (!intel_sdvo)
2864 return false;
2865
2866 intel_sdvo->sdvo_reg = sdvo_reg;
2867 intel_sdvo->is_sdvob = is_sdvob;
2868 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
2869 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
2870 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2871 goto err_i2c_bus;
2872
2873 /* encoder type will be decided later */
2874 intel_encoder = &intel_sdvo->base;
2875 intel_encoder->type = INTEL_OUTPUT_SDVO;
2876 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
2877
2878 /* Read the regs to test if we can talk to the device */
2879 for (i = 0; i < 0x40; i++) {
2880 u8 byte;
2881
2882 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
2883 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2884 SDVO_NAME(intel_sdvo));
2885 goto err;
2886 }
2887 }
2888
2889 intel_encoder->compute_config = intel_sdvo_compute_config;
2890 intel_encoder->disable = intel_disable_sdvo;
2891 intel_encoder->mode_set = intel_sdvo_mode_set;
2892 intel_encoder->enable = intel_enable_sdvo;
2893 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
2894 intel_encoder->get_config = intel_sdvo_get_config;
2895
2896 /* In default case sdvo lvds is false */
2897 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2898 goto err;
2899
2900 if (intel_sdvo_output_setup(intel_sdvo,
2901 intel_sdvo->caps.output_flags) != true) {
2902 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2903 SDVO_NAME(intel_sdvo));
2904 /* Output_setup can leave behind connectors! */
2905 goto err_output;
2906 }
2907
2908 /* Only enable the hotplug irq if we need it, to work around noisy
2909 * hotplug lines.
2910 */
2911 if (intel_sdvo->hotplug_active) {
2912 intel_encoder->hpd_pin =
2913 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
2914 }
2915
2916 /*
2917 * Cloning SDVO with anything is often impossible, since the SDVO
2918 * encoder can request a special input timing mode. And even if that's
2919 * not the case we have evidence that cloning a plain unscaled mode with
2920 * VGA doesn't really work. Furthermore the cloning flags are way too
2921 * simplistic anyway to express such constraints, so just give up on
2922 * cloning for SDVO encoders.
2923 */
2924 intel_sdvo->base.cloneable = false;
2925
2926 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
2927
2928 /* Set the input timing to the screen. Assume always input 0. */
2929 if (!intel_sdvo_set_target_input(intel_sdvo))
2930 goto err_output;
2931
2932 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2933 &intel_sdvo->pixel_clock_min,
2934 &intel_sdvo->pixel_clock_max))
2935 goto err_output;
2936
2937 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2938 "clock range %dMHz - %dMHz, "
2939 "input 1: %c, input 2: %c, "
2940 "output 1: %c, output 2: %c\n",
2941 SDVO_NAME(intel_sdvo),
2942 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2943 intel_sdvo->caps.device_rev_id,
2944 intel_sdvo->pixel_clock_min / 1000,
2945 intel_sdvo->pixel_clock_max / 1000,
2946 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2947 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2948 /* check currently supported outputs */
2949 intel_sdvo->caps.output_flags &
2950 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2951 intel_sdvo->caps.output_flags &
2952 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2953 return true;
2954
2955 err_output:
2956 intel_sdvo_output_cleanup(intel_sdvo);
2957
2958 err:
2959 drm_encoder_cleanup(&intel_encoder->base);
2960 i2c_del_adapter(&intel_sdvo->ddc);
2961 err_i2c_bus:
2962 intel_sdvo_unselect_i2c_bus(intel_sdvo);
2963 kfree(intel_sdvo);
2964
2965 return false;
2966 }
Linux kernel - Deliverables
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