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Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/delay.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "intel_sdvo_regs.h"
37
38 #undef SDVO_DEBUG
39 #define I915_SDVO "i915_sdvo"
40 struct intel_sdvo_priv {
41 struct intel_i2c_chan *i2c_bus;
42 int slaveaddr;
43
44 /* Register for the SDVO device: SDVOB or SDVOC */
45 int output_device;
46
47 /* Active outputs controlled by this SDVO output */
48 uint16_t controlled_output;
49
50 /*
51 * Capabilities of the SDVO device returned by
52 * i830_sdvo_get_capabilities()
53 */
54 struct intel_sdvo_caps caps;
55
56 /* Pixel clock limitations reported by the SDVO device, in kHz */
57 int pixel_clock_min, pixel_clock_max;
58
59 /**
60 * This is set if we're going to treat the device as TV-out.
61 *
62 * While we have these nice friendly flags for output types that ought
63 * to decide this for us, the S-Video output on our HDMI+S-Video card
64 * shows up as RGB1 (VGA).
65 */
66 bool is_tv;
67
68 /**
69 * This is set if we treat the device as HDMI, instead of DVI.
70 */
71 bool is_hdmi;
72 /**
73 * This is set if we detect output of sdvo device as LVDS.
74 */
75 bool is_lvds;
76
77 /**
78 * Returned SDTV resolutions allowed for the current format, if the
79 * device reported it.
80 */
81 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
82
83 /**
84 * Current selected TV format.
85 *
86 * This is stored in the same structure that's passed to the device, for
87 * convenience.
88 */
89 struct intel_sdvo_tv_format tv_format;
90
91 /*
92 * supported encoding mode, used to determine whether HDMI is
93 * supported
94 */
95 struct intel_sdvo_encode encode;
96
97 /* DDC bus used by this SDVO output */
98 uint8_t ddc_bus;
99
100 int save_sdvo_mult;
101 u16 save_active_outputs;
102 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
103 struct intel_sdvo_dtd save_output_dtd[16];
104 u32 save_SDVOX;
105 };
106
107 /**
108 * Writes the SDVOB or SDVOC with the given value, but always writes both
109 * SDVOB and SDVOC to work around apparent hardware issues (according to
110 * comments in the BIOS).
111 */
112 static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
113 {
114 struct drm_device *dev = intel_output->base.dev;
115 struct drm_i915_private *dev_priv = dev->dev_private;
116 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
117 u32 bval = val, cval = val;
118 int i;
119
120 if (sdvo_priv->output_device == SDVOB) {
121 cval = I915_READ(SDVOC);
122 } else {
123 bval = I915_READ(SDVOB);
124 }
125 /*
126 * Write the registers twice for luck. Sometimes,
127 * writing them only once doesn't appear to 'stick'.
128 * The BIOS does this too. Yay, magic
129 */
130 for (i = 0; i < 2; i++)
131 {
132 I915_WRITE(SDVOB, bval);
133 I915_READ(SDVOB);
134 I915_WRITE(SDVOC, cval);
135 I915_READ(SDVOC);
136 }
137 }
138
139 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
140 u8 *ch)
141 {
142 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
143 u8 out_buf[2];
144 u8 buf[2];
145 int ret;
146
147 struct i2c_msg msgs[] = {
148 {
149 .addr = sdvo_priv->i2c_bus->slave_addr,
150 .flags = 0,
151 .len = 1,
152 .buf = out_buf,
153 },
154 {
155 .addr = sdvo_priv->i2c_bus->slave_addr,
156 .flags = I2C_M_RD,
157 .len = 1,
158 .buf = buf,
159 }
160 };
161
162 out_buf[0] = addr;
163 out_buf[1] = 0;
164
165 if ((ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2)) == 2)
166 {
167 *ch = buf[0];
168 return true;
169 }
170
171 DRM_DEBUG("i2c transfer returned %d\n", ret);
172 return false;
173 }
174
175 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
176 u8 ch)
177 {
178 u8 out_buf[2];
179 struct i2c_msg msgs[] = {
180 {
181 .addr = intel_output->i2c_bus->slave_addr,
182 .flags = 0,
183 .len = 2,
184 .buf = out_buf,
185 }
186 };
187
188 out_buf[0] = addr;
189 out_buf[1] = ch;
190
191 if (i2c_transfer(&intel_output->i2c_bus->adapter, msgs, 1) == 1)
192 {
193 return true;
194 }
195 return false;
196 }
197
198 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
199 /** Mapping of command numbers to names, for debug output */
200 static const struct _sdvo_cmd_name {
201 u8 cmd;
202 char *name;
203 } sdvo_cmd_names[] = {
204 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
205 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
206 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
207 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
208 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
209 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
210 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
211 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
212 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
213 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
214 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
215 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
216 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
217 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
218 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
219 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
220 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
221 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
222 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
223 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
224 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
225 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
226 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
227 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
228 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
229 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
230 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
231 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
232 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
233 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
234 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
235 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
236 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
237 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
238 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
239 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
240 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
241 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
242 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
243 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
244 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
245 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
246 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
247 /* HDMI op code */
248 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
249 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
250 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
251 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
252 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
253 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
254 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
255 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
256 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
257 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
258 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
259 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
260 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
261 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
262 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
263 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
264 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
265 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
266 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
267 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
268 };
269
270 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
271 #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
272
273 #ifdef SDVO_DEBUG
274 static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
275 void *args, int args_len)
276 {
277 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
278 int i;
279
280 DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ",
281 SDVO_NAME(sdvo_priv), cmd);
282 for (i = 0; i < args_len; i++)
283 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
284 for (; i < 8; i++)
285 DRM_LOG_KMS(" ");
286 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
287 if (cmd == sdvo_cmd_names[i].cmd) {
288 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
289 break;
290 }
291 }
292 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
293 DRM_LOG_KMS("(%02X)", cmd);
294 DRM_LOG_KMS("\n");
295 }
296 #else
297 #define intel_sdvo_debug_write(o, c, a, l)
298 #endif
299
300 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
301 void *args, int args_len)
302 {
303 int i;
304
305 intel_sdvo_debug_write(intel_output, cmd, args, args_len);
306
307 for (i = 0; i < args_len; i++) {
308 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
309 ((u8*)args)[i]);
310 }
311
312 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
313 }
314
315 #ifdef SDVO_DEBUG
316 static const char *cmd_status_names[] = {
317 "Power on",
318 "Success",
319 "Not supported",
320 "Invalid arg",
321 "Pending",
322 "Target not specified",
323 "Scaling not supported"
324 };
325
326 static void intel_sdvo_debug_response(struct intel_output *intel_output,
327 void *response, int response_len,
328 u8 status)
329 {
330 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
331 int i;
332
333 DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv));
334 for (i = 0; i < response_len; i++)
335 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
336 for (; i < 8; i++)
337 DRM_LOG_KMS(" ");
338 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
339 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
340 else
341 DRM_LOG_KMS("(??? %d)", status);
342 DRM_LOG_KMS("\n");
343 }
344 #else
345 #define intel_sdvo_debug_response(o, r, l, s)
346 #endif
347
348 static u8 intel_sdvo_read_response(struct intel_output *intel_output,
349 void *response, int response_len)
350 {
351 int i;
352 u8 status;
353 u8 retry = 50;
354
355 while (retry--) {
356 /* Read the command response */
357 for (i = 0; i < response_len; i++) {
358 intel_sdvo_read_byte(intel_output,
359 SDVO_I2C_RETURN_0 + i,
360 &((u8 *)response)[i]);
361 }
362
363 /* read the return status */
364 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
365 &status);
366
367 intel_sdvo_debug_response(intel_output, response, response_len,
368 status);
369 if (status != SDVO_CMD_STATUS_PENDING)
370 return status;
371
372 mdelay(50);
373 }
374
375 return status;
376 }
377
378 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
379 {
380 if (mode->clock >= 100000)
381 return 1;
382 else if (mode->clock >= 50000)
383 return 2;
384 else
385 return 4;
386 }
387
388 /**
389 * Don't check status code from this as it switches the bus back to the
390 * SDVO chips which defeats the purpose of doing a bus switch in the first
391 * place.
392 */
393 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
394 u8 target)
395 {
396 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
397 }
398
399 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
400 {
401 struct intel_sdvo_set_target_input_args targets = {0};
402 u8 status;
403
404 if (target_0 && target_1)
405 return SDVO_CMD_STATUS_NOTSUPP;
406
407 if (target_1)
408 targets.target_1 = 1;
409
410 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
411 sizeof(targets));
412
413 status = intel_sdvo_read_response(intel_output, NULL, 0);
414
415 return (status == SDVO_CMD_STATUS_SUCCESS);
416 }
417
418 /**
419 * Return whether each input is trained.
420 *
421 * This function is making an assumption about the layout of the response,
422 * which should be checked against the docs.
423 */
424 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
425 {
426 struct intel_sdvo_get_trained_inputs_response response;
427 u8 status;
428
429 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
430 status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
431 if (status != SDVO_CMD_STATUS_SUCCESS)
432 return false;
433
434 *input_1 = response.input0_trained;
435 *input_2 = response.input1_trained;
436 return true;
437 }
438
439 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
440 u16 *outputs)
441 {
442 u8 status;
443
444 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
445 status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
446
447 return (status == SDVO_CMD_STATUS_SUCCESS);
448 }
449
450 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
451 u16 outputs)
452 {
453 u8 status;
454
455 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
456 sizeof(outputs));
457 status = intel_sdvo_read_response(intel_output, NULL, 0);
458 return (status == SDVO_CMD_STATUS_SUCCESS);
459 }
460
461 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
462 int mode)
463 {
464 u8 status, state = SDVO_ENCODER_STATE_ON;
465
466 switch (mode) {
467 case DRM_MODE_DPMS_ON:
468 state = SDVO_ENCODER_STATE_ON;
469 break;
470 case DRM_MODE_DPMS_STANDBY:
471 state = SDVO_ENCODER_STATE_STANDBY;
472 break;
473 case DRM_MODE_DPMS_SUSPEND:
474 state = SDVO_ENCODER_STATE_SUSPEND;
475 break;
476 case DRM_MODE_DPMS_OFF:
477 state = SDVO_ENCODER_STATE_OFF;
478 break;
479 }
480
481 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
482 sizeof(state));
483 status = intel_sdvo_read_response(intel_output, NULL, 0);
484
485 return (status == SDVO_CMD_STATUS_SUCCESS);
486 }
487
488 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
489 int *clock_min,
490 int *clock_max)
491 {
492 struct intel_sdvo_pixel_clock_range clocks;
493 u8 status;
494
495 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
496 NULL, 0);
497
498 status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
499
500 if (status != SDVO_CMD_STATUS_SUCCESS)
501 return false;
502
503 /* Convert the values from units of 10 kHz to kHz. */
504 *clock_min = clocks.min * 10;
505 *clock_max = clocks.max * 10;
506
507 return true;
508 }
509
510 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
511 u16 outputs)
512 {
513 u8 status;
514
515 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
516 sizeof(outputs));
517
518 status = intel_sdvo_read_response(intel_output, NULL, 0);
519 return (status == SDVO_CMD_STATUS_SUCCESS);
520 }
521
522 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
523 struct intel_sdvo_dtd *dtd)
524 {
525 u8 status;
526
527 intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
528 status = intel_sdvo_read_response(intel_output, &dtd->part1,
529 sizeof(dtd->part1));
530 if (status != SDVO_CMD_STATUS_SUCCESS)
531 return false;
532
533 intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
534 status = intel_sdvo_read_response(intel_output, &dtd->part2,
535 sizeof(dtd->part2));
536 if (status != SDVO_CMD_STATUS_SUCCESS)
537 return false;
538
539 return true;
540 }
541
542 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
543 struct intel_sdvo_dtd *dtd)
544 {
545 return intel_sdvo_get_timing(intel_output,
546 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
547 }
548
549 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
550 struct intel_sdvo_dtd *dtd)
551 {
552 return intel_sdvo_get_timing(intel_output,
553 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
554 }
555
556 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
557 struct intel_sdvo_dtd *dtd)
558 {
559 u8 status;
560
561 intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
562 status = intel_sdvo_read_response(intel_output, NULL, 0);
563 if (status != SDVO_CMD_STATUS_SUCCESS)
564 return false;
565
566 intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
567 status = intel_sdvo_read_response(intel_output, NULL, 0);
568 if (status != SDVO_CMD_STATUS_SUCCESS)
569 return false;
570
571 return true;
572 }
573
574 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
575 struct intel_sdvo_dtd *dtd)
576 {
577 return intel_sdvo_set_timing(intel_output,
578 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
579 }
580
581 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
582 struct intel_sdvo_dtd *dtd)
583 {
584 return intel_sdvo_set_timing(intel_output,
585 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
586 }
587
588 static bool
589 intel_sdvo_create_preferred_input_timing(struct intel_output *output,
590 uint16_t clock,
591 uint16_t width,
592 uint16_t height)
593 {
594 struct intel_sdvo_preferred_input_timing_args args;
595 uint8_t status;
596
597 memset(&args, 0, sizeof(args));
598 args.clock = clock;
599 args.width = width;
600 args.height = height;
601 args.interlace = 0;
602 args.scaled = 0;
603 intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
604 &args, sizeof(args));
605 status = intel_sdvo_read_response(output, NULL, 0);
606 if (status != SDVO_CMD_STATUS_SUCCESS)
607 return false;
608
609 return true;
610 }
611
612 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
613 struct intel_sdvo_dtd *dtd)
614 {
615 bool status;
616
617 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
618 NULL, 0);
619
620 status = intel_sdvo_read_response(output, &dtd->part1,
621 sizeof(dtd->part1));
622 if (status != SDVO_CMD_STATUS_SUCCESS)
623 return false;
624
625 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
626 NULL, 0);
627
628 status = intel_sdvo_read_response(output, &dtd->part2,
629 sizeof(dtd->part2));
630 if (status != SDVO_CMD_STATUS_SUCCESS)
631 return false;
632
633 return false;
634 }
635
636 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
637 {
638 u8 response, status;
639
640 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
641 status = intel_sdvo_read_response(intel_output, &response, 1);
642
643 if (status != SDVO_CMD_STATUS_SUCCESS) {
644 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
645 return SDVO_CLOCK_RATE_MULT_1X;
646 } else {
647 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
648 }
649
650 return response;
651 }
652
653 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
654 {
655 u8 status;
656
657 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
658 status = intel_sdvo_read_response(intel_output, NULL, 0);
659 if (status != SDVO_CMD_STATUS_SUCCESS)
660 return false;
661
662 return true;
663 }
664
665 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
666 struct drm_display_mode *mode)
667 {
668 uint16_t width, height;
669 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
670 uint16_t h_sync_offset, v_sync_offset;
671
672 width = mode->crtc_hdisplay;
673 height = mode->crtc_vdisplay;
674
675 /* do some mode translations */
676 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
677 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
678
679 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
680 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
681
682 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
683 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
684
685 dtd->part1.clock = mode->clock / 10;
686 dtd->part1.h_active = width & 0xff;
687 dtd->part1.h_blank = h_blank_len & 0xff;
688 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
689 ((h_blank_len >> 8) & 0xf);
690 dtd->part1.v_active = height & 0xff;
691 dtd->part1.v_blank = v_blank_len & 0xff;
692 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
693 ((v_blank_len >> 8) & 0xf);
694
695 dtd->part2.h_sync_off = h_sync_offset & 0xff;
696 dtd->part2.h_sync_width = h_sync_len & 0xff;
697 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
698 (v_sync_len & 0xf);
699 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
700 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
701 ((v_sync_len & 0x30) >> 4);
702
703 dtd->part2.dtd_flags = 0x18;
704 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
705 dtd->part2.dtd_flags |= 0x2;
706 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
707 dtd->part2.dtd_flags |= 0x4;
708
709 dtd->part2.sdvo_flags = 0;
710 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
711 dtd->part2.reserved = 0;
712 }
713
714 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
715 struct intel_sdvo_dtd *dtd)
716 {
717 mode->hdisplay = dtd->part1.h_active;
718 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
719 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
720 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
721 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
722 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
723 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
724 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
725
726 mode->vdisplay = dtd->part1.v_active;
727 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
728 mode->vsync_start = mode->vdisplay;
729 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
730 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
731 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
732 mode->vsync_end = mode->vsync_start +
733 (dtd->part2.v_sync_off_width & 0xf);
734 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
735 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
736 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
737
738 mode->clock = dtd->part1.clock * 10;
739
740 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
741 if (dtd->part2.dtd_flags & 0x2)
742 mode->flags |= DRM_MODE_FLAG_PHSYNC;
743 if (dtd->part2.dtd_flags & 0x4)
744 mode->flags |= DRM_MODE_FLAG_PVSYNC;
745 }
746
747 static bool intel_sdvo_get_supp_encode(struct intel_output *output,
748 struct intel_sdvo_encode *encode)
749 {
750 uint8_t status;
751
752 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
753 status = intel_sdvo_read_response(output, encode, sizeof(*encode));
754 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
755 memset(encode, 0, sizeof(*encode));
756 return false;
757 }
758
759 return true;
760 }
761
762 static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
763 {
764 uint8_t status;
765
766 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
767 status = intel_sdvo_read_response(output, NULL, 0);
768
769 return (status == SDVO_CMD_STATUS_SUCCESS);
770 }
771
772 static bool intel_sdvo_set_colorimetry(struct intel_output *output,
773 uint8_t mode)
774 {
775 uint8_t status;
776
777 intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
778 status = intel_sdvo_read_response(output, NULL, 0);
779
780 return (status == SDVO_CMD_STATUS_SUCCESS);
781 }
782
783 #if 0
784 static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
785 {
786 int i, j;
787 uint8_t set_buf_index[2];
788 uint8_t av_split;
789 uint8_t buf_size;
790 uint8_t buf[48];
791 uint8_t *pos;
792
793 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
794 intel_sdvo_read_response(output, &av_split, 1);
795
796 for (i = 0; i <= av_split; i++) {
797 set_buf_index[0] = i; set_buf_index[1] = 0;
798 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
799 set_buf_index, 2);
800 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
801 intel_sdvo_read_response(output, &buf_size, 1);
802
803 pos = buf;
804 for (j = 0; j <= buf_size; j += 8) {
805 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
806 NULL, 0);
807 intel_sdvo_read_response(output, pos, 8);
808 pos += 8;
809 }
810 }
811 }
812 #endif
813
814 static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
815 uint8_t *data, int8_t size, uint8_t tx_rate)
816 {
817 uint8_t set_buf_index[2];
818
819 set_buf_index[0] = index;
820 set_buf_index[1] = 0;
821
822 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
823
824 for (; size > 0; size -= 8) {
825 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
826 data += 8;
827 }
828
829 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
830 }
831
832 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
833 {
834 uint8_t csum = 0;
835 int i;
836
837 for (i = 0; i < size; i++)
838 csum += data[i];
839
840 return 0x100 - csum;
841 }
842
843 #define DIP_TYPE_AVI 0x82
844 #define DIP_VERSION_AVI 0x2
845 #define DIP_LEN_AVI 13
846
847 struct dip_infoframe {
848 uint8_t type;
849 uint8_t version;
850 uint8_t len;
851 uint8_t checksum;
852 union {
853 struct {
854 /* Packet Byte #1 */
855 uint8_t S:2;
856 uint8_t B:2;
857 uint8_t A:1;
858 uint8_t Y:2;
859 uint8_t rsvd1:1;
860 /* Packet Byte #2 */
861 uint8_t R:4;
862 uint8_t M:2;
863 uint8_t C:2;
864 /* Packet Byte #3 */
865 uint8_t SC:2;
866 uint8_t Q:2;
867 uint8_t EC:3;
868 uint8_t ITC:1;
869 /* Packet Byte #4 */
870 uint8_t VIC:7;
871 uint8_t rsvd2:1;
872 /* Packet Byte #5 */
873 uint8_t PR:4;
874 uint8_t rsvd3:4;
875 /* Packet Byte #6~13 */
876 uint16_t top_bar_end;
877 uint16_t bottom_bar_start;
878 uint16_t left_bar_end;
879 uint16_t right_bar_start;
880 } avi;
881 struct {
882 /* Packet Byte #1 */
883 uint8_t channel_count:3;
884 uint8_t rsvd1:1;
885 uint8_t coding_type:4;
886 /* Packet Byte #2 */
887 uint8_t sample_size:2; /* SS0, SS1 */
888 uint8_t sample_frequency:3;
889 uint8_t rsvd2:3;
890 /* Packet Byte #3 */
891 uint8_t coding_type_private:5;
892 uint8_t rsvd3:3;
893 /* Packet Byte #4 */
894 uint8_t channel_allocation;
895 /* Packet Byte #5 */
896 uint8_t rsvd4:3;
897 uint8_t level_shift:4;
898 uint8_t downmix_inhibit:1;
899 } audio;
900 uint8_t payload[28];
901 } __attribute__ ((packed)) u;
902 } __attribute__((packed));
903
904 static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
905 struct drm_display_mode * mode)
906 {
907 struct dip_infoframe avi_if = {
908 .type = DIP_TYPE_AVI,
909 .version = DIP_VERSION_AVI,
910 .len = DIP_LEN_AVI,
911 };
912
913 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
914 4 + avi_if.len);
915 intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
916 SDVO_HBUF_TX_VSYNC);
917 }
918
919 static void intel_sdvo_set_tv_format(struct intel_output *output)
920 {
921 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
922 struct intel_sdvo_tv_format *format, unset;
923 u8 status;
924
925 format = &sdvo_priv->tv_format;
926 memset(&unset, 0, sizeof(unset));
927 if (memcmp(format, &unset, sizeof(*format))) {
928 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
929 SDVO_NAME(sdvo_priv));
930 format->ntsc_m = 1;
931 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format,
932 sizeof(*format));
933 status = intel_sdvo_read_response(output, NULL, 0);
934 if (status != SDVO_CMD_STATUS_SUCCESS)
935 DRM_DEBUG("%s: Failed to set TV format\n",
936 SDVO_NAME(sdvo_priv));
937 }
938 }
939
940 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
941 struct drm_display_mode *mode,
942 struct drm_display_mode *adjusted_mode)
943 {
944 struct intel_output *output = enc_to_intel_output(encoder);
945 struct intel_sdvo_priv *dev_priv = output->dev_priv;
946
947 if (!dev_priv->is_tv) {
948 /* Make the CRTC code factor in the SDVO pixel multiplier. The
949 * SDVO device will be told of the multiplier during mode_set.
950 */
951 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
952 } else {
953 struct intel_sdvo_dtd output_dtd;
954 bool success;
955
956 /* We need to construct preferred input timings based on our
957 * output timings. To do that, we have to set the output
958 * timings, even though this isn't really the right place in
959 * the sequence to do it. Oh well.
960 */
961
962
963 /* Set output timings */
964 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
965 intel_sdvo_set_target_output(output,
966 dev_priv->controlled_output);
967 intel_sdvo_set_output_timing(output, &output_dtd);
968
969 /* Set the input timing to the screen. Assume always input 0. */
970 intel_sdvo_set_target_input(output, true, false);
971
972
973 success = intel_sdvo_create_preferred_input_timing(output,
974 mode->clock / 10,
975 mode->hdisplay,
976 mode->vdisplay);
977 if (success) {
978 struct intel_sdvo_dtd input_dtd;
979
980 intel_sdvo_get_preferred_input_timing(output,
981 &input_dtd);
982 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
983
984 drm_mode_set_crtcinfo(adjusted_mode, 0);
985
986 mode->clock = adjusted_mode->clock;
987
988 adjusted_mode->clock *=
989 intel_sdvo_get_pixel_multiplier(mode);
990 } else {
991 return false;
992 }
993 }
994 return true;
995 }
996
997 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
998 struct drm_display_mode *mode,
999 struct drm_display_mode *adjusted_mode)
1000 {
1001 struct drm_device *dev = encoder->dev;
1002 struct drm_i915_private *dev_priv = dev->dev_private;
1003 struct drm_crtc *crtc = encoder->crtc;
1004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1005 struct intel_output *output = enc_to_intel_output(encoder);
1006 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1007 u32 sdvox = 0;
1008 int sdvo_pixel_multiply;
1009 struct intel_sdvo_in_out_map in_out;
1010 struct intel_sdvo_dtd input_dtd;
1011 u8 status;
1012
1013 if (!mode)
1014 return;
1015
1016 /* First, set the input mapping for the first input to our controlled
1017 * output. This is only correct if we're a single-input device, in
1018 * which case the first input is the output from the appropriate SDVO
1019 * channel on the motherboard. In a two-input device, the first input
1020 * will be SDVOB and the second SDVOC.
1021 */
1022 in_out.in0 = sdvo_priv->controlled_output;
1023 in_out.in1 = 0;
1024
1025 intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1026 &in_out, sizeof(in_out));
1027 status = intel_sdvo_read_response(output, NULL, 0);
1028
1029 if (sdvo_priv->is_hdmi) {
1030 intel_sdvo_set_avi_infoframe(output, mode);
1031 sdvox |= SDVO_AUDIO_ENABLE;
1032 }
1033
1034 /* We have tried to get input timing in mode_fixup, and filled into
1035 adjusted_mode */
1036 if (sdvo_priv->is_tv)
1037 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1038 else
1039 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1040
1041 /* If it's a TV, we already set the output timing in mode_fixup.
1042 * Otherwise, the output timing is equal to the input timing.
1043 */
1044 if (!sdvo_priv->is_tv) {
1045 /* Set the output timing to the screen */
1046 intel_sdvo_set_target_output(output,
1047 sdvo_priv->controlled_output);
1048 intel_sdvo_set_output_timing(output, &input_dtd);
1049 }
1050
1051 /* Set the input timing to the screen. Assume always input 0. */
1052 intel_sdvo_set_target_input(output, true, false);
1053
1054 if (sdvo_priv->is_tv)
1055 intel_sdvo_set_tv_format(output);
1056
1057 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1058 * provide the device with a timing it can support, if it supports that
1059 * feature. However, presumably we would need to adjust the CRTC to
1060 * output the preferred timing, and we don't support that currently.
1061 */
1062 #if 0
1063 success = intel_sdvo_create_preferred_input_timing(output, clock,
1064 width, height);
1065 if (success) {
1066 struct intel_sdvo_dtd *input_dtd;
1067
1068 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1069 intel_sdvo_set_input_timing(output, &input_dtd);
1070 }
1071 #else
1072 intel_sdvo_set_input_timing(output, &input_dtd);
1073 #endif
1074
1075 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1076 case 1:
1077 intel_sdvo_set_clock_rate_mult(output,
1078 SDVO_CLOCK_RATE_MULT_1X);
1079 break;
1080 case 2:
1081 intel_sdvo_set_clock_rate_mult(output,
1082 SDVO_CLOCK_RATE_MULT_2X);
1083 break;
1084 case 4:
1085 intel_sdvo_set_clock_rate_mult(output,
1086 SDVO_CLOCK_RATE_MULT_4X);
1087 break;
1088 }
1089
1090 /* Set the SDVO control regs. */
1091 if (IS_I965G(dev)) {
1092 sdvox |= SDVO_BORDER_ENABLE |
1093 SDVO_VSYNC_ACTIVE_HIGH |
1094 SDVO_HSYNC_ACTIVE_HIGH;
1095 } else {
1096 sdvox |= I915_READ(sdvo_priv->output_device);
1097 switch (sdvo_priv->output_device) {
1098 case SDVOB:
1099 sdvox &= SDVOB_PRESERVE_MASK;
1100 break;
1101 case SDVOC:
1102 sdvox &= SDVOC_PRESERVE_MASK;
1103 break;
1104 }
1105 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1106 }
1107 if (intel_crtc->pipe == 1)
1108 sdvox |= SDVO_PIPE_B_SELECT;
1109
1110 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1111 if (IS_I965G(dev)) {
1112 /* done in crtc_mode_set as the dpll_md reg must be written early */
1113 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1114 /* done in crtc_mode_set as it lives inside the dpll register */
1115 } else {
1116 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1117 }
1118
1119 intel_sdvo_write_sdvox(output, sdvox);
1120 }
1121
1122 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1123 {
1124 struct drm_device *dev = encoder->dev;
1125 struct drm_i915_private *dev_priv = dev->dev_private;
1126 struct intel_output *intel_output = enc_to_intel_output(encoder);
1127 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1128 u32 temp;
1129
1130 if (mode != DRM_MODE_DPMS_ON) {
1131 intel_sdvo_set_active_outputs(intel_output, 0);
1132 if (0)
1133 intel_sdvo_set_encoder_power_state(intel_output, mode);
1134
1135 if (mode == DRM_MODE_DPMS_OFF) {
1136 temp = I915_READ(sdvo_priv->output_device);
1137 if ((temp & SDVO_ENABLE) != 0) {
1138 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1139 }
1140 }
1141 } else {
1142 bool input1, input2;
1143 int i;
1144 u8 status;
1145
1146 temp = I915_READ(sdvo_priv->output_device);
1147 if ((temp & SDVO_ENABLE) == 0)
1148 intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1149 for (i = 0; i < 2; i++)
1150 intel_wait_for_vblank(dev);
1151
1152 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1153 &input2);
1154
1155
1156 /* Warn if the device reported failure to sync.
1157 * A lot of SDVO devices fail to notify of sync, but it's
1158 * a given it the status is a success, we succeeded.
1159 */
1160 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1161 DRM_DEBUG("First %s output reported failure to sync\n",
1162 SDVO_NAME(sdvo_priv));
1163 }
1164
1165 if (0)
1166 intel_sdvo_set_encoder_power_state(intel_output, mode);
1167 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
1168 }
1169 return;
1170 }
1171
1172 static void intel_sdvo_save(struct drm_connector *connector)
1173 {
1174 struct drm_device *dev = connector->dev;
1175 struct drm_i915_private *dev_priv = dev->dev_private;
1176 struct intel_output *intel_output = to_intel_output(connector);
1177 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1178 int o;
1179
1180 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1181 intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1182
1183 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1184 intel_sdvo_set_target_input(intel_output, true, false);
1185 intel_sdvo_get_input_timing(intel_output,
1186 &sdvo_priv->save_input_dtd_1);
1187 }
1188
1189 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1190 intel_sdvo_set_target_input(intel_output, false, true);
1191 intel_sdvo_get_input_timing(intel_output,
1192 &sdvo_priv->save_input_dtd_2);
1193 }
1194
1195 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1196 {
1197 u16 this_output = (1 << o);
1198 if (sdvo_priv->caps.output_flags & this_output)
1199 {
1200 intel_sdvo_set_target_output(intel_output, this_output);
1201 intel_sdvo_get_output_timing(intel_output,
1202 &sdvo_priv->save_output_dtd[o]);
1203 }
1204 }
1205 if (sdvo_priv->is_tv) {
1206 /* XXX: Save TV format/enhancements. */
1207 }
1208
1209 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1210 }
1211
1212 static void intel_sdvo_restore(struct drm_connector *connector)
1213 {
1214 struct drm_device *dev = connector->dev;
1215 struct intel_output *intel_output = to_intel_output(connector);
1216 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1217 int o;
1218 int i;
1219 bool input1, input2;
1220 u8 status;
1221
1222 intel_sdvo_set_active_outputs(intel_output, 0);
1223
1224 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1225 {
1226 u16 this_output = (1 << o);
1227 if (sdvo_priv->caps.output_flags & this_output) {
1228 intel_sdvo_set_target_output(intel_output, this_output);
1229 intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1230 }
1231 }
1232
1233 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1234 intel_sdvo_set_target_input(intel_output, true, false);
1235 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1236 }
1237
1238 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1239 intel_sdvo_set_target_input(intel_output, false, true);
1240 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1241 }
1242
1243 intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1244
1245 if (sdvo_priv->is_tv) {
1246 /* XXX: Restore TV format/enhancements. */
1247 }
1248
1249 intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
1250
1251 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1252 {
1253 for (i = 0; i < 2; i++)
1254 intel_wait_for_vblank(dev);
1255 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1256 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1257 DRM_DEBUG("First %s output reported failure to sync\n",
1258 SDVO_NAME(sdvo_priv));
1259 }
1260
1261 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1262 }
1263
1264 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1265 struct drm_display_mode *mode)
1266 {
1267 struct intel_output *intel_output = to_intel_output(connector);
1268 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1269
1270 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1271 return MODE_NO_DBLESCAN;
1272
1273 if (sdvo_priv->pixel_clock_min > mode->clock)
1274 return MODE_CLOCK_LOW;
1275
1276 if (sdvo_priv->pixel_clock_max < mode->clock)
1277 return MODE_CLOCK_HIGH;
1278
1279 return MODE_OK;
1280 }
1281
1282 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1283 {
1284 u8 status;
1285
1286 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1287 status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1288 if (status != SDVO_CMD_STATUS_SUCCESS)
1289 return false;
1290
1291 return true;
1292 }
1293
1294 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1295 {
1296 struct drm_connector *connector = NULL;
1297 struct intel_output *iout = NULL;
1298 struct intel_sdvo_priv *sdvo;
1299
1300 /* find the sdvo connector */
1301 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1302 iout = to_intel_output(connector);
1303
1304 if (iout->type != INTEL_OUTPUT_SDVO)
1305 continue;
1306
1307 sdvo = iout->dev_priv;
1308
1309 if (sdvo->output_device == SDVOB && sdvoB)
1310 return connector;
1311
1312 if (sdvo->output_device == SDVOC && !sdvoB)
1313 return connector;
1314
1315 }
1316
1317 return NULL;
1318 }
1319
1320 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1321 {
1322 u8 response[2];
1323 u8 status;
1324 struct intel_output *intel_output;
1325 DRM_DEBUG("\n");
1326
1327 if (!connector)
1328 return 0;
1329
1330 intel_output = to_intel_output(connector);
1331
1332 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1333 status = intel_sdvo_read_response(intel_output, &response, 2);
1334
1335 if (response[0] !=0)
1336 return 1;
1337
1338 return 0;
1339 }
1340
1341 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1342 {
1343 u8 response[2];
1344 u8 status;
1345 struct intel_output *intel_output = to_intel_output(connector);
1346
1347 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1348 intel_sdvo_read_response(intel_output, &response, 2);
1349
1350 if (on) {
1351 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1352 status = intel_sdvo_read_response(intel_output, &response, 2);
1353
1354 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1355 } else {
1356 response[0] = 0;
1357 response[1] = 0;
1358 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1359 }
1360
1361 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1362 intel_sdvo_read_response(intel_output, &response, 2);
1363 }
1364
1365 static void
1366 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1367 {
1368 struct intel_output *intel_output = to_intel_output(connector);
1369 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1370 struct edid *edid = NULL;
1371
1372 intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1373 edid = drm_get_edid(&intel_output->base,
1374 &intel_output->ddc_bus->adapter);
1375 if (edid != NULL) {
1376 sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid);
1377 kfree(edid);
1378 intel_output->base.display_info.raw_edid = NULL;
1379 }
1380 }
1381
1382 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1383 {
1384 u8 response[2];
1385 u8 status;
1386 struct intel_output *intel_output = to_intel_output(connector);
1387
1388 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1389 status = intel_sdvo_read_response(intel_output, &response, 2);
1390
1391 DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
1392
1393 if (status != SDVO_CMD_STATUS_SUCCESS)
1394 return connector_status_unknown;
1395
1396 if ((response[0] != 0) || (response[1] != 0)) {
1397 intel_sdvo_hdmi_sink_detect(connector);
1398 return connector_status_connected;
1399 } else
1400 return connector_status_disconnected;
1401 }
1402
1403 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1404 {
1405 struct intel_output *intel_output = to_intel_output(connector);
1406
1407 /* set the bus switch and get the modes */
1408 intel_ddc_get_modes(intel_output);
1409
1410 #if 0
1411 struct drm_device *dev = encoder->dev;
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 /* Mac mini hack. On this device, I get DDC through the analog, which
1414 * load-detects as disconnected. I fail to DDC through the SDVO DDC,
1415 * but it does load-detect as connected. So, just steal the DDC bits
1416 * from analog when we fail at finding it the right way.
1417 */
1418 crt = xf86_config->output[0];
1419 intel_output = crt->driver_private;
1420 if (intel_output->type == I830_OUTPUT_ANALOG &&
1421 crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
1422 I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
1423 edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
1424 xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
1425 }
1426 if (edid_mon) {
1427 xf86OutputSetEDID(output, edid_mon);
1428 modes = xf86OutputGetEDIDModes(output);
1429 }
1430 #endif
1431 }
1432
1433 /**
1434 * This function checks the current TV format, and chooses a default if
1435 * it hasn't been set.
1436 */
1437 static void
1438 intel_sdvo_check_tv_format(struct intel_output *output)
1439 {
1440 struct intel_sdvo_priv *dev_priv = output->dev_priv;
1441 struct intel_sdvo_tv_format format;
1442 uint8_t status;
1443
1444 intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
1445 status = intel_sdvo_read_response(output, &format, sizeof(format));
1446 if (status != SDVO_CMD_STATUS_SUCCESS)
1447 return;
1448
1449 memcpy(&dev_priv->tv_format, &format, sizeof(format));
1450 }
1451
1452 /*
1453 * Set of SDVO TV modes.
1454 * Note! This is in reply order (see loop in get_tv_modes).
1455 * XXX: all 60Hz refresh?
1456 */
1457 struct drm_display_mode sdvo_tv_modes[] = {
1458 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1459 416, 0, 200, 201, 232, 233, 0,
1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1461 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1462 416, 0, 240, 241, 272, 273, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1464 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1465 496, 0, 300, 301, 332, 333, 0,
1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1467 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1468 736, 0, 350, 351, 382, 383, 0,
1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1470 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1471 736, 0, 400, 401, 432, 433, 0,
1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1473 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1474 736, 0, 480, 481, 512, 513, 0,
1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1476 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1477 800, 0, 480, 481, 512, 513, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1479 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1480 800, 0, 576, 577, 608, 609, 0,
1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1482 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1483 816, 0, 350, 351, 382, 383, 0,
1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1485 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1486 816, 0, 400, 401, 432, 433, 0,
1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1488 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1489 816, 0, 480, 481, 512, 513, 0,
1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1491 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1492 816, 0, 540, 541, 572, 573, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1494 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1495 816, 0, 576, 577, 608, 609, 0,
1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1497 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1498 864, 0, 576, 577, 608, 609, 0,
1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1500 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1501 896, 0, 600, 601, 632, 633, 0,
1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1503 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1504 928, 0, 624, 625, 656, 657, 0,
1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1506 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1507 1016, 0, 766, 767, 798, 799, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1509 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1510 1120, 0, 768, 769, 800, 801, 0,
1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1512 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1513 1376, 0, 1024, 1025, 1056, 1057, 0,
1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1515 };
1516
1517 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1518 {
1519 struct intel_output *output = to_intel_output(connector);
1520 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1521 struct intel_sdvo_sdtv_resolution_request tv_res;
1522 uint32_t reply = 0;
1523 uint8_t status;
1524 int i = 0;
1525
1526 intel_sdvo_check_tv_format(output);
1527
1528 /* Read the list of supported input resolutions for the selected TV
1529 * format.
1530 */
1531 memset(&tv_res, 0, sizeof(tv_res));
1532 memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res));
1533 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1534 &tv_res, sizeof(tv_res));
1535 status = intel_sdvo_read_response(output, &reply, 3);
1536 if (status != SDVO_CMD_STATUS_SUCCESS)
1537 return;
1538
1539 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1540 if (reply & (1 << i)) {
1541 struct drm_display_mode *nmode;
1542 nmode = drm_mode_duplicate(connector->dev,
1543 &sdvo_tv_modes[i]);
1544 if (nmode)
1545 drm_mode_probed_add(connector, nmode);
1546 }
1547 }
1548
1549 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1550 {
1551 struct intel_output *intel_output = to_intel_output(connector);
1552 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1553 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1554
1555 /*
1556 * Attempt to get the mode list from DDC.
1557 * Assume that the preferred modes are
1558 * arranged in priority order.
1559 */
1560 /* set the bus switch and get the modes */
1561 intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1562 intel_ddc_get_modes(intel_output);
1563 if (list_empty(&connector->probed_modes) == false)
1564 return;
1565
1566 /* Fetch modes from VBT */
1567 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1568 struct drm_display_mode *newmode;
1569 newmode = drm_mode_duplicate(connector->dev,
1570 dev_priv->sdvo_lvds_vbt_mode);
1571 if (newmode != NULL) {
1572 /* Guarantee the mode is preferred */
1573 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1574 DRM_MODE_TYPE_DRIVER);
1575 drm_mode_probed_add(connector, newmode);
1576 }
1577 }
1578 }
1579
1580 static int intel_sdvo_get_modes(struct drm_connector *connector)
1581 {
1582 struct intel_output *output = to_intel_output(connector);
1583 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1584
1585 if (sdvo_priv->is_tv)
1586 intel_sdvo_get_tv_modes(connector);
1587 else if (sdvo_priv->is_lvds == true)
1588 intel_sdvo_get_lvds_modes(connector);
1589 else
1590 intel_sdvo_get_ddc_modes(connector);
1591
1592 if (list_empty(&connector->probed_modes))
1593 return 0;
1594 return 1;
1595 }
1596
1597 static void intel_sdvo_destroy(struct drm_connector *connector)
1598 {
1599 struct intel_output *intel_output = to_intel_output(connector);
1600
1601 if (intel_output->i2c_bus)
1602 intel_i2c_destroy(intel_output->i2c_bus);
1603 if (intel_output->ddc_bus)
1604 intel_i2c_destroy(intel_output->ddc_bus);
1605
1606 drm_sysfs_connector_remove(connector);
1607 drm_connector_cleanup(connector);
1608 kfree(intel_output);
1609 }
1610
1611 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1612 .dpms = intel_sdvo_dpms,
1613 .mode_fixup = intel_sdvo_mode_fixup,
1614 .prepare = intel_encoder_prepare,
1615 .mode_set = intel_sdvo_mode_set,
1616 .commit = intel_encoder_commit,
1617 };
1618
1619 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1620 .dpms = drm_helper_connector_dpms,
1621 .save = intel_sdvo_save,
1622 .restore = intel_sdvo_restore,
1623 .detect = intel_sdvo_detect,
1624 .fill_modes = drm_helper_probe_single_connector_modes,
1625 .destroy = intel_sdvo_destroy,
1626 };
1627
1628 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1629 .get_modes = intel_sdvo_get_modes,
1630 .mode_valid = intel_sdvo_mode_valid,
1631 .best_encoder = intel_best_encoder,
1632 };
1633
1634 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1635 {
1636 drm_encoder_cleanup(encoder);
1637 }
1638
1639 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1640 .destroy = intel_sdvo_enc_destroy,
1641 };
1642
1643
1644 /**
1645 * Choose the appropriate DDC bus for control bus switch command for this
1646 * SDVO output based on the controlled output.
1647 *
1648 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1649 * outputs, then LVDS outputs.
1650 */
1651 static void
1652 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
1653 {
1654 uint16_t mask = 0;
1655 unsigned int num_bits;
1656
1657 /* Make a mask of outputs less than or equal to our own priority in the
1658 * list.
1659 */
1660 switch (dev_priv->controlled_output) {
1661 case SDVO_OUTPUT_LVDS1:
1662 mask |= SDVO_OUTPUT_LVDS1;
1663 case SDVO_OUTPUT_LVDS0:
1664 mask |= SDVO_OUTPUT_LVDS0;
1665 case SDVO_OUTPUT_TMDS1:
1666 mask |= SDVO_OUTPUT_TMDS1;
1667 case SDVO_OUTPUT_TMDS0:
1668 mask |= SDVO_OUTPUT_TMDS0;
1669 case SDVO_OUTPUT_RGB1:
1670 mask |= SDVO_OUTPUT_RGB1;
1671 case SDVO_OUTPUT_RGB0:
1672 mask |= SDVO_OUTPUT_RGB0;
1673 break;
1674 }
1675
1676 /* Count bits to find what number we are in the priority list. */
1677 mask &= dev_priv->caps.output_flags;
1678 num_bits = hweight16(mask);
1679 if (num_bits > 3) {
1680 /* if more than 3 outputs, default to DDC bus 3 for now */
1681 num_bits = 3;
1682 }
1683
1684 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1685 dev_priv->ddc_bus = 1 << num_bits;
1686 }
1687
1688 static bool
1689 intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
1690 {
1691 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1692 uint8_t status;
1693
1694 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1695
1696 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
1697 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
1698 if (status != SDVO_CMD_STATUS_SUCCESS)
1699 return false;
1700 return true;
1701 }
1702
1703 static struct intel_output *
1704 intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
1705 {
1706 struct drm_device *dev = chan->drm_dev;
1707 struct drm_connector *connector;
1708 struct intel_output *intel_output = NULL;
1709
1710 list_for_each_entry(connector,
1711 &dev->mode_config.connector_list, head) {
1712 if (to_intel_output(connector)->ddc_bus == chan) {
1713 intel_output = to_intel_output(connector);
1714 break;
1715 }
1716 }
1717 return intel_output;
1718 }
1719
1720 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
1721 struct i2c_msg msgs[], int num)
1722 {
1723 struct intel_output *intel_output;
1724 struct intel_sdvo_priv *sdvo_priv;
1725 struct i2c_algo_bit_data *algo_data;
1726 struct i2c_algorithm *algo;
1727
1728 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
1729 intel_output =
1730 intel_sdvo_chan_to_intel_output(
1731 (struct intel_i2c_chan *)(algo_data->data));
1732 if (intel_output == NULL)
1733 return -EINVAL;
1734
1735 sdvo_priv = intel_output->dev_priv;
1736 algo = (struct i2c_algorithm *)intel_output->i2c_bus->adapter.algo;
1737
1738 intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1739 return algo->master_xfer(i2c_adap, msgs, num);
1740 }
1741
1742 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
1743 .master_xfer = intel_sdvo_master_xfer,
1744 };
1745
1746 static u8
1747 intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
1748 {
1749 struct drm_i915_private *dev_priv = dev->dev_private;
1750 struct sdvo_device_mapping *my_mapping, *other_mapping;
1751
1752 if (output_device == SDVOB) {
1753 my_mapping = &dev_priv->sdvo_mappings[0];
1754 other_mapping = &dev_priv->sdvo_mappings[1];
1755 } else {
1756 my_mapping = &dev_priv->sdvo_mappings[1];
1757 other_mapping = &dev_priv->sdvo_mappings[0];
1758 }
1759
1760 /* If the BIOS described our SDVO device, take advantage of it. */
1761 if (my_mapping->slave_addr)
1762 return my_mapping->slave_addr;
1763
1764 /* If the BIOS only described a different SDVO device, use the
1765 * address that it isn't using.
1766 */
1767 if (other_mapping->slave_addr) {
1768 if (other_mapping->slave_addr == 0x70)
1769 return 0x72;
1770 else
1771 return 0x70;
1772 }
1773
1774 /* No SDVO device info is found for another DVO port,
1775 * so use mapping assumption we had before BIOS parsing.
1776 */
1777 if (output_device == SDVOB)
1778 return 0x70;
1779 else
1780 return 0x72;
1781 }
1782
1783 bool intel_sdvo_init(struct drm_device *dev, int output_device)
1784 {
1785 struct drm_connector *connector;
1786 struct intel_output *intel_output;
1787 struct intel_sdvo_priv *sdvo_priv;
1788 struct intel_i2c_chan *i2cbus = NULL;
1789 struct intel_i2c_chan *ddcbus = NULL;
1790 int connector_type;
1791 u8 ch[0x40];
1792 int i;
1793 int encoder_type, output_id;
1794 u8 slave_addr;
1795
1796 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
1797 if (!intel_output) {
1798 return false;
1799 }
1800
1801 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
1802 intel_output->type = INTEL_OUTPUT_SDVO;
1803
1804 /* setup the DDC bus. */
1805 if (output_device == SDVOB)
1806 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
1807 else
1808 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
1809
1810 if (!i2cbus)
1811 goto err_inteloutput;
1812
1813 slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
1814 sdvo_priv->i2c_bus = i2cbus;
1815
1816 if (output_device == SDVOB) {
1817 output_id = 1;
1818 } else {
1819 output_id = 2;
1820 }
1821 sdvo_priv->i2c_bus->slave_addr = slave_addr >> 1;
1822 sdvo_priv->output_device = output_device;
1823 intel_output->i2c_bus = i2cbus;
1824 intel_output->dev_priv = sdvo_priv;
1825
1826 /* Read the regs to test if we can talk to the device */
1827 for (i = 0; i < 0x40; i++) {
1828 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
1829 DRM_DEBUG_KMS(I915_SDVO,
1830 "No SDVO device found on SDVO%c\n",
1831 output_device == SDVOB ? 'B' : 'C');
1832 goto err_i2c;
1833 }
1834 }
1835
1836 /* setup the DDC bus. */
1837 if (output_device == SDVOB)
1838 ddcbus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
1839 else
1840 ddcbus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
1841
1842 if (ddcbus == NULL)
1843 goto err_i2c;
1844
1845 intel_sdvo_i2c_bit_algo.functionality =
1846 intel_output->i2c_bus->adapter.algo->functionality;
1847 ddcbus->adapter.algo = &intel_sdvo_i2c_bit_algo;
1848 intel_output->ddc_bus = ddcbus;
1849
1850 /* In defaut case sdvo lvds is false */
1851 sdvo_priv->is_lvds = false;
1852 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
1853
1854 if (sdvo_priv->caps.output_flags &
1855 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1856 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1857 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
1858 else
1859 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
1860
1861 encoder_type = DRM_MODE_ENCODER_TMDS;
1862 connector_type = DRM_MODE_CONNECTOR_DVID;
1863
1864 if (intel_sdvo_get_supp_encode(intel_output,
1865 &sdvo_priv->encode) &&
1866 intel_sdvo_get_digital_encoding_mode(intel_output) &&
1867 sdvo_priv->is_hdmi) {
1868 /* enable hdmi encoding mode if supported */
1869 intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
1870 intel_sdvo_set_colorimetry(intel_output,
1871 SDVO_COLORIMETRY_RGB256);
1872 connector_type = DRM_MODE_CONNECTOR_HDMIA;
1873 }
1874 }
1875 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_SVID0)
1876 {
1877 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
1878 encoder_type = DRM_MODE_ENCODER_TVDAC;
1879 connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1880 sdvo_priv->is_tv = true;
1881 intel_output->needs_tv_clock = true;
1882 }
1883 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
1884 {
1885 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
1886 encoder_type = DRM_MODE_ENCODER_DAC;
1887 connector_type = DRM_MODE_CONNECTOR_VGA;
1888 }
1889 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
1890 {
1891 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
1892 encoder_type = DRM_MODE_ENCODER_DAC;
1893 connector_type = DRM_MODE_CONNECTOR_VGA;
1894 }
1895 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS0)
1896 {
1897 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
1898 encoder_type = DRM_MODE_ENCODER_LVDS;
1899 connector_type = DRM_MODE_CONNECTOR_LVDS;
1900 sdvo_priv->is_lvds = true;
1901 }
1902 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS1)
1903 {
1904 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
1905 encoder_type = DRM_MODE_ENCODER_LVDS;
1906 connector_type = DRM_MODE_CONNECTOR_LVDS;
1907 sdvo_priv->is_lvds = true;
1908 }
1909 else
1910 {
1911 unsigned char bytes[2];
1912
1913 sdvo_priv->controlled_output = 0;
1914 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
1915 DRM_DEBUG_KMS(I915_SDVO,
1916 "%s: Unknown SDVO output type (0x%02x%02x)\n",
1917 SDVO_NAME(sdvo_priv),
1918 bytes[0], bytes[1]);
1919 encoder_type = DRM_MODE_ENCODER_NONE;
1920 connector_type = DRM_MODE_CONNECTOR_Unknown;
1921 goto err_i2c;
1922 }
1923
1924 connector = &intel_output->base;
1925 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
1926 connector_type);
1927 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
1928 connector->interlace_allowed = 0;
1929 connector->doublescan_allowed = 0;
1930 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1931
1932 drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type);
1933 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
1934
1935 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
1936 drm_sysfs_connector_add(connector);
1937
1938 intel_sdvo_select_ddc_bus(sdvo_priv);
1939
1940 /* Set the input timing to the screen. Assume always input 0. */
1941 intel_sdvo_set_target_input(intel_output, true, false);
1942
1943 intel_sdvo_get_input_pixel_clock_range(intel_output,
1944 &sdvo_priv->pixel_clock_min,
1945 &sdvo_priv->pixel_clock_max);
1946
1947
1948 DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, "
1949 "clock range %dMHz - %dMHz, "
1950 "input 1: %c, input 2: %c, "
1951 "output 1: %c, output 2: %c\n",
1952 SDVO_NAME(sdvo_priv),
1953 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
1954 sdvo_priv->caps.device_rev_id,
1955 sdvo_priv->pixel_clock_min / 1000,
1956 sdvo_priv->pixel_clock_max / 1000,
1957 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
1958 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
1959 /* check currently supported outputs */
1960 sdvo_priv->caps.output_flags &
1961 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
1962 sdvo_priv->caps.output_flags &
1963 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
1964
1965 return true;
1966
1967 err_i2c:
1968 if (ddcbus != NULL)
1969 intel_i2c_destroy(intel_output->ddc_bus);
1970 intel_i2c_destroy(intel_output->i2c_bus);
1971 err_inteloutput:
1972 kfree(intel_output);
1973
1974 return false;
1975 }
Linux kernel - Deliverables
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