2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
28 #include <linux/i2c.h>
29 #include <linux/delay.h>
33 #include "intel_drv.h"
36 #include "intel_sdvo_regs.h"
39 #define I915_SDVO "i915_sdvo"
40 struct intel_sdvo_priv
{
43 /* Register for the SDVO device: SDVOB or SDVOC */
46 /* Active outputs controlled by this SDVO output */
47 uint16_t controlled_output
;
50 * Capabilities of the SDVO device returned by
51 * i830_sdvo_get_capabilities()
53 struct intel_sdvo_caps caps
;
55 /* Pixel clock limitations reported by the SDVO device, in kHz */
56 int pixel_clock_min
, pixel_clock_max
;
59 * This is set if we're going to treat the device as TV-out.
61 * While we have these nice friendly flags for output types that ought
62 * to decide this for us, the S-Video output on our HDMI+S-Video card
63 * shows up as RGB1 (VGA).
68 * This is set if we treat the device as HDMI, instead of DVI.
72 * This is set if we detect output of sdvo device as LVDS.
77 * Returned SDTV resolutions allowed for the current format, if the
80 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions
;
83 * Current selected TV format.
85 * This is stored in the same structure that's passed to the device, for
88 struct intel_sdvo_tv_format tv_format
;
91 * supported encoding mode, used to determine whether HDMI is
94 struct intel_sdvo_encode encode
;
96 /* DDC bus used by this SDVO output */
100 u16 save_active_outputs
;
101 struct intel_sdvo_dtd save_input_dtd_1
, save_input_dtd_2
;
102 struct intel_sdvo_dtd save_output_dtd
[16];
107 * Writes the SDVOB or SDVOC with the given value, but always writes both
108 * SDVOB and SDVOC to work around apparent hardware issues (according to
109 * comments in the BIOS).
111 static void intel_sdvo_write_sdvox(struct intel_output
*intel_output
, u32 val
)
113 struct drm_device
*dev
= intel_output
->base
.dev
;
114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
115 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
116 u32 bval
= val
, cval
= val
;
119 if (sdvo_priv
->output_device
== SDVOB
) {
120 cval
= I915_READ(SDVOC
);
122 bval
= I915_READ(SDVOB
);
125 * Write the registers twice for luck. Sometimes,
126 * writing them only once doesn't appear to 'stick'.
127 * The BIOS does this too. Yay, magic
129 for (i
= 0; i
< 2; i
++)
131 I915_WRITE(SDVOB
, bval
);
133 I915_WRITE(SDVOC
, cval
);
138 static bool intel_sdvo_read_byte(struct intel_output
*intel_output
, u8 addr
,
141 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
146 struct i2c_msg msgs
[] = {
148 .addr
= sdvo_priv
->slave_addr
>> 1,
154 .addr
= sdvo_priv
->slave_addr
>> 1,
164 if ((ret
= i2c_transfer(intel_output
->i2c_bus
, msgs
, 2)) == 2)
170 DRM_DEBUG("i2c transfer returned %d\n", ret
);
174 static bool intel_sdvo_write_byte(struct intel_output
*intel_output
, int addr
,
177 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
179 struct i2c_msg msgs
[] = {
181 .addr
= sdvo_priv
->slave_addr
>> 1,
191 if (i2c_transfer(intel_output
->i2c_bus
, msgs
, 1) == 1)
198 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
199 /** Mapping of command numbers to names, for debug output */
200 static const struct _sdvo_cmd_name
{
203 } sdvo_cmd_names
[] = {
204 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET
),
205 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS
),
206 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV
),
207 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS
),
208 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS
),
209 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS
),
210 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP
),
211 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP
),
212 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS
),
213 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT
),
214 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG
),
215 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG
),
216 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE
),
217 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT
),
218 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT
),
219 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1
),
220 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2
),
221 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1
),
222 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2
),
223 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1
),
224 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1
),
225 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2
),
226 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1
),
227 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2
),
228 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING
),
229 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1
),
230 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2
),
231 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE
),
232 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE
),
233 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS
),
234 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT
),
235 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT
),
236 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS
),
237 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT
),
238 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT
),
239 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES
),
240 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE
),
241 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE
),
242 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE
),
243 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH
),
244 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT
),
245 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT
),
246 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS
),
248 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE
),
249 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE
),
250 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE
),
251 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI
),
252 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI
),
253 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP
),
254 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY
),
255 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY
),
256 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER
),
257 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT
),
258 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT
),
259 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX
),
260 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX
),
261 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO
),
262 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT
),
263 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT
),
264 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE
),
265 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE
),
266 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA
),
267 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA
),
270 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
271 #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
274 static void intel_sdvo_debug_write(struct intel_output
*intel_output
, u8 cmd
,
275 void *args
, int args_len
)
277 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
280 DRM_DEBUG_KMS(I915_SDVO
, "%s: W: %02X ",
281 SDVO_NAME(sdvo_priv
), cmd
);
282 for (i
= 0; i
< args_len
; i
++)
283 DRM_LOG_KMS("%02X ", ((u8
*)args
)[i
]);
286 for (i
= 0; i
< sizeof(sdvo_cmd_names
) / sizeof(sdvo_cmd_names
[0]); i
++) {
287 if (cmd
== sdvo_cmd_names
[i
].cmd
) {
288 DRM_LOG_KMS("(%s)", sdvo_cmd_names
[i
].name
);
292 if (i
== sizeof(sdvo_cmd_names
)/ sizeof(sdvo_cmd_names
[0]))
293 DRM_LOG_KMS("(%02X)", cmd
);
297 #define intel_sdvo_debug_write(o, c, a, l)
300 static void intel_sdvo_write_cmd(struct intel_output
*intel_output
, u8 cmd
,
301 void *args
, int args_len
)
305 intel_sdvo_debug_write(intel_output
, cmd
, args
, args_len
);
307 for (i
= 0; i
< args_len
; i
++) {
308 intel_sdvo_write_byte(intel_output
, SDVO_I2C_ARG_0
- i
,
312 intel_sdvo_write_byte(intel_output
, SDVO_I2C_OPCODE
, cmd
);
316 static const char *cmd_status_names
[] = {
322 "Target not specified",
323 "Scaling not supported"
326 static void intel_sdvo_debug_response(struct intel_output
*intel_output
,
327 void *response
, int response_len
,
330 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
333 DRM_DEBUG_KMS(I915_SDVO
, "%s: R: ", SDVO_NAME(sdvo_priv
));
334 for (i
= 0; i
< response_len
; i
++)
335 DRM_LOG_KMS("%02X ", ((u8
*)response
)[i
]);
338 if (status
<= SDVO_CMD_STATUS_SCALING_NOT_SUPP
)
339 DRM_LOG_KMS("(%s)", cmd_status_names
[status
]);
341 DRM_LOG_KMS("(??? %d)", status
);
345 #define intel_sdvo_debug_response(o, r, l, s)
348 static u8
intel_sdvo_read_response(struct intel_output
*intel_output
,
349 void *response
, int response_len
)
356 /* Read the command response */
357 for (i
= 0; i
< response_len
; i
++) {
358 intel_sdvo_read_byte(intel_output
,
359 SDVO_I2C_RETURN_0
+ i
,
360 &((u8
*)response
)[i
]);
363 /* read the return status */
364 intel_sdvo_read_byte(intel_output
, SDVO_I2C_CMD_STATUS
,
367 intel_sdvo_debug_response(intel_output
, response
, response_len
,
369 if (status
!= SDVO_CMD_STATUS_PENDING
)
378 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode
*mode
)
380 if (mode
->clock
>= 100000)
382 else if (mode
->clock
>= 50000)
389 * Don't check status code from this as it switches the bus back to the
390 * SDVO chips which defeats the purpose of doing a bus switch in the first
393 static void intel_sdvo_set_control_bus_switch(struct intel_output
*intel_output
,
396 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_CONTROL_BUS_SWITCH
, &target
, 1);
399 static bool intel_sdvo_set_target_input(struct intel_output
*intel_output
, bool target_0
, bool target_1
)
401 struct intel_sdvo_set_target_input_args targets
= {0};
404 if (target_0
&& target_1
)
405 return SDVO_CMD_STATUS_NOTSUPP
;
408 targets
.target_1
= 1;
410 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_TARGET_INPUT
, &targets
,
413 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
415 return (status
== SDVO_CMD_STATUS_SUCCESS
);
419 * Return whether each input is trained.
421 * This function is making an assumption about the layout of the response,
422 * which should be checked against the docs.
424 static bool intel_sdvo_get_trained_inputs(struct intel_output
*intel_output
, bool *input_1
, bool *input_2
)
426 struct intel_sdvo_get_trained_inputs_response response
;
429 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_TRAINED_INPUTS
, NULL
, 0);
430 status
= intel_sdvo_read_response(intel_output
, &response
, sizeof(response
));
431 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
434 *input_1
= response
.input0_trained
;
435 *input_2
= response
.input1_trained
;
439 static bool intel_sdvo_get_active_outputs(struct intel_output
*intel_output
,
444 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_ACTIVE_OUTPUTS
, NULL
, 0);
445 status
= intel_sdvo_read_response(intel_output
, outputs
, sizeof(*outputs
));
447 return (status
== SDVO_CMD_STATUS_SUCCESS
);
450 static bool intel_sdvo_set_active_outputs(struct intel_output
*intel_output
,
455 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_ACTIVE_OUTPUTS
, &outputs
,
457 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
458 return (status
== SDVO_CMD_STATUS_SUCCESS
);
461 static bool intel_sdvo_set_encoder_power_state(struct intel_output
*intel_output
,
464 u8 status
, state
= SDVO_ENCODER_STATE_ON
;
467 case DRM_MODE_DPMS_ON
:
468 state
= SDVO_ENCODER_STATE_ON
;
470 case DRM_MODE_DPMS_STANDBY
:
471 state
= SDVO_ENCODER_STATE_STANDBY
;
473 case DRM_MODE_DPMS_SUSPEND
:
474 state
= SDVO_ENCODER_STATE_SUSPEND
;
476 case DRM_MODE_DPMS_OFF
:
477 state
= SDVO_ENCODER_STATE_OFF
;
481 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_ENCODER_POWER_STATE
, &state
,
483 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
485 return (status
== SDVO_CMD_STATUS_SUCCESS
);
488 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output
*intel_output
,
492 struct intel_sdvo_pixel_clock_range clocks
;
495 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE
,
498 status
= intel_sdvo_read_response(intel_output
, &clocks
, sizeof(clocks
));
500 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
503 /* Convert the values from units of 10 kHz to kHz. */
504 *clock_min
= clocks
.min
* 10;
505 *clock_max
= clocks
.max
* 10;
510 static bool intel_sdvo_set_target_output(struct intel_output
*intel_output
,
515 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_TARGET_OUTPUT
, &outputs
,
518 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
519 return (status
== SDVO_CMD_STATUS_SUCCESS
);
522 static bool intel_sdvo_get_timing(struct intel_output
*intel_output
, u8 cmd
,
523 struct intel_sdvo_dtd
*dtd
)
527 intel_sdvo_write_cmd(intel_output
, cmd
, NULL
, 0);
528 status
= intel_sdvo_read_response(intel_output
, &dtd
->part1
,
530 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
533 intel_sdvo_write_cmd(intel_output
, cmd
+ 1, NULL
, 0);
534 status
= intel_sdvo_read_response(intel_output
, &dtd
->part2
,
536 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
542 static bool intel_sdvo_get_input_timing(struct intel_output
*intel_output
,
543 struct intel_sdvo_dtd
*dtd
)
545 return intel_sdvo_get_timing(intel_output
,
546 SDVO_CMD_GET_INPUT_TIMINGS_PART1
, dtd
);
549 static bool intel_sdvo_get_output_timing(struct intel_output
*intel_output
,
550 struct intel_sdvo_dtd
*dtd
)
552 return intel_sdvo_get_timing(intel_output
,
553 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1
, dtd
);
556 static bool intel_sdvo_set_timing(struct intel_output
*intel_output
, u8 cmd
,
557 struct intel_sdvo_dtd
*dtd
)
561 intel_sdvo_write_cmd(intel_output
, cmd
, &dtd
->part1
, sizeof(dtd
->part1
));
562 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
563 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
566 intel_sdvo_write_cmd(intel_output
, cmd
+ 1, &dtd
->part2
, sizeof(dtd
->part2
));
567 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
568 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
574 static bool intel_sdvo_set_input_timing(struct intel_output
*intel_output
,
575 struct intel_sdvo_dtd
*dtd
)
577 return intel_sdvo_set_timing(intel_output
,
578 SDVO_CMD_SET_INPUT_TIMINGS_PART1
, dtd
);
581 static bool intel_sdvo_set_output_timing(struct intel_output
*intel_output
,
582 struct intel_sdvo_dtd
*dtd
)
584 return intel_sdvo_set_timing(intel_output
,
585 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1
, dtd
);
589 intel_sdvo_create_preferred_input_timing(struct intel_output
*output
,
594 struct intel_sdvo_preferred_input_timing_args args
;
597 memset(&args
, 0, sizeof(args
));
600 args
.height
= height
;
603 intel_sdvo_write_cmd(output
, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING
,
604 &args
, sizeof(args
));
605 status
= intel_sdvo_read_response(output
, NULL
, 0);
606 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
612 static bool intel_sdvo_get_preferred_input_timing(struct intel_output
*output
,
613 struct intel_sdvo_dtd
*dtd
)
617 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1
,
620 status
= intel_sdvo_read_response(output
, &dtd
->part1
,
622 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
625 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2
,
628 status
= intel_sdvo_read_response(output
, &dtd
->part2
,
630 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
636 static int intel_sdvo_get_clock_rate_mult(struct intel_output
*intel_output
)
640 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_CLOCK_RATE_MULT
, NULL
, 0);
641 status
= intel_sdvo_read_response(intel_output
, &response
, 1);
643 if (status
!= SDVO_CMD_STATUS_SUCCESS
) {
644 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
645 return SDVO_CLOCK_RATE_MULT_1X
;
647 DRM_DEBUG("Current clock rate multiplier: %d\n", response
);
653 static bool intel_sdvo_set_clock_rate_mult(struct intel_output
*intel_output
, u8 val
)
657 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_CLOCK_RATE_MULT
, &val
, 1);
658 status
= intel_sdvo_read_response(intel_output
, NULL
, 0);
659 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
665 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd
*dtd
,
666 struct drm_display_mode
*mode
)
668 uint16_t width
, height
;
669 uint16_t h_blank_len
, h_sync_len
, v_blank_len
, v_sync_len
;
670 uint16_t h_sync_offset
, v_sync_offset
;
672 width
= mode
->crtc_hdisplay
;
673 height
= mode
->crtc_vdisplay
;
675 /* do some mode translations */
676 h_blank_len
= mode
->crtc_hblank_end
- mode
->crtc_hblank_start
;
677 h_sync_len
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
679 v_blank_len
= mode
->crtc_vblank_end
- mode
->crtc_vblank_start
;
680 v_sync_len
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
682 h_sync_offset
= mode
->crtc_hsync_start
- mode
->crtc_hblank_start
;
683 v_sync_offset
= mode
->crtc_vsync_start
- mode
->crtc_vblank_start
;
685 dtd
->part1
.clock
= mode
->clock
/ 10;
686 dtd
->part1
.h_active
= width
& 0xff;
687 dtd
->part1
.h_blank
= h_blank_len
& 0xff;
688 dtd
->part1
.h_high
= (((width
>> 8) & 0xf) << 4) |
689 ((h_blank_len
>> 8) & 0xf);
690 dtd
->part1
.v_active
= height
& 0xff;
691 dtd
->part1
.v_blank
= v_blank_len
& 0xff;
692 dtd
->part1
.v_high
= (((height
>> 8) & 0xf) << 4) |
693 ((v_blank_len
>> 8) & 0xf);
695 dtd
->part2
.h_sync_off
= h_sync_offset
& 0xff;
696 dtd
->part2
.h_sync_width
= h_sync_len
& 0xff;
697 dtd
->part2
.v_sync_off_width
= (v_sync_offset
& 0xf) << 4 |
699 dtd
->part2
.sync_off_width_high
= ((h_sync_offset
& 0x300) >> 2) |
700 ((h_sync_len
& 0x300) >> 4) | ((v_sync_offset
& 0x30) >> 2) |
701 ((v_sync_len
& 0x30) >> 4);
703 dtd
->part2
.dtd_flags
= 0x18;
704 if (mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
705 dtd
->part2
.dtd_flags
|= 0x2;
706 if (mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
707 dtd
->part2
.dtd_flags
|= 0x4;
709 dtd
->part2
.sdvo_flags
= 0;
710 dtd
->part2
.v_sync_off_high
= v_sync_offset
& 0xc0;
711 dtd
->part2
.reserved
= 0;
714 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode
* mode
,
715 struct intel_sdvo_dtd
*dtd
)
717 mode
->hdisplay
= dtd
->part1
.h_active
;
718 mode
->hdisplay
+= ((dtd
->part1
.h_high
>> 4) & 0x0f) << 8;
719 mode
->hsync_start
= mode
->hdisplay
+ dtd
->part2
.h_sync_off
;
720 mode
->hsync_start
+= (dtd
->part2
.sync_off_width_high
& 0xc0) << 2;
721 mode
->hsync_end
= mode
->hsync_start
+ dtd
->part2
.h_sync_width
;
722 mode
->hsync_end
+= (dtd
->part2
.sync_off_width_high
& 0x30) << 4;
723 mode
->htotal
= mode
->hdisplay
+ dtd
->part1
.h_blank
;
724 mode
->htotal
+= (dtd
->part1
.h_high
& 0xf) << 8;
726 mode
->vdisplay
= dtd
->part1
.v_active
;
727 mode
->vdisplay
+= ((dtd
->part1
.v_high
>> 4) & 0x0f) << 8;
728 mode
->vsync_start
= mode
->vdisplay
;
729 mode
->vsync_start
+= (dtd
->part2
.v_sync_off_width
>> 4) & 0xf;
730 mode
->vsync_start
+= (dtd
->part2
.sync_off_width_high
& 0x0c) << 2;
731 mode
->vsync_start
+= dtd
->part2
.v_sync_off_high
& 0xc0;
732 mode
->vsync_end
= mode
->vsync_start
+
733 (dtd
->part2
.v_sync_off_width
& 0xf);
734 mode
->vsync_end
+= (dtd
->part2
.sync_off_width_high
& 0x3) << 4;
735 mode
->vtotal
= mode
->vdisplay
+ dtd
->part1
.v_blank
;
736 mode
->vtotal
+= (dtd
->part1
.v_high
& 0xf) << 8;
738 mode
->clock
= dtd
->part1
.clock
* 10;
740 mode
->flags
&= ~(DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
);
741 if (dtd
->part2
.dtd_flags
& 0x2)
742 mode
->flags
|= DRM_MODE_FLAG_PHSYNC
;
743 if (dtd
->part2
.dtd_flags
& 0x4)
744 mode
->flags
|= DRM_MODE_FLAG_PVSYNC
;
747 static bool intel_sdvo_get_supp_encode(struct intel_output
*output
,
748 struct intel_sdvo_encode
*encode
)
752 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_SUPP_ENCODE
, NULL
, 0);
753 status
= intel_sdvo_read_response(output
, encode
, sizeof(*encode
));
754 if (status
!= SDVO_CMD_STATUS_SUCCESS
) { /* non-support means DVI */
755 memset(encode
, 0, sizeof(*encode
));
762 static bool intel_sdvo_set_encode(struct intel_output
*output
, uint8_t mode
)
766 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_ENCODE
, &mode
, 1);
767 status
= intel_sdvo_read_response(output
, NULL
, 0);
769 return (status
== SDVO_CMD_STATUS_SUCCESS
);
772 static bool intel_sdvo_set_colorimetry(struct intel_output
*output
,
777 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_COLORIMETRY
, &mode
, 1);
778 status
= intel_sdvo_read_response(output
, NULL
, 0);
780 return (status
== SDVO_CMD_STATUS_SUCCESS
);
784 static void intel_sdvo_dump_hdmi_buf(struct intel_output
*output
)
787 uint8_t set_buf_index
[2];
793 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_HBUF_AV_SPLIT
, NULL
, 0);
794 intel_sdvo_read_response(output
, &av_split
, 1);
796 for (i
= 0; i
<= av_split
; i
++) {
797 set_buf_index
[0] = i
; set_buf_index
[1] = 0;
798 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_HBUF_INDEX
,
800 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_HBUF_INFO
, NULL
, 0);
801 intel_sdvo_read_response(output
, &buf_size
, 1);
804 for (j
= 0; j
<= buf_size
; j
+= 8) {
805 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_HBUF_DATA
,
807 intel_sdvo_read_response(output
, pos
, 8);
814 static void intel_sdvo_set_hdmi_buf(struct intel_output
*output
, int index
,
815 uint8_t *data
, int8_t size
, uint8_t tx_rate
)
817 uint8_t set_buf_index
[2];
819 set_buf_index
[0] = index
;
820 set_buf_index
[1] = 0;
822 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_HBUF_INDEX
, set_buf_index
, 2);
824 for (; size
> 0; size
-= 8) {
825 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_HBUF_DATA
, data
, 8);
829 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_HBUF_TXRATE
, &tx_rate
, 1);
832 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data
, uint8_t size
)
837 for (i
= 0; i
< size
; i
++)
843 #define DIP_TYPE_AVI 0x82
844 #define DIP_VERSION_AVI 0x2
845 #define DIP_LEN_AVI 13
847 struct dip_infoframe
{
875 /* Packet Byte #6~13 */
876 uint16_t top_bar_end
;
877 uint16_t bottom_bar_start
;
878 uint16_t left_bar_end
;
879 uint16_t right_bar_start
;
883 uint8_t channel_count
:3;
885 uint8_t coding_type
:4;
887 uint8_t sample_size
:2; /* SS0, SS1 */
888 uint8_t sample_frequency
:3;
891 uint8_t coding_type_private
:5;
894 uint8_t channel_allocation
;
897 uint8_t level_shift
:4;
898 uint8_t downmix_inhibit
:1;
901 } __attribute__ ((packed
)) u
;
902 } __attribute__((packed
));
904 static void intel_sdvo_set_avi_infoframe(struct intel_output
*output
,
905 struct drm_display_mode
* mode
)
907 struct dip_infoframe avi_if
= {
908 .type
= DIP_TYPE_AVI
,
909 .version
= DIP_VERSION_AVI
,
913 avi_if
.checksum
= intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if
,
915 intel_sdvo_set_hdmi_buf(output
, 1, (uint8_t *)&avi_if
, 4 + avi_if
.len
,
919 static void intel_sdvo_set_tv_format(struct intel_output
*output
)
921 struct intel_sdvo_priv
*sdvo_priv
= output
->dev_priv
;
922 struct intel_sdvo_tv_format
*format
, unset
;
925 format
= &sdvo_priv
->tv_format
;
926 memset(&unset
, 0, sizeof(unset
));
927 if (memcmp(format
, &unset
, sizeof(*format
))) {
928 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
929 SDVO_NAME(sdvo_priv
));
931 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_TV_FORMAT
, format
,
933 status
= intel_sdvo_read_response(output
, NULL
, 0);
934 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
935 DRM_DEBUG("%s: Failed to set TV format\n",
936 SDVO_NAME(sdvo_priv
));
940 static bool intel_sdvo_mode_fixup(struct drm_encoder
*encoder
,
941 struct drm_display_mode
*mode
,
942 struct drm_display_mode
*adjusted_mode
)
944 struct intel_output
*output
= enc_to_intel_output(encoder
);
945 struct intel_sdvo_priv
*dev_priv
= output
->dev_priv
;
947 if (!dev_priv
->is_tv
) {
948 /* Make the CRTC code factor in the SDVO pixel multiplier. The
949 * SDVO device will be told of the multiplier during mode_set.
951 adjusted_mode
->clock
*= intel_sdvo_get_pixel_multiplier(mode
);
953 struct intel_sdvo_dtd output_dtd
;
956 /* We need to construct preferred input timings based on our
957 * output timings. To do that, we have to set the output
958 * timings, even though this isn't really the right place in
959 * the sequence to do it. Oh well.
963 /* Set output timings */
964 intel_sdvo_get_dtd_from_mode(&output_dtd
, mode
);
965 intel_sdvo_set_target_output(output
,
966 dev_priv
->controlled_output
);
967 intel_sdvo_set_output_timing(output
, &output_dtd
);
969 /* Set the input timing to the screen. Assume always input 0. */
970 intel_sdvo_set_target_input(output
, true, false);
973 success
= intel_sdvo_create_preferred_input_timing(output
,
978 struct intel_sdvo_dtd input_dtd
;
980 intel_sdvo_get_preferred_input_timing(output
,
982 intel_sdvo_get_mode_from_dtd(adjusted_mode
, &input_dtd
);
984 drm_mode_set_crtcinfo(adjusted_mode
, 0);
986 mode
->clock
= adjusted_mode
->clock
;
988 adjusted_mode
->clock
*=
989 intel_sdvo_get_pixel_multiplier(mode
);
997 static void intel_sdvo_mode_set(struct drm_encoder
*encoder
,
998 struct drm_display_mode
*mode
,
999 struct drm_display_mode
*adjusted_mode
)
1001 struct drm_device
*dev
= encoder
->dev
;
1002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1003 struct drm_crtc
*crtc
= encoder
->crtc
;
1004 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1005 struct intel_output
*output
= enc_to_intel_output(encoder
);
1006 struct intel_sdvo_priv
*sdvo_priv
= output
->dev_priv
;
1008 int sdvo_pixel_multiply
;
1009 struct intel_sdvo_in_out_map in_out
;
1010 struct intel_sdvo_dtd input_dtd
;
1016 /* First, set the input mapping for the first input to our controlled
1017 * output. This is only correct if we're a single-input device, in
1018 * which case the first input is the output from the appropriate SDVO
1019 * channel on the motherboard. In a two-input device, the first input
1020 * will be SDVOB and the second SDVOC.
1022 in_out
.in0
= sdvo_priv
->controlled_output
;
1025 intel_sdvo_write_cmd(output
, SDVO_CMD_SET_IN_OUT_MAP
,
1026 &in_out
, sizeof(in_out
));
1027 status
= intel_sdvo_read_response(output
, NULL
, 0);
1029 if (sdvo_priv
->is_hdmi
) {
1030 intel_sdvo_set_avi_infoframe(output
, mode
);
1031 sdvox
|= SDVO_AUDIO_ENABLE
;
1034 /* We have tried to get input timing in mode_fixup, and filled into
1036 if (sdvo_priv
->is_tv
)
1037 intel_sdvo_get_dtd_from_mode(&input_dtd
, adjusted_mode
);
1039 intel_sdvo_get_dtd_from_mode(&input_dtd
, mode
);
1041 /* If it's a TV, we already set the output timing in mode_fixup.
1042 * Otherwise, the output timing is equal to the input timing.
1044 if (!sdvo_priv
->is_tv
) {
1045 /* Set the output timing to the screen */
1046 intel_sdvo_set_target_output(output
,
1047 sdvo_priv
->controlled_output
);
1048 intel_sdvo_set_output_timing(output
, &input_dtd
);
1051 /* Set the input timing to the screen. Assume always input 0. */
1052 intel_sdvo_set_target_input(output
, true, false);
1054 if (sdvo_priv
->is_tv
)
1055 intel_sdvo_set_tv_format(output
);
1057 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1058 * provide the device with a timing it can support, if it supports that
1059 * feature. However, presumably we would need to adjust the CRTC to
1060 * output the preferred timing, and we don't support that currently.
1063 success
= intel_sdvo_create_preferred_input_timing(output
, clock
,
1066 struct intel_sdvo_dtd
*input_dtd
;
1068 intel_sdvo_get_preferred_input_timing(output
, &input_dtd
);
1069 intel_sdvo_set_input_timing(output
, &input_dtd
);
1072 intel_sdvo_set_input_timing(output
, &input_dtd
);
1075 switch (intel_sdvo_get_pixel_multiplier(mode
)) {
1077 intel_sdvo_set_clock_rate_mult(output
,
1078 SDVO_CLOCK_RATE_MULT_1X
);
1081 intel_sdvo_set_clock_rate_mult(output
,
1082 SDVO_CLOCK_RATE_MULT_2X
);
1085 intel_sdvo_set_clock_rate_mult(output
,
1086 SDVO_CLOCK_RATE_MULT_4X
);
1090 /* Set the SDVO control regs. */
1091 if (IS_I965G(dev
)) {
1092 sdvox
|= SDVO_BORDER_ENABLE
|
1093 SDVO_VSYNC_ACTIVE_HIGH
|
1094 SDVO_HSYNC_ACTIVE_HIGH
;
1096 sdvox
|= I915_READ(sdvo_priv
->output_device
);
1097 switch (sdvo_priv
->output_device
) {
1099 sdvox
&= SDVOB_PRESERVE_MASK
;
1102 sdvox
&= SDVOC_PRESERVE_MASK
;
1105 sdvox
|= (9 << 19) | SDVO_BORDER_ENABLE
;
1107 if (intel_crtc
->pipe
== 1)
1108 sdvox
|= SDVO_PIPE_B_SELECT
;
1110 sdvo_pixel_multiply
= intel_sdvo_get_pixel_multiplier(mode
);
1111 if (IS_I965G(dev
)) {
1112 /* done in crtc_mode_set as the dpll_md reg must be written early */
1113 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
1114 /* done in crtc_mode_set as it lives inside the dpll register */
1116 sdvox
|= (sdvo_pixel_multiply
- 1) << SDVO_PORT_MULTIPLY_SHIFT
;
1119 intel_sdvo_write_sdvox(output
, sdvox
);
1122 static void intel_sdvo_dpms(struct drm_encoder
*encoder
, int mode
)
1124 struct drm_device
*dev
= encoder
->dev
;
1125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1126 struct intel_output
*intel_output
= enc_to_intel_output(encoder
);
1127 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
1130 if (mode
!= DRM_MODE_DPMS_ON
) {
1131 intel_sdvo_set_active_outputs(intel_output
, 0);
1133 intel_sdvo_set_encoder_power_state(intel_output
, mode
);
1135 if (mode
== DRM_MODE_DPMS_OFF
) {
1136 temp
= I915_READ(sdvo_priv
->output_device
);
1137 if ((temp
& SDVO_ENABLE
) != 0) {
1138 intel_sdvo_write_sdvox(intel_output
, temp
& ~SDVO_ENABLE
);
1142 bool input1
, input2
;
1146 temp
= I915_READ(sdvo_priv
->output_device
);
1147 if ((temp
& SDVO_ENABLE
) == 0)
1148 intel_sdvo_write_sdvox(intel_output
, temp
| SDVO_ENABLE
);
1149 for (i
= 0; i
< 2; i
++)
1150 intel_wait_for_vblank(dev
);
1152 status
= intel_sdvo_get_trained_inputs(intel_output
, &input1
,
1156 /* Warn if the device reported failure to sync.
1157 * A lot of SDVO devices fail to notify of sync, but it's
1158 * a given it the status is a success, we succeeded.
1160 if (status
== SDVO_CMD_STATUS_SUCCESS
&& !input1
) {
1161 DRM_DEBUG("First %s output reported failure to sync\n",
1162 SDVO_NAME(sdvo_priv
));
1166 intel_sdvo_set_encoder_power_state(intel_output
, mode
);
1167 intel_sdvo_set_active_outputs(intel_output
, sdvo_priv
->controlled_output
);
1172 static void intel_sdvo_save(struct drm_connector
*connector
)
1174 struct drm_device
*dev
= connector
->dev
;
1175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1176 struct intel_output
*intel_output
= to_intel_output(connector
);
1177 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
1180 sdvo_priv
->save_sdvo_mult
= intel_sdvo_get_clock_rate_mult(intel_output
);
1181 intel_sdvo_get_active_outputs(intel_output
, &sdvo_priv
->save_active_outputs
);
1183 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x1) {
1184 intel_sdvo_set_target_input(intel_output
, true, false);
1185 intel_sdvo_get_input_timing(intel_output
,
1186 &sdvo_priv
->save_input_dtd_1
);
1189 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x2) {
1190 intel_sdvo_set_target_input(intel_output
, false, true);
1191 intel_sdvo_get_input_timing(intel_output
,
1192 &sdvo_priv
->save_input_dtd_2
);
1195 for (o
= SDVO_OUTPUT_FIRST
; o
<= SDVO_OUTPUT_LAST
; o
++)
1197 u16 this_output
= (1 << o
);
1198 if (sdvo_priv
->caps
.output_flags
& this_output
)
1200 intel_sdvo_set_target_output(intel_output
, this_output
);
1201 intel_sdvo_get_output_timing(intel_output
,
1202 &sdvo_priv
->save_output_dtd
[o
]);
1205 if (sdvo_priv
->is_tv
) {
1206 /* XXX: Save TV format/enhancements. */
1209 sdvo_priv
->save_SDVOX
= I915_READ(sdvo_priv
->output_device
);
1212 static void intel_sdvo_restore(struct drm_connector
*connector
)
1214 struct drm_device
*dev
= connector
->dev
;
1215 struct intel_output
*intel_output
= to_intel_output(connector
);
1216 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
1219 bool input1
, input2
;
1222 intel_sdvo_set_active_outputs(intel_output
, 0);
1224 for (o
= SDVO_OUTPUT_FIRST
; o
<= SDVO_OUTPUT_LAST
; o
++)
1226 u16 this_output
= (1 << o
);
1227 if (sdvo_priv
->caps
.output_flags
& this_output
) {
1228 intel_sdvo_set_target_output(intel_output
, this_output
);
1229 intel_sdvo_set_output_timing(intel_output
, &sdvo_priv
->save_output_dtd
[o
]);
1233 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x1) {
1234 intel_sdvo_set_target_input(intel_output
, true, false);
1235 intel_sdvo_set_input_timing(intel_output
, &sdvo_priv
->save_input_dtd_1
);
1238 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x2) {
1239 intel_sdvo_set_target_input(intel_output
, false, true);
1240 intel_sdvo_set_input_timing(intel_output
, &sdvo_priv
->save_input_dtd_2
);
1243 intel_sdvo_set_clock_rate_mult(intel_output
, sdvo_priv
->save_sdvo_mult
);
1245 if (sdvo_priv
->is_tv
) {
1246 /* XXX: Restore TV format/enhancements. */
1249 intel_sdvo_write_sdvox(intel_output
, sdvo_priv
->save_SDVOX
);
1251 if (sdvo_priv
->save_SDVOX
& SDVO_ENABLE
)
1253 for (i
= 0; i
< 2; i
++)
1254 intel_wait_for_vblank(dev
);
1255 status
= intel_sdvo_get_trained_inputs(intel_output
, &input1
, &input2
);
1256 if (status
== SDVO_CMD_STATUS_SUCCESS
&& !input1
)
1257 DRM_DEBUG("First %s output reported failure to sync\n",
1258 SDVO_NAME(sdvo_priv
));
1261 intel_sdvo_set_active_outputs(intel_output
, sdvo_priv
->save_active_outputs
);
1264 static int intel_sdvo_mode_valid(struct drm_connector
*connector
,
1265 struct drm_display_mode
*mode
)
1267 struct intel_output
*intel_output
= to_intel_output(connector
);
1268 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
1270 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
1271 return MODE_NO_DBLESCAN
;
1273 if (sdvo_priv
->pixel_clock_min
> mode
->clock
)
1274 return MODE_CLOCK_LOW
;
1276 if (sdvo_priv
->pixel_clock_max
< mode
->clock
)
1277 return MODE_CLOCK_HIGH
;
1282 static bool intel_sdvo_get_capabilities(struct intel_output
*intel_output
, struct intel_sdvo_caps
*caps
)
1286 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_DEVICE_CAPS
, NULL
, 0);
1287 status
= intel_sdvo_read_response(intel_output
, caps
, sizeof(*caps
));
1288 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
1294 struct drm_connector
* intel_sdvo_find(struct drm_device
*dev
, int sdvoB
)
1296 struct drm_connector
*connector
= NULL
;
1297 struct intel_output
*iout
= NULL
;
1298 struct intel_sdvo_priv
*sdvo
;
1300 /* find the sdvo connector */
1301 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1302 iout
= to_intel_output(connector
);
1304 if (iout
->type
!= INTEL_OUTPUT_SDVO
)
1307 sdvo
= iout
->dev_priv
;
1309 if (sdvo
->output_device
== SDVOB
&& sdvoB
)
1312 if (sdvo
->output_device
== SDVOC
&& !sdvoB
)
1320 int intel_sdvo_supports_hotplug(struct drm_connector
*connector
)
1324 struct intel_output
*intel_output
;
1330 intel_output
= to_intel_output(connector
);
1332 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_HOT_PLUG_SUPPORT
, NULL
, 0);
1333 status
= intel_sdvo_read_response(intel_output
, &response
, 2);
1335 if (response
[0] !=0)
1341 void intel_sdvo_set_hotplug(struct drm_connector
*connector
, int on
)
1345 struct intel_output
*intel_output
= to_intel_output(connector
);
1347 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_ACTIVE_HOT_PLUG
, NULL
, 0);
1348 intel_sdvo_read_response(intel_output
, &response
, 2);
1351 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_HOT_PLUG_SUPPORT
, NULL
, 0);
1352 status
= intel_sdvo_read_response(intel_output
, &response
, 2);
1354 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_ACTIVE_HOT_PLUG
, &response
, 2);
1358 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_SET_ACTIVE_HOT_PLUG
, &response
, 2);
1361 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_ACTIVE_HOT_PLUG
, NULL
, 0);
1362 intel_sdvo_read_response(intel_output
, &response
, 2);
1366 intel_sdvo_hdmi_sink_detect(struct drm_connector
*connector
)
1368 struct intel_output
*intel_output
= to_intel_output(connector
);
1369 struct intel_sdvo_priv
*sdvo_priv
= intel_output
->dev_priv
;
1370 struct edid
*edid
= NULL
;
1372 edid
= drm_get_edid(&intel_output
->base
,
1373 intel_output
->ddc_bus
);
1375 sdvo_priv
->is_hdmi
= drm_detect_hdmi_monitor(edid
);
1377 intel_output
->base
.display_info
.raw_edid
= NULL
;
1381 static enum drm_connector_status
intel_sdvo_detect(struct drm_connector
*connector
)
1385 struct intel_output
*intel_output
= to_intel_output(connector
);
1387 intel_sdvo_write_cmd(intel_output
, SDVO_CMD_GET_ATTACHED_DISPLAYS
, NULL
, 0);
1388 status
= intel_sdvo_read_response(intel_output
, &response
, 2);
1390 DRM_DEBUG("SDVO response %d %d\n", response
[0], response
[1]);
1392 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
1393 return connector_status_unknown
;
1395 if ((response
[0] != 0) || (response
[1] != 0)) {
1396 intel_sdvo_hdmi_sink_detect(connector
);
1397 return connector_status_connected
;
1399 return connector_status_disconnected
;
1402 static void intel_sdvo_get_ddc_modes(struct drm_connector
*connector
)
1404 struct intel_output
*intel_output
= to_intel_output(connector
);
1406 /* set the bus switch and get the modes */
1407 intel_ddc_get_modes(intel_output
);
1410 struct drm_device
*dev
= encoder
->dev
;
1411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1412 /* Mac mini hack. On this device, I get DDC through the analog, which
1413 * load-detects as disconnected. I fail to DDC through the SDVO DDC,
1414 * but it does load-detect as connected. So, just steal the DDC bits
1415 * from analog when we fail at finding it the right way.
1417 crt
= xf86_config
->output
[0];
1418 intel_output
= crt
->driver_private
;
1419 if (intel_output
->type
== I830_OUTPUT_ANALOG
&&
1420 crt
->funcs
->detect(crt
) == XF86OutputStatusDisconnected
) {
1421 I830I2CInit(pScrn
, &intel_output
->pDDCBus
, GPIOA
, "CRTDDC_A");
1422 edid_mon
= xf86OutputGetEDID(crt
, intel_output
->pDDCBus
);
1423 xf86DestroyI2CBusRec(intel_output
->pDDCBus
, true, true);
1426 xf86OutputSetEDID(output
, edid_mon
);
1427 modes
= xf86OutputGetEDIDModes(output
);
1433 * This function checks the current TV format, and chooses a default if
1434 * it hasn't been set.
1437 intel_sdvo_check_tv_format(struct intel_output
*output
)
1439 struct intel_sdvo_priv
*dev_priv
= output
->dev_priv
;
1440 struct intel_sdvo_tv_format format
;
1443 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_TV_FORMAT
, NULL
, 0);
1444 status
= intel_sdvo_read_response(output
, &format
, sizeof(format
));
1445 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
1448 memcpy(&dev_priv
->tv_format
, &format
, sizeof(format
));
1452 * Set of SDVO TV modes.
1453 * Note! This is in reply order (see loop in get_tv_modes).
1454 * XXX: all 60Hz refresh?
1456 struct drm_display_mode sdvo_tv_modes
[] = {
1457 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER
, 5815, 320, 321, 384,
1458 416, 0, 200, 201, 232, 233, 0,
1459 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1460 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER
, 6814, 320, 321, 384,
1461 416, 0, 240, 241, 272, 273, 0,
1462 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1463 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER
, 9910, 400, 401, 464,
1464 496, 0, 300, 301, 332, 333, 0,
1465 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1466 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER
, 16913, 640, 641, 704,
1467 736, 0, 350, 351, 382, 383, 0,
1468 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1469 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER
, 19121, 640, 641, 704,
1470 736, 0, 400, 401, 432, 433, 0,
1471 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1472 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 22654, 640, 641, 704,
1473 736, 0, 480, 481, 512, 513, 0,
1474 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1475 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER
, 24624, 704, 705, 768,
1476 800, 0, 480, 481, 512, 513, 0,
1477 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1478 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER
, 29232, 704, 705, 768,
1479 800, 0, 576, 577, 608, 609, 0,
1480 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1481 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER
, 18751, 720, 721, 784,
1482 816, 0, 350, 351, 382, 383, 0,
1483 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1484 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER
, 21199, 720, 721, 784,
1485 816, 0, 400, 401, 432, 433, 0,
1486 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1487 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 25116, 720, 721, 784,
1488 816, 0, 480, 481, 512, 513, 0,
1489 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1490 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER
, 28054, 720, 721, 784,
1491 816, 0, 540, 541, 572, 573, 0,
1492 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1493 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 29816, 720, 721, 784,
1494 816, 0, 576, 577, 608, 609, 0,
1495 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1496 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER
, 31570, 768, 769, 832,
1497 864, 0, 576, 577, 608, 609, 0,
1498 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1499 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 34030, 800, 801, 864,
1500 896, 0, 600, 601, 632, 633, 0,
1501 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1502 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER
, 36581, 832, 833, 896,
1503 928, 0, 624, 625, 656, 657, 0,
1504 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1505 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER
, 48707, 920, 921, 984,
1506 1016, 0, 766, 767, 798, 799, 0,
1507 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1508 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 53827, 1024, 1025, 1088,
1509 1120, 0, 768, 769, 800, 801, 0,
1510 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1511 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER
, 87265, 1280, 1281, 1344,
1512 1376, 0, 1024, 1025, 1056, 1057, 0,
1513 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
1516 static void intel_sdvo_get_tv_modes(struct drm_connector
*connector
)
1518 struct intel_output
*output
= to_intel_output(connector
);
1519 struct intel_sdvo_priv
*sdvo_priv
= output
->dev_priv
;
1520 struct intel_sdvo_sdtv_resolution_request tv_res
;
1525 intel_sdvo_check_tv_format(output
);
1527 /* Read the list of supported input resolutions for the selected TV
1530 memset(&tv_res
, 0, sizeof(tv_res
));
1531 memcpy(&tv_res
, &sdvo_priv
->tv_format
, sizeof(tv_res
));
1532 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT
,
1533 &tv_res
, sizeof(tv_res
));
1534 status
= intel_sdvo_read_response(output
, &reply
, 3);
1535 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
1538 for (i
= 0; i
< ARRAY_SIZE(sdvo_tv_modes
); i
++)
1539 if (reply
& (1 << i
)) {
1540 struct drm_display_mode
*nmode
;
1541 nmode
= drm_mode_duplicate(connector
->dev
,
1544 drm_mode_probed_add(connector
, nmode
);
1548 static void intel_sdvo_get_lvds_modes(struct drm_connector
*connector
)
1550 struct intel_output
*intel_output
= to_intel_output(connector
);
1551 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
1554 * Attempt to get the mode list from DDC.
1555 * Assume that the preferred modes are
1556 * arranged in priority order.
1558 intel_ddc_get_modes(intel_output
);
1559 if (list_empty(&connector
->probed_modes
) == false)
1562 /* Fetch modes from VBT */
1563 if (dev_priv
->sdvo_lvds_vbt_mode
!= NULL
) {
1564 struct drm_display_mode
*newmode
;
1565 newmode
= drm_mode_duplicate(connector
->dev
,
1566 dev_priv
->sdvo_lvds_vbt_mode
);
1567 if (newmode
!= NULL
) {
1568 /* Guarantee the mode is preferred */
1569 newmode
->type
= (DRM_MODE_TYPE_PREFERRED
|
1570 DRM_MODE_TYPE_DRIVER
);
1571 drm_mode_probed_add(connector
, newmode
);
1576 static int intel_sdvo_get_modes(struct drm_connector
*connector
)
1578 struct intel_output
*output
= to_intel_output(connector
);
1579 struct intel_sdvo_priv
*sdvo_priv
= output
->dev_priv
;
1581 if (sdvo_priv
->is_tv
)
1582 intel_sdvo_get_tv_modes(connector
);
1583 else if (sdvo_priv
->is_lvds
== true)
1584 intel_sdvo_get_lvds_modes(connector
);
1586 intel_sdvo_get_ddc_modes(connector
);
1588 if (list_empty(&connector
->probed_modes
))
1593 static void intel_sdvo_destroy(struct drm_connector
*connector
)
1595 struct intel_output
*intel_output
= to_intel_output(connector
);
1597 if (intel_output
->i2c_bus
)
1598 intel_i2c_destroy(intel_output
->i2c_bus
);
1599 if (intel_output
->ddc_bus
)
1600 intel_i2c_destroy(intel_output
->ddc_bus
);
1602 drm_sysfs_connector_remove(connector
);
1603 drm_connector_cleanup(connector
);
1604 kfree(intel_output
);
1607 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs
= {
1608 .dpms
= intel_sdvo_dpms
,
1609 .mode_fixup
= intel_sdvo_mode_fixup
,
1610 .prepare
= intel_encoder_prepare
,
1611 .mode_set
= intel_sdvo_mode_set
,
1612 .commit
= intel_encoder_commit
,
1615 static const struct drm_connector_funcs intel_sdvo_connector_funcs
= {
1616 .dpms
= drm_helper_connector_dpms
,
1617 .save
= intel_sdvo_save
,
1618 .restore
= intel_sdvo_restore
,
1619 .detect
= intel_sdvo_detect
,
1620 .fill_modes
= drm_helper_probe_single_connector_modes
,
1621 .destroy
= intel_sdvo_destroy
,
1624 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs
= {
1625 .get_modes
= intel_sdvo_get_modes
,
1626 .mode_valid
= intel_sdvo_mode_valid
,
1627 .best_encoder
= intel_best_encoder
,
1630 static void intel_sdvo_enc_destroy(struct drm_encoder
*encoder
)
1632 drm_encoder_cleanup(encoder
);
1635 static const struct drm_encoder_funcs intel_sdvo_enc_funcs
= {
1636 .destroy
= intel_sdvo_enc_destroy
,
1641 * Choose the appropriate DDC bus for control bus switch command for this
1642 * SDVO output based on the controlled output.
1644 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1645 * outputs, then LVDS outputs.
1648 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv
*dev_priv
)
1651 unsigned int num_bits
;
1653 /* Make a mask of outputs less than or equal to our own priority in the
1656 switch (dev_priv
->controlled_output
) {
1657 case SDVO_OUTPUT_LVDS1
:
1658 mask
|= SDVO_OUTPUT_LVDS1
;
1659 case SDVO_OUTPUT_LVDS0
:
1660 mask
|= SDVO_OUTPUT_LVDS0
;
1661 case SDVO_OUTPUT_TMDS1
:
1662 mask
|= SDVO_OUTPUT_TMDS1
;
1663 case SDVO_OUTPUT_TMDS0
:
1664 mask
|= SDVO_OUTPUT_TMDS0
;
1665 case SDVO_OUTPUT_RGB1
:
1666 mask
|= SDVO_OUTPUT_RGB1
;
1667 case SDVO_OUTPUT_RGB0
:
1668 mask
|= SDVO_OUTPUT_RGB0
;
1672 /* Count bits to find what number we are in the priority list. */
1673 mask
&= dev_priv
->caps
.output_flags
;
1674 num_bits
= hweight16(mask
);
1676 /* if more than 3 outputs, default to DDC bus 3 for now */
1680 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1681 dev_priv
->ddc_bus
= 1 << num_bits
;
1685 intel_sdvo_get_digital_encoding_mode(struct intel_output
*output
)
1687 struct intel_sdvo_priv
*sdvo_priv
= output
->dev_priv
;
1690 intel_sdvo_set_target_output(output
, sdvo_priv
->controlled_output
);
1692 intel_sdvo_write_cmd(output
, SDVO_CMD_GET_ENCODE
, NULL
, 0);
1693 status
= intel_sdvo_read_response(output
, &sdvo_priv
->is_hdmi
, 1);
1694 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
1699 static struct intel_output
*
1700 intel_sdvo_chan_to_intel_output(struct intel_i2c_chan
*chan
)
1702 struct drm_device
*dev
= chan
->drm_dev
;
1703 struct drm_connector
*connector
;
1704 struct intel_output
*intel_output
= NULL
;
1706 list_for_each_entry(connector
,
1707 &dev
->mode_config
.connector_list
, head
) {
1708 if (to_intel_output(connector
)->ddc_bus
== &chan
->adapter
) {
1709 intel_output
= to_intel_output(connector
);
1713 return intel_output
;
1716 static int intel_sdvo_master_xfer(struct i2c_adapter
*i2c_adap
,
1717 struct i2c_msg msgs
[], int num
)
1719 struct intel_output
*intel_output
;
1720 struct intel_sdvo_priv
*sdvo_priv
;
1721 struct i2c_algo_bit_data
*algo_data
;
1722 const struct i2c_algorithm
*algo
;
1724 algo_data
= (struct i2c_algo_bit_data
*)i2c_adap
->algo_data
;
1726 intel_sdvo_chan_to_intel_output(
1727 (struct intel_i2c_chan
*)(algo_data
->data
));
1728 if (intel_output
== NULL
)
1731 sdvo_priv
= intel_output
->dev_priv
;
1732 algo
= intel_output
->i2c_bus
->algo
;
1734 intel_sdvo_set_control_bus_switch(intel_output
, sdvo_priv
->ddc_bus
);
1735 return algo
->master_xfer(i2c_adap
, msgs
, num
);
1738 static struct i2c_algorithm intel_sdvo_i2c_bit_algo
= {
1739 .master_xfer
= intel_sdvo_master_xfer
,
1743 intel_sdvo_get_slave_addr(struct drm_device
*dev
, int output_device
)
1745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1746 struct sdvo_device_mapping
*my_mapping
, *other_mapping
;
1748 if (output_device
== SDVOB
) {
1749 my_mapping
= &dev_priv
->sdvo_mappings
[0];
1750 other_mapping
= &dev_priv
->sdvo_mappings
[1];
1752 my_mapping
= &dev_priv
->sdvo_mappings
[1];
1753 other_mapping
= &dev_priv
->sdvo_mappings
[0];
1756 /* If the BIOS described our SDVO device, take advantage of it. */
1757 if (my_mapping
->slave_addr
)
1758 return my_mapping
->slave_addr
;
1760 /* If the BIOS only described a different SDVO device, use the
1761 * address that it isn't using.
1763 if (other_mapping
->slave_addr
) {
1764 if (other_mapping
->slave_addr
== 0x70)
1770 /* No SDVO device info is found for another DVO port,
1771 * so use mapping assumption we had before BIOS parsing.
1773 if (output_device
== SDVOB
)
1779 bool intel_sdvo_init(struct drm_device
*dev
, int output_device
)
1781 struct drm_connector
*connector
;
1782 struct intel_output
*intel_output
;
1783 struct intel_sdvo_priv
*sdvo_priv
;
1790 intel_output
= kcalloc(sizeof(struct intel_output
)+sizeof(struct intel_sdvo_priv
), 1, GFP_KERNEL
);
1791 if (!intel_output
) {
1795 sdvo_priv
= (struct intel_sdvo_priv
*)(intel_output
+ 1);
1796 sdvo_priv
->output_device
= output_device
;
1798 intel_output
->dev_priv
= sdvo_priv
;
1799 intel_output
->type
= INTEL_OUTPUT_SDVO
;
1801 /* setup the DDC bus. */
1802 if (output_device
== SDVOB
)
1803 intel_output
->i2c_bus
= intel_i2c_create(dev
, GPIOE
, "SDVOCTRL_E for SDVOB");
1805 intel_output
->i2c_bus
= intel_i2c_create(dev
, GPIOE
, "SDVOCTRL_E for SDVOC");
1807 if (!intel_output
->i2c_bus
)
1808 goto err_inteloutput
;
1810 sdvo_priv
->slave_addr
= intel_sdvo_get_slave_addr(dev
, output_device
);
1812 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
1813 intel_sdvo_i2c_bit_algo
.functionality
= intel_output
->i2c_bus
->algo
->functionality
;
1815 /* Read the regs to test if we can talk to the device */
1816 for (i
= 0; i
< 0x40; i
++) {
1817 if (!intel_sdvo_read_byte(intel_output
, i
, &ch
[i
])) {
1818 DRM_DEBUG_KMS(I915_SDVO
,
1819 "No SDVO device found on SDVO%c\n",
1820 output_device
== SDVOB
? 'B' : 'C');
1825 /* setup the DDC bus. */
1826 if (output_device
== SDVOB
)
1827 intel_output
->ddc_bus
= intel_i2c_create(dev
, GPIOE
, "SDVOB DDC BUS");
1829 intel_output
->ddc_bus
= intel_i2c_create(dev
, GPIOE
, "SDVOC DDC BUS");
1831 if (intel_output
->ddc_bus
== NULL
)
1834 /* Wrap with our custom algo which switches to DDC mode */
1835 intel_output
->ddc_bus
->algo
= &intel_sdvo_i2c_bit_algo
;
1837 /* In defaut case sdvo lvds is false */
1838 sdvo_priv
->is_lvds
= false;
1839 intel_sdvo_get_capabilities(intel_output
, &sdvo_priv
->caps
);
1841 if (sdvo_priv
->caps
.output_flags
&
1842 (SDVO_OUTPUT_TMDS0
| SDVO_OUTPUT_TMDS1
)) {
1843 if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_TMDS0
)
1844 sdvo_priv
->controlled_output
= SDVO_OUTPUT_TMDS0
;
1846 sdvo_priv
->controlled_output
= SDVO_OUTPUT_TMDS1
;
1848 encoder_type
= DRM_MODE_ENCODER_TMDS
;
1849 connector_type
= DRM_MODE_CONNECTOR_DVID
;
1851 if (intel_sdvo_get_supp_encode(intel_output
,
1852 &sdvo_priv
->encode
) &&
1853 intel_sdvo_get_digital_encoding_mode(intel_output
) &&
1854 sdvo_priv
->is_hdmi
) {
1855 /* enable hdmi encoding mode if supported */
1856 intel_sdvo_set_encode(intel_output
, SDVO_ENCODE_HDMI
);
1857 intel_sdvo_set_colorimetry(intel_output
,
1858 SDVO_COLORIMETRY_RGB256
);
1859 connector_type
= DRM_MODE_CONNECTOR_HDMIA
;
1862 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_SVID0
)
1864 sdvo_priv
->controlled_output
= SDVO_OUTPUT_SVID0
;
1865 encoder_type
= DRM_MODE_ENCODER_TVDAC
;
1866 connector_type
= DRM_MODE_CONNECTOR_SVIDEO
;
1867 sdvo_priv
->is_tv
= true;
1868 intel_output
->needs_tv_clock
= true;
1870 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_RGB0
)
1872 sdvo_priv
->controlled_output
= SDVO_OUTPUT_RGB0
;
1873 encoder_type
= DRM_MODE_ENCODER_DAC
;
1874 connector_type
= DRM_MODE_CONNECTOR_VGA
;
1876 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_RGB1
)
1878 sdvo_priv
->controlled_output
= SDVO_OUTPUT_RGB1
;
1879 encoder_type
= DRM_MODE_ENCODER_DAC
;
1880 connector_type
= DRM_MODE_CONNECTOR_VGA
;
1882 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_LVDS0
)
1884 sdvo_priv
->controlled_output
= SDVO_OUTPUT_LVDS0
;
1885 encoder_type
= DRM_MODE_ENCODER_LVDS
;
1886 connector_type
= DRM_MODE_CONNECTOR_LVDS
;
1887 sdvo_priv
->is_lvds
= true;
1889 else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_LVDS1
)
1891 sdvo_priv
->controlled_output
= SDVO_OUTPUT_LVDS1
;
1892 encoder_type
= DRM_MODE_ENCODER_LVDS
;
1893 connector_type
= DRM_MODE_CONNECTOR_LVDS
;
1894 sdvo_priv
->is_lvds
= true;
1898 unsigned char bytes
[2];
1900 sdvo_priv
->controlled_output
= 0;
1901 memcpy (bytes
, &sdvo_priv
->caps
.output_flags
, 2);
1902 DRM_DEBUG_KMS(I915_SDVO
,
1903 "%s: Unknown SDVO output type (0x%02x%02x)\n",
1904 SDVO_NAME(sdvo_priv
),
1905 bytes
[0], bytes
[1]);
1906 encoder_type
= DRM_MODE_ENCODER_NONE
;
1907 connector_type
= DRM_MODE_CONNECTOR_Unknown
;
1911 connector
= &intel_output
->base
;
1912 drm_connector_init(dev
, connector
, &intel_sdvo_connector_funcs
,
1914 drm_connector_helper_add(connector
, &intel_sdvo_connector_helper_funcs
);
1915 connector
->interlace_allowed
= 0;
1916 connector
->doublescan_allowed
= 0;
1917 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
;
1919 drm_encoder_init(dev
, &intel_output
->enc
, &intel_sdvo_enc_funcs
, encoder_type
);
1920 drm_encoder_helper_add(&intel_output
->enc
, &intel_sdvo_helper_funcs
);
1922 drm_mode_connector_attach_encoder(&intel_output
->base
, &intel_output
->enc
);
1923 drm_sysfs_connector_add(connector
);
1925 intel_sdvo_select_ddc_bus(sdvo_priv
);
1927 /* Set the input timing to the screen. Assume always input 0. */
1928 intel_sdvo_set_target_input(intel_output
, true, false);
1930 intel_sdvo_get_input_pixel_clock_range(intel_output
,
1931 &sdvo_priv
->pixel_clock_min
,
1932 &sdvo_priv
->pixel_clock_max
);
1935 DRM_DEBUG_KMS(I915_SDVO
, "%s device VID/DID: %02X:%02X.%02X, "
1936 "clock range %dMHz - %dMHz, "
1937 "input 1: %c, input 2: %c, "
1938 "output 1: %c, output 2: %c\n",
1939 SDVO_NAME(sdvo_priv
),
1940 sdvo_priv
->caps
.vendor_id
, sdvo_priv
->caps
.device_id
,
1941 sdvo_priv
->caps
.device_rev_id
,
1942 sdvo_priv
->pixel_clock_min
/ 1000,
1943 sdvo_priv
->pixel_clock_max
/ 1000,
1944 (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x1) ? 'Y' : 'N',
1945 (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x2) ? 'Y' : 'N',
1946 /* check currently supported outputs */
1947 sdvo_priv
->caps
.output_flags
&
1948 (SDVO_OUTPUT_TMDS0
| SDVO_OUTPUT_RGB0
) ? 'Y' : 'N',
1949 sdvo_priv
->caps
.output_flags
&
1950 (SDVO_OUTPUT_TMDS1
| SDVO_OUTPUT_RGB1
) ? 'Y' : 'N');
1955 if (intel_output
->ddc_bus
!= NULL
)
1956 intel_i2c_destroy(intel_output
->ddc_bus
);
1957 if (intel_output
->i2c_bus
!= NULL
)
1958 intel_i2c_destroy(intel_output
->i2c_bus
);
1960 kfree(intel_output
);