2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_plane_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
43 format_is_yuv(uint32_t format
)
56 static int usecs_to_scanlines(const struct drm_display_mode
*adjusted_mode
,
60 if (!adjusted_mode
->crtc_htotal
)
63 return DIV_ROUND_UP(usecs
* adjusted_mode
->crtc_clock
,
64 1000 * adjusted_mode
->crtc_htotal
);
68 * intel_pipe_update_start() - start update of a set of display registers
69 * @crtc: the crtc of which the registers are going to be updated
70 * @start_vbl_count: vblank counter return pointer used for error checking
72 * Mark the start of an update to pipe registers that should be updated
73 * atomically regarding vblank. If the next vblank will happens within
74 * the next 100 us, this function waits until the vblank passes.
76 * After a successful call to this function, interrupts will be disabled
77 * until a subsequent call to intel_pipe_update_end(). That is done to
78 * avoid random delays. The value written to @start_vbl_count should be
79 * supplied to intel_pipe_update_end() for error checking.
81 void intel_pipe_update_start(struct intel_crtc
*crtc
)
83 struct drm_device
*dev
= crtc
->base
.dev
;
84 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
85 enum pipe pipe
= crtc
->pipe
;
86 long timeout
= msecs_to_jiffies_timeout(1);
87 int scanline
, min
, max
, vblank_start
;
88 wait_queue_head_t
*wq
= drm_crtc_vblank_waitqueue(&crtc
->base
);
91 vblank_start
= adjusted_mode
->crtc_vblank_start
;
92 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
93 vblank_start
= DIV_ROUND_UP(vblank_start
, 2);
95 /* FIXME needs to be calibrated sensibly */
96 min
= vblank_start
- usecs_to_scanlines(adjusted_mode
, 100);
97 max
= vblank_start
- 1;
101 if (min
<= 0 || max
<= 0)
104 if (WARN_ON(drm_crtc_vblank_get(&crtc
->base
)))
107 crtc
->debug
.min_vbl
= min
;
108 crtc
->debug
.max_vbl
= max
;
109 trace_i915_pipe_update_start(crtc
);
113 * prepare_to_wait() has a memory barrier, which guarantees
114 * other CPUs can see the task state update by the time we
117 prepare_to_wait(wq
, &wait
, TASK_UNINTERRUPTIBLE
);
119 scanline
= intel_get_crtc_scanline(crtc
);
120 if (scanline
< min
|| scanline
> max
)
124 DRM_ERROR("Potential atomic update failure on pipe %c\n",
125 pipe_name(crtc
->pipe
));
131 timeout
= schedule_timeout(timeout
);
136 finish_wait(wq
, &wait
);
138 drm_crtc_vblank_put(&crtc
->base
);
140 crtc
->debug
.scanline_start
= scanline
;
141 crtc
->debug
.start_vbl_time
= ktime_get();
142 crtc
->debug
.start_vbl_count
=
143 dev
->driver
->get_vblank_counter(dev
, pipe
);
145 trace_i915_pipe_update_vblank_evaded(crtc
);
149 * intel_pipe_update_end() - end update of a set of display registers
150 * @crtc: the crtc of which the registers were updated
151 * @start_vbl_count: start vblank counter (used for error checking)
153 * Mark the end of an update started with intel_pipe_update_start(). This
154 * re-enables interrupts and verifies the update was actually completed
155 * before a vblank using the value of @start_vbl_count.
157 void intel_pipe_update_end(struct intel_crtc
*crtc
)
159 struct drm_device
*dev
= crtc
->base
.dev
;
160 enum pipe pipe
= crtc
->pipe
;
161 int scanline_end
= intel_get_crtc_scanline(crtc
);
162 u32 end_vbl_count
= dev
->driver
->get_vblank_counter(dev
, pipe
);
163 ktime_t end_vbl_time
= ktime_get();
165 trace_i915_pipe_update_end(crtc
, end_vbl_count
, scanline_end
);
169 if (crtc
->debug
.start_vbl_count
&&
170 crtc
->debug
.start_vbl_count
!= end_vbl_count
) {
171 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
172 pipe_name(pipe
), crtc
->debug
.start_vbl_count
,
174 ktime_us_delta(end_vbl_time
, crtc
->debug
.start_vbl_time
),
175 crtc
->debug
.min_vbl
, crtc
->debug
.max_vbl
,
176 crtc
->debug
.scanline_start
, scanline_end
);
181 skl_update_plane(struct drm_plane
*drm_plane
,
182 const struct intel_crtc_state
*crtc_state
,
183 const struct intel_plane_state
*plane_state
)
185 struct drm_device
*dev
= drm_plane
->dev
;
186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
187 struct intel_plane
*intel_plane
= to_intel_plane(drm_plane
);
188 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
189 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
190 const int pipe
= intel_plane
->pipe
;
191 const int plane
= intel_plane
->plane
+ 1;
192 u32 plane_ctl
, stride_div
, stride
;
193 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
195 u32 tile_height
, plane_offset
, plane_size
;
196 unsigned int rotation
;
197 int x_offset
, y_offset
;
198 int crtc_x
= plane_state
->dst
.x1
;
199 int crtc_y
= plane_state
->dst
.y1
;
200 uint32_t crtc_w
= drm_rect_width(&plane_state
->dst
);
201 uint32_t crtc_h
= drm_rect_height(&plane_state
->dst
);
202 uint32_t x
= plane_state
->src
.x1
>> 16;
203 uint32_t y
= plane_state
->src
.y1
>> 16;
204 uint32_t src_w
= drm_rect_width(&plane_state
->src
) >> 16;
205 uint32_t src_h
= drm_rect_height(&plane_state
->src
) >> 16;
206 const struct intel_scaler
*scaler
=
207 &crtc_state
->scaler_state
.scalers
[plane_state
->scaler_id
];
209 plane_ctl
= PLANE_CTL_ENABLE
|
210 PLANE_CTL_PIPE_GAMMA_ENABLE
|
211 PLANE_CTL_PIPE_CSC_ENABLE
;
213 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
214 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
216 rotation
= plane_state
->base
.rotation
;
217 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
219 stride_div
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
222 /* Sizes are 0 based */
229 I915_WRITE(PLANE_KEYVAL(pipe
, plane
), key
->min_value
);
230 I915_WRITE(PLANE_KEYMAX(pipe
, plane
), key
->max_value
);
231 I915_WRITE(PLANE_KEYMSK(pipe
, plane
), key
->channel_mask
);
234 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
235 plane_ctl
|= PLANE_CTL_KEY_ENABLE_DESTINATION
;
236 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
237 plane_ctl
|= PLANE_CTL_KEY_ENABLE_SOURCE
;
239 surf_addr
= intel_plane_obj_offset(intel_plane
, obj
, 0);
241 if (intel_rotation_90_or_270(rotation
)) {
242 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
244 /* stride: Surface height in tiles */
245 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], cpp
);
246 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
247 plane_size
= (src_w
<< 16) | src_h
;
248 x_offset
= stride
* tile_height
- y
- (src_h
+ 1);
251 stride
= fb
->pitches
[0] / stride_div
;
252 plane_size
= (src_h
<< 16) | src_w
;
256 plane_offset
= y_offset
<< 16 | x_offset
;
258 I915_WRITE(PLANE_OFFSET(pipe
, plane
), plane_offset
);
259 I915_WRITE(PLANE_STRIDE(pipe
, plane
), stride
);
260 I915_WRITE(PLANE_SIZE(pipe
, plane
), plane_size
);
262 /* program plane scaler */
263 if (plane_state
->scaler_id
>= 0) {
264 uint32_t ps_ctrl
= 0;
265 int scaler_id
= plane_state
->scaler_id
;
267 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane
,
268 PS_PLANE_SEL(plane
));
269 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(plane
) | scaler
->mode
;
270 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
271 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
272 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (crtc_x
<< 16) | crtc_y
);
273 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
),
274 ((crtc_w
+ 1) << 16)|(crtc_h
+ 1));
276 I915_WRITE(PLANE_POS(pipe
, plane
), 0);
278 I915_WRITE(PLANE_POS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
281 I915_WRITE(PLANE_CTL(pipe
, plane
), plane_ctl
);
282 I915_WRITE(PLANE_SURF(pipe
, plane
), surf_addr
);
283 POSTING_READ(PLANE_SURF(pipe
, plane
));
287 skl_disable_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
)
289 struct drm_device
*dev
= dplane
->dev
;
290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
291 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
292 const int pipe
= intel_plane
->pipe
;
293 const int plane
= intel_plane
->plane
+ 1;
295 I915_WRITE(PLANE_CTL(pipe
, plane
), 0);
297 I915_WRITE(PLANE_SURF(pipe
, plane
), 0);
298 POSTING_READ(PLANE_SURF(pipe
, plane
));
302 chv_update_csc(struct intel_plane
*intel_plane
, uint32_t format
)
304 struct drm_i915_private
*dev_priv
= intel_plane
->base
.dev
->dev_private
;
305 int plane
= intel_plane
->plane
;
307 /* Seems RGB data bypasses the CSC always */
308 if (!format_is_yuv(format
))
312 * BT.601 limited range YCbCr -> full range RGB
314 * |r| | 6537 4769 0| |cr |
315 * |g| = |-3330 4769 -1605| x |y-64|
316 * |b| | 0 4769 8263| |cb |
318 * Cb and Cr apparently come in as signed already, so no
319 * need for any offset. For Y we need to remove the offset.
321 I915_WRITE(SPCSCYGOFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
322 I915_WRITE(SPCSCCBOFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
323 I915_WRITE(SPCSCCROFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
325 I915_WRITE(SPCSCC01(plane
), SPCSC_C1(4769) | SPCSC_C0(6537));
326 I915_WRITE(SPCSCC23(plane
), SPCSC_C1(-3330) | SPCSC_C0(0));
327 I915_WRITE(SPCSCC45(plane
), SPCSC_C1(-1605) | SPCSC_C0(4769));
328 I915_WRITE(SPCSCC67(plane
), SPCSC_C1(4769) | SPCSC_C0(0));
329 I915_WRITE(SPCSCC8(plane
), SPCSC_C0(8263));
331 I915_WRITE(SPCSCYGICLAMP(plane
), SPCSC_IMAX(940) | SPCSC_IMIN(64));
332 I915_WRITE(SPCSCCBICLAMP(plane
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
333 I915_WRITE(SPCSCCRICLAMP(plane
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
335 I915_WRITE(SPCSCYGOCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
336 I915_WRITE(SPCSCCBOCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
337 I915_WRITE(SPCSCCROCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
341 vlv_update_plane(struct drm_plane
*dplane
,
342 const struct intel_crtc_state
*crtc_state
,
343 const struct intel_plane_state
*plane_state
)
345 struct drm_device
*dev
= dplane
->dev
;
346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
347 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
348 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
349 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
350 int pipe
= intel_plane
->pipe
;
351 int plane
= intel_plane
->plane
;
353 unsigned long sprsurf_offset
, linear_offset
;
354 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
355 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
356 int crtc_x
= plane_state
->dst
.x1
;
357 int crtc_y
= plane_state
->dst
.y1
;
358 uint32_t crtc_w
= drm_rect_width(&plane_state
->dst
);
359 uint32_t crtc_h
= drm_rect_height(&plane_state
->dst
);
360 uint32_t x
= plane_state
->src
.x1
>> 16;
361 uint32_t y
= plane_state
->src
.y1
>> 16;
362 uint32_t src_w
= drm_rect_width(&plane_state
->src
) >> 16;
363 uint32_t src_h
= drm_rect_height(&plane_state
->src
) >> 16;
367 switch (fb
->pixel_format
) {
368 case DRM_FORMAT_YUYV
:
369 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YUYV
;
371 case DRM_FORMAT_YVYU
:
372 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YVYU
;
374 case DRM_FORMAT_UYVY
:
375 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_UYVY
;
377 case DRM_FORMAT_VYUY
:
378 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_VYUY
;
380 case DRM_FORMAT_RGB565
:
381 sprctl
|= SP_FORMAT_BGR565
;
383 case DRM_FORMAT_XRGB8888
:
384 sprctl
|= SP_FORMAT_BGRX8888
;
386 case DRM_FORMAT_ARGB8888
:
387 sprctl
|= SP_FORMAT_BGRA8888
;
389 case DRM_FORMAT_XBGR2101010
:
390 sprctl
|= SP_FORMAT_RGBX1010102
;
392 case DRM_FORMAT_ABGR2101010
:
393 sprctl
|= SP_FORMAT_RGBA1010102
;
395 case DRM_FORMAT_XBGR8888
:
396 sprctl
|= SP_FORMAT_RGBX8888
;
398 case DRM_FORMAT_ABGR8888
:
399 sprctl
|= SP_FORMAT_RGBA8888
;
403 * If we get here one of the upper layers failed to filter
404 * out the unsupported plane formats
411 * Enable gamma to match primary/cursor plane behaviour.
412 * FIXME should be user controllable via propertiesa.
414 sprctl
|= SP_GAMMA_ENABLE
;
416 if (obj
->tiling_mode
!= I915_TILING_NONE
)
419 /* Sizes are 0 based */
425 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
426 sprsurf_offset
= intel_compute_tile_offset(dev_priv
, &x
, &y
,
430 linear_offset
-= sprsurf_offset
;
432 if (plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
)) {
433 sprctl
|= SP_ROTATE_180
;
437 linear_offset
+= src_h
* fb
->pitches
[0] + src_w
* pixel_size
;
441 I915_WRITE(SPKEYMINVAL(pipe
, plane
), key
->min_value
);
442 I915_WRITE(SPKEYMAXVAL(pipe
, plane
), key
->max_value
);
443 I915_WRITE(SPKEYMSK(pipe
, plane
), key
->channel_mask
);
446 if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
447 sprctl
|= SP_SOURCE_KEY
;
449 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
)
450 chv_update_csc(intel_plane
, fb
->pixel_format
);
452 I915_WRITE(SPSTRIDE(pipe
, plane
), fb
->pitches
[0]);
453 I915_WRITE(SPPOS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
455 if (obj
->tiling_mode
!= I915_TILING_NONE
)
456 I915_WRITE(SPTILEOFF(pipe
, plane
), (y
<< 16) | x
);
458 I915_WRITE(SPLINOFF(pipe
, plane
), linear_offset
);
460 I915_WRITE(SPCONSTALPHA(pipe
, plane
), 0);
462 I915_WRITE(SPSIZE(pipe
, plane
), (crtc_h
<< 16) | crtc_w
);
463 I915_WRITE(SPCNTR(pipe
, plane
), sprctl
);
464 I915_WRITE(SPSURF(pipe
, plane
), i915_gem_obj_ggtt_offset(obj
) +
466 POSTING_READ(SPSURF(pipe
, plane
));
470 vlv_disable_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
)
472 struct drm_device
*dev
= dplane
->dev
;
473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
474 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
475 int pipe
= intel_plane
->pipe
;
476 int plane
= intel_plane
->plane
;
478 I915_WRITE(SPCNTR(pipe
, plane
), 0);
480 I915_WRITE(SPSURF(pipe
, plane
), 0);
481 POSTING_READ(SPSURF(pipe
, plane
));
485 ivb_update_plane(struct drm_plane
*plane
,
486 const struct intel_crtc_state
*crtc_state
,
487 const struct intel_plane_state
*plane_state
)
489 struct drm_device
*dev
= plane
->dev
;
490 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
491 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
492 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
493 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
494 enum pipe pipe
= intel_plane
->pipe
;
495 u32 sprctl
, sprscale
= 0;
496 unsigned long sprsurf_offset
, linear_offset
;
497 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
498 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
499 int crtc_x
= plane_state
->dst
.x1
;
500 int crtc_y
= plane_state
->dst
.y1
;
501 uint32_t crtc_w
= drm_rect_width(&plane_state
->dst
);
502 uint32_t crtc_h
= drm_rect_height(&plane_state
->dst
);
503 uint32_t x
= plane_state
->src
.x1
>> 16;
504 uint32_t y
= plane_state
->src
.y1
>> 16;
505 uint32_t src_w
= drm_rect_width(&plane_state
->src
) >> 16;
506 uint32_t src_h
= drm_rect_height(&plane_state
->src
) >> 16;
508 sprctl
= SPRITE_ENABLE
;
510 switch (fb
->pixel_format
) {
511 case DRM_FORMAT_XBGR8888
:
512 sprctl
|= SPRITE_FORMAT_RGBX888
| SPRITE_RGB_ORDER_RGBX
;
514 case DRM_FORMAT_XRGB8888
:
515 sprctl
|= SPRITE_FORMAT_RGBX888
;
517 case DRM_FORMAT_YUYV
:
518 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YUYV
;
520 case DRM_FORMAT_YVYU
:
521 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YVYU
;
523 case DRM_FORMAT_UYVY
:
524 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_UYVY
;
526 case DRM_FORMAT_VYUY
:
527 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_VYUY
;
534 * Enable gamma to match primary/cursor plane behaviour.
535 * FIXME should be user controllable via propertiesa.
537 sprctl
|= SPRITE_GAMMA_ENABLE
;
539 if (obj
->tiling_mode
!= I915_TILING_NONE
)
540 sprctl
|= SPRITE_TILED
;
542 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
543 sprctl
&= ~SPRITE_TRICKLE_FEED_DISABLE
;
545 sprctl
|= SPRITE_TRICKLE_FEED_DISABLE
;
547 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
548 sprctl
|= SPRITE_PIPE_CSC_ENABLE
;
550 /* Sizes are 0 based */
556 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
557 sprscale
= SPRITE_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
559 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
560 sprsurf_offset
= intel_compute_tile_offset(dev_priv
, &x
, &y
,
564 linear_offset
-= sprsurf_offset
;
566 if (plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
)) {
567 sprctl
|= SPRITE_ROTATE_180
;
569 /* HSW and BDW does this automagically in hardware */
570 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
573 linear_offset
+= src_h
* fb
->pitches
[0] +
579 I915_WRITE(SPRKEYVAL(pipe
), key
->min_value
);
580 I915_WRITE(SPRKEYMAX(pipe
), key
->max_value
);
581 I915_WRITE(SPRKEYMSK(pipe
), key
->channel_mask
);
584 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
585 sprctl
|= SPRITE_DEST_KEY
;
586 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
587 sprctl
|= SPRITE_SOURCE_KEY
;
589 I915_WRITE(SPRSTRIDE(pipe
), fb
->pitches
[0]);
590 I915_WRITE(SPRPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
592 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
594 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
595 I915_WRITE(SPROFFSET(pipe
), (y
<< 16) | x
);
596 else if (obj
->tiling_mode
!= I915_TILING_NONE
)
597 I915_WRITE(SPRTILEOFF(pipe
), (y
<< 16) | x
);
599 I915_WRITE(SPRLINOFF(pipe
), linear_offset
);
601 I915_WRITE(SPRSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
602 if (intel_plane
->can_scale
)
603 I915_WRITE(SPRSCALE(pipe
), sprscale
);
604 I915_WRITE(SPRCTL(pipe
), sprctl
);
605 I915_WRITE(SPRSURF(pipe
),
606 i915_gem_obj_ggtt_offset(obj
) + sprsurf_offset
);
607 POSTING_READ(SPRSURF(pipe
));
611 ivb_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
)
613 struct drm_device
*dev
= plane
->dev
;
614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
615 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
616 int pipe
= intel_plane
->pipe
;
618 I915_WRITE(SPRCTL(pipe
), 0);
619 /* Can't leave the scaler enabled... */
620 if (intel_plane
->can_scale
)
621 I915_WRITE(SPRSCALE(pipe
), 0);
623 I915_WRITE(SPRSURF(pipe
), 0);
624 POSTING_READ(SPRSURF(pipe
));
628 ilk_update_plane(struct drm_plane
*plane
,
629 const struct intel_crtc_state
*crtc_state
,
630 const struct intel_plane_state
*plane_state
)
632 struct drm_device
*dev
= plane
->dev
;
633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
634 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
635 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
636 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
637 int pipe
= intel_plane
->pipe
;
638 unsigned long dvssurf_offset
, linear_offset
;
639 u32 dvscntr
, dvsscale
;
640 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
641 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
642 int crtc_x
= plane_state
->dst
.x1
;
643 int crtc_y
= plane_state
->dst
.y1
;
644 uint32_t crtc_w
= drm_rect_width(&plane_state
->dst
);
645 uint32_t crtc_h
= drm_rect_height(&plane_state
->dst
);
646 uint32_t x
= plane_state
->src
.x1
>> 16;
647 uint32_t y
= plane_state
->src
.y1
>> 16;
648 uint32_t src_w
= drm_rect_width(&plane_state
->src
) >> 16;
649 uint32_t src_h
= drm_rect_height(&plane_state
->src
) >> 16;
651 dvscntr
= DVS_ENABLE
;
653 switch (fb
->pixel_format
) {
654 case DRM_FORMAT_XBGR8888
:
655 dvscntr
|= DVS_FORMAT_RGBX888
| DVS_RGB_ORDER_XBGR
;
657 case DRM_FORMAT_XRGB8888
:
658 dvscntr
|= DVS_FORMAT_RGBX888
;
660 case DRM_FORMAT_YUYV
:
661 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YUYV
;
663 case DRM_FORMAT_YVYU
:
664 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YVYU
;
666 case DRM_FORMAT_UYVY
:
667 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_UYVY
;
669 case DRM_FORMAT_VYUY
:
670 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_VYUY
;
677 * Enable gamma to match primary/cursor plane behaviour.
678 * FIXME should be user controllable via propertiesa.
680 dvscntr
|= DVS_GAMMA_ENABLE
;
682 if (obj
->tiling_mode
!= I915_TILING_NONE
)
683 dvscntr
|= DVS_TILED
;
686 dvscntr
|= DVS_TRICKLE_FEED_DISABLE
; /* must disable */
688 /* Sizes are 0 based */
695 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
696 dvsscale
= DVS_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
698 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
699 dvssurf_offset
= intel_compute_tile_offset(dev_priv
, &x
, &y
,
703 linear_offset
-= dvssurf_offset
;
705 if (plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
)) {
706 dvscntr
|= DVS_ROTATE_180
;
710 linear_offset
+= src_h
* fb
->pitches
[0] + src_w
* pixel_size
;
714 I915_WRITE(DVSKEYVAL(pipe
), key
->min_value
);
715 I915_WRITE(DVSKEYMAX(pipe
), key
->max_value
);
716 I915_WRITE(DVSKEYMSK(pipe
), key
->channel_mask
);
719 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
720 dvscntr
|= DVS_DEST_KEY
;
721 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
722 dvscntr
|= DVS_SOURCE_KEY
;
724 I915_WRITE(DVSSTRIDE(pipe
), fb
->pitches
[0]);
725 I915_WRITE(DVSPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
727 if (obj
->tiling_mode
!= I915_TILING_NONE
)
728 I915_WRITE(DVSTILEOFF(pipe
), (y
<< 16) | x
);
730 I915_WRITE(DVSLINOFF(pipe
), linear_offset
);
732 I915_WRITE(DVSSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
733 I915_WRITE(DVSSCALE(pipe
), dvsscale
);
734 I915_WRITE(DVSCNTR(pipe
), dvscntr
);
735 I915_WRITE(DVSSURF(pipe
),
736 i915_gem_obj_ggtt_offset(obj
) + dvssurf_offset
);
737 POSTING_READ(DVSSURF(pipe
));
741 ilk_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
)
743 struct drm_device
*dev
= plane
->dev
;
744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
745 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
746 int pipe
= intel_plane
->pipe
;
748 I915_WRITE(DVSCNTR(pipe
), 0);
749 /* Disable the scaler */
750 I915_WRITE(DVSSCALE(pipe
), 0);
752 I915_WRITE(DVSSURF(pipe
), 0);
753 POSTING_READ(DVSSURF(pipe
));
757 intel_check_sprite_plane(struct drm_plane
*plane
,
758 struct intel_crtc_state
*crtc_state
,
759 struct intel_plane_state
*state
)
761 struct drm_device
*dev
= plane
->dev
;
762 struct drm_crtc
*crtc
= state
->base
.crtc
;
763 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
764 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
765 struct drm_framebuffer
*fb
= state
->base
.fb
;
767 unsigned int crtc_w
, crtc_h
;
768 uint32_t src_x
, src_y
, src_w
, src_h
;
769 struct drm_rect
*src
= &state
->src
;
770 struct drm_rect
*dst
= &state
->dst
;
771 const struct drm_rect
*clip
= &state
->clip
;
773 int max_scale
, min_scale
;
778 state
->visible
= false;
782 /* Don't modify another pipe's plane */
783 if (intel_plane
->pipe
!= intel_crtc
->pipe
) {
784 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
788 /* FIXME check all gen limits */
789 if (fb
->width
< 3 || fb
->height
< 3 || fb
->pitches
[0] > 16384) {
790 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
794 /* setup can_scale, min_scale, max_scale */
795 if (INTEL_INFO(dev
)->gen
>= 9) {
796 /* use scaler when colorkey is not required */
797 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
800 max_scale
= skl_max_scale(intel_crtc
, crtc_state
);
803 min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
804 max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
807 can_scale
= intel_plane
->can_scale
;
808 max_scale
= intel_plane
->max_downscale
<< 16;
809 min_scale
= intel_plane
->can_scale
? 1 : (1 << 16);
813 * FIXME the following code does a bunch of fuzzy adjustments to the
814 * coordinates and sizes. We probably need some way to decide whether
815 * more strict checking should be done instead.
817 drm_rect_rotate(src
, fb
->width
<< 16, fb
->height
<< 16,
818 state
->base
.rotation
);
820 hscale
= drm_rect_calc_hscale_relaxed(src
, dst
, min_scale
, max_scale
);
823 vscale
= drm_rect_calc_vscale_relaxed(src
, dst
, min_scale
, max_scale
);
826 state
->visible
= drm_rect_clip_scaled(src
, dst
, clip
, hscale
, vscale
);
830 crtc_w
= drm_rect_width(dst
);
831 crtc_h
= drm_rect_height(dst
);
833 if (state
->visible
) {
834 /* check again in case clipping clamped the results */
835 hscale
= drm_rect_calc_hscale(src
, dst
, min_scale
, max_scale
);
837 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
838 drm_rect_debug_print("src: ", src
, true);
839 drm_rect_debug_print("dst: ", dst
, false);
844 vscale
= drm_rect_calc_vscale(src
, dst
, min_scale
, max_scale
);
846 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
847 drm_rect_debug_print("src: ", src
, true);
848 drm_rect_debug_print("dst: ", dst
, false);
853 /* Make the source viewport size an exact multiple of the scaling factors. */
854 drm_rect_adjust_size(src
,
855 drm_rect_width(dst
) * hscale
- drm_rect_width(src
),
856 drm_rect_height(dst
) * vscale
- drm_rect_height(src
));
858 drm_rect_rotate_inv(src
, fb
->width
<< 16, fb
->height
<< 16,
859 state
->base
.rotation
);
861 /* sanity check to make sure the src viewport wasn't enlarged */
862 WARN_ON(src
->x1
< (int) state
->base
.src_x
||
863 src
->y1
< (int) state
->base
.src_y
||
864 src
->x2
> (int) state
->base
.src_x
+ state
->base
.src_w
||
865 src
->y2
> (int) state
->base
.src_y
+ state
->base
.src_h
);
868 * Hardware doesn't handle subpixel coordinates.
869 * Adjust to (macro)pixel boundary, but be careful not to
870 * increase the source viewport size, because that could
871 * push the downscaling factor out of bounds.
873 src_x
= src
->x1
>> 16;
874 src_w
= drm_rect_width(src
) >> 16;
875 src_y
= src
->y1
>> 16;
876 src_h
= drm_rect_height(src
) >> 16;
878 if (format_is_yuv(fb
->pixel_format
)) {
883 * Must keep src and dst the
884 * same if we can't scale.
890 state
->visible
= false;
894 /* Check size restrictions when scaling */
895 if (state
->visible
&& (src_w
!= crtc_w
|| src_h
!= crtc_h
)) {
896 unsigned int width_bytes
;
900 /* FIXME interlacing min height is 6 */
902 if (crtc_w
< 3 || crtc_h
< 3)
903 state
->visible
= false;
905 if (src_w
< 3 || src_h
< 3)
906 state
->visible
= false;
908 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
909 width_bytes
= ((src_x
* pixel_size
) & 63) +
912 if (INTEL_INFO(dev
)->gen
< 9 && (src_w
> 2048 || src_h
> 2048 ||
913 width_bytes
> 4096 || fb
->pitches
[0] > 4096)) {
914 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
919 if (state
->visible
) {
920 src
->x1
= src_x
<< 16;
921 src
->x2
= (src_x
+ src_w
) << 16;
922 src
->y1
= src_y
<< 16;
923 src
->y2
= (src_y
+ src_h
) << 16;
927 dst
->x2
= crtc_x
+ crtc_w
;
929 dst
->y2
= crtc_y
+ crtc_h
;
934 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
935 struct drm_file
*file_priv
)
937 struct drm_intel_sprite_colorkey
*set
= data
;
938 struct drm_plane
*plane
;
939 struct drm_plane_state
*plane_state
;
940 struct drm_atomic_state
*state
;
941 struct drm_modeset_acquire_ctx ctx
;
944 /* Make sure we don't try to enable both src & dest simultaneously */
945 if ((set
->flags
& (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
)) == (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
))
948 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
949 set
->flags
& I915_SET_COLORKEY_DESTINATION
)
952 plane
= drm_plane_find(dev
, set
->plane_id
);
953 if (!plane
|| plane
->type
!= DRM_PLANE_TYPE_OVERLAY
)
956 drm_modeset_acquire_init(&ctx
, 0);
958 state
= drm_atomic_state_alloc(plane
->dev
);
963 state
->acquire_ctx
= &ctx
;
966 plane_state
= drm_atomic_get_plane_state(state
, plane
);
967 ret
= PTR_ERR_OR_ZERO(plane_state
);
969 to_intel_plane_state(plane_state
)->ckey
= *set
;
970 ret
= drm_atomic_commit(state
);
976 drm_atomic_state_clear(state
);
977 drm_modeset_backoff(&ctx
);
981 drm_atomic_state_free(state
);
984 drm_modeset_drop_locks(&ctx
);
985 drm_modeset_acquire_fini(&ctx
);
989 static const uint32_t ilk_plane_formats
[] = {
997 static const uint32_t snb_plane_formats
[] = {
1006 static const uint32_t vlv_plane_formats
[] = {
1008 DRM_FORMAT_ABGR8888
,
1009 DRM_FORMAT_ARGB8888
,
1010 DRM_FORMAT_XBGR8888
,
1011 DRM_FORMAT_XRGB8888
,
1012 DRM_FORMAT_XBGR2101010
,
1013 DRM_FORMAT_ABGR2101010
,
1020 static uint32_t skl_plane_formats
[] = {
1022 DRM_FORMAT_ABGR8888
,
1023 DRM_FORMAT_ARGB8888
,
1024 DRM_FORMAT_XBGR8888
,
1025 DRM_FORMAT_XRGB8888
,
1033 intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
)
1035 struct intel_plane
*intel_plane
;
1036 struct intel_plane_state
*state
;
1037 unsigned long possible_crtcs
;
1038 const uint32_t *plane_formats
;
1039 int num_plane_formats
;
1042 if (INTEL_INFO(dev
)->gen
< 5)
1045 intel_plane
= kzalloc(sizeof(*intel_plane
), GFP_KERNEL
);
1049 state
= intel_create_plane_state(&intel_plane
->base
);
1054 intel_plane
->base
.state
= &state
->base
;
1056 switch (INTEL_INFO(dev
)->gen
) {
1059 intel_plane
->can_scale
= true;
1060 intel_plane
->max_downscale
= 16;
1061 intel_plane
->update_plane
= ilk_update_plane
;
1062 intel_plane
->disable_plane
= ilk_disable_plane
;
1065 plane_formats
= snb_plane_formats
;
1066 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1068 plane_formats
= ilk_plane_formats
;
1069 num_plane_formats
= ARRAY_SIZE(ilk_plane_formats
);
1075 if (IS_IVYBRIDGE(dev
)) {
1076 intel_plane
->can_scale
= true;
1077 intel_plane
->max_downscale
= 2;
1079 intel_plane
->can_scale
= false;
1080 intel_plane
->max_downscale
= 1;
1083 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1084 intel_plane
->update_plane
= vlv_update_plane
;
1085 intel_plane
->disable_plane
= vlv_disable_plane
;
1087 plane_formats
= vlv_plane_formats
;
1088 num_plane_formats
= ARRAY_SIZE(vlv_plane_formats
);
1090 intel_plane
->update_plane
= ivb_update_plane
;
1091 intel_plane
->disable_plane
= ivb_disable_plane
;
1093 plane_formats
= snb_plane_formats
;
1094 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1098 intel_plane
->can_scale
= true;
1099 intel_plane
->update_plane
= skl_update_plane
;
1100 intel_plane
->disable_plane
= skl_disable_plane
;
1101 state
->scaler_id
= -1;
1103 plane_formats
= skl_plane_formats
;
1104 num_plane_formats
= ARRAY_SIZE(skl_plane_formats
);
1111 intel_plane
->pipe
= pipe
;
1112 intel_plane
->plane
= plane
;
1113 intel_plane
->frontbuffer_bit
= INTEL_FRONTBUFFER_SPRITE(pipe
, plane
);
1114 intel_plane
->check_plane
= intel_check_sprite_plane
;
1115 possible_crtcs
= (1 << pipe
);
1116 ret
= drm_universal_plane_init(dev
, &intel_plane
->base
, possible_crtcs
,
1118 plane_formats
, num_plane_formats
,
1119 DRM_PLANE_TYPE_OVERLAY
, NULL
);
1125 intel_create_rotation_property(dev
, intel_plane
);
1127 drm_plane_helper_add(&intel_plane
->base
, &intel_plane_helper_funcs
);