2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_plane_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
43 format_is_yuv(uint32_t format
)
56 static int usecs_to_scanlines(const struct drm_display_mode
*adjusted_mode
,
60 if (!adjusted_mode
->crtc_htotal
)
63 return DIV_ROUND_UP(usecs
* adjusted_mode
->crtc_clock
,
64 1000 * adjusted_mode
->crtc_htotal
);
68 * intel_pipe_update_start() - start update of a set of display registers
69 * @crtc: the crtc of which the registers are going to be updated
70 * @start_vbl_count: vblank counter return pointer used for error checking
72 * Mark the start of an update to pipe registers that should be updated
73 * atomically regarding vblank. If the next vblank will happens within
74 * the next 100 us, this function waits until the vblank passes.
76 * After a successful call to this function, interrupts will be disabled
77 * until a subsequent call to intel_pipe_update_end(). That is done to
78 * avoid random delays. The value written to @start_vbl_count should be
79 * supplied to intel_pipe_update_end() for error checking.
81 void intel_pipe_update_start(struct intel_crtc
*crtc
)
83 struct drm_device
*dev
= crtc
->base
.dev
;
84 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
85 enum pipe pipe
= crtc
->pipe
;
86 long timeout
= msecs_to_jiffies_timeout(1);
87 int scanline
, min
, max
, vblank_start
;
88 wait_queue_head_t
*wq
= drm_crtc_vblank_waitqueue(&crtc
->base
);
91 vblank_start
= adjusted_mode
->crtc_vblank_start
;
92 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
93 vblank_start
= DIV_ROUND_UP(vblank_start
, 2);
95 /* FIXME needs to be calibrated sensibly */
96 min
= vblank_start
- usecs_to_scanlines(adjusted_mode
, 100);
97 max
= vblank_start
- 1;
101 if (min
<= 0 || max
<= 0)
104 if (WARN_ON(drm_crtc_vblank_get(&crtc
->base
)))
107 crtc
->debug
.min_vbl
= min
;
108 crtc
->debug
.max_vbl
= max
;
109 trace_i915_pipe_update_start(crtc
);
113 * prepare_to_wait() has a memory barrier, which guarantees
114 * other CPUs can see the task state update by the time we
117 prepare_to_wait(wq
, &wait
, TASK_UNINTERRUPTIBLE
);
119 scanline
= intel_get_crtc_scanline(crtc
);
120 if (scanline
< min
|| scanline
> max
)
124 DRM_ERROR("Potential atomic update failure on pipe %c\n",
125 pipe_name(crtc
->pipe
));
131 timeout
= schedule_timeout(timeout
);
136 finish_wait(wq
, &wait
);
138 drm_crtc_vblank_put(&crtc
->base
);
140 crtc
->debug
.scanline_start
= scanline
;
141 crtc
->debug
.start_vbl_time
= ktime_get();
142 crtc
->debug
.start_vbl_count
=
143 dev
->driver
->get_vblank_counter(dev
, pipe
);
145 trace_i915_pipe_update_vblank_evaded(crtc
);
149 * intel_pipe_update_end() - end update of a set of display registers
150 * @crtc: the crtc of which the registers were updated
151 * @start_vbl_count: start vblank counter (used for error checking)
153 * Mark the end of an update started with intel_pipe_update_start(). This
154 * re-enables interrupts and verifies the update was actually completed
155 * before a vblank using the value of @start_vbl_count.
157 void intel_pipe_update_end(struct intel_crtc
*crtc
)
159 struct drm_device
*dev
= crtc
->base
.dev
;
160 enum pipe pipe
= crtc
->pipe
;
161 int scanline_end
= intel_get_crtc_scanline(crtc
);
162 u32 end_vbl_count
= dev
->driver
->get_vblank_counter(dev
, pipe
);
163 ktime_t end_vbl_time
= ktime_get();
165 trace_i915_pipe_update_end(crtc
, end_vbl_count
, scanline_end
);
169 if (crtc
->debug
.start_vbl_count
&&
170 crtc
->debug
.start_vbl_count
!= end_vbl_count
) {
171 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
172 pipe_name(pipe
), crtc
->debug
.start_vbl_count
,
174 ktime_us_delta(end_vbl_time
, crtc
->debug
.start_vbl_time
),
175 crtc
->debug
.min_vbl
, crtc
->debug
.max_vbl
,
176 crtc
->debug
.scanline_start
, scanline_end
);
181 skl_update_plane(struct drm_plane
*drm_plane
,
182 const struct intel_crtc_state
*crtc_state
,
183 const struct intel_plane_state
*plane_state
)
185 struct drm_device
*dev
= drm_plane
->dev
;
186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
187 struct intel_plane
*intel_plane
= to_intel_plane(drm_plane
);
188 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
189 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
190 const int pipe
= intel_plane
->pipe
;
191 const int plane
= intel_plane
->plane
+ 1;
192 u32 plane_ctl
, stride_div
, stride
;
193 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
195 u32 tile_height
, plane_offset
, plane_size
;
196 unsigned int rotation
= plane_state
->base
.rotation
;
197 int x_offset
, y_offset
;
198 int crtc_x
= plane_state
->dst
.x1
;
199 int crtc_y
= plane_state
->dst
.y1
;
200 uint32_t crtc_w
= drm_rect_width(&plane_state
->dst
);
201 uint32_t crtc_h
= drm_rect_height(&plane_state
->dst
);
202 uint32_t x
= plane_state
->src
.x1
>> 16;
203 uint32_t y
= plane_state
->src
.y1
>> 16;
204 uint32_t src_w
= drm_rect_width(&plane_state
->src
) >> 16;
205 uint32_t src_h
= drm_rect_height(&plane_state
->src
) >> 16;
206 const struct intel_scaler
*scaler
=
207 &crtc_state
->scaler_state
.scalers
[plane_state
->scaler_id
];
209 plane_ctl
= PLANE_CTL_ENABLE
|
210 PLANE_CTL_PIPE_GAMMA_ENABLE
|
211 PLANE_CTL_PIPE_CSC_ENABLE
;
213 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
214 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
216 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
218 stride_div
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
221 /* Sizes are 0 based */
228 I915_WRITE(PLANE_KEYVAL(pipe
, plane
), key
->min_value
);
229 I915_WRITE(PLANE_KEYMAX(pipe
, plane
), key
->max_value
);
230 I915_WRITE(PLANE_KEYMSK(pipe
, plane
), key
->channel_mask
);
233 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
234 plane_ctl
|= PLANE_CTL_KEY_ENABLE_DESTINATION
;
235 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
236 plane_ctl
|= PLANE_CTL_KEY_ENABLE_SOURCE
;
238 surf_addr
= intel_plane_obj_offset(intel_plane
, obj
, 0);
240 if (intel_rotation_90_or_270(rotation
)) {
241 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
243 /* stride: Surface height in tiles */
244 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], cpp
);
245 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
246 plane_size
= (src_w
<< 16) | src_h
;
247 x_offset
= stride
* tile_height
- y
- (src_h
+ 1);
250 stride
= fb
->pitches
[0] / stride_div
;
251 plane_size
= (src_h
<< 16) | src_w
;
255 plane_offset
= y_offset
<< 16 | x_offset
;
257 I915_WRITE(PLANE_OFFSET(pipe
, plane
), plane_offset
);
258 I915_WRITE(PLANE_STRIDE(pipe
, plane
), stride
);
259 I915_WRITE(PLANE_SIZE(pipe
, plane
), plane_size
);
261 /* program plane scaler */
262 if (plane_state
->scaler_id
>= 0) {
263 uint32_t ps_ctrl
= 0;
264 int scaler_id
= plane_state
->scaler_id
;
266 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane
,
267 PS_PLANE_SEL(plane
));
268 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(plane
) | scaler
->mode
;
269 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
270 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
271 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (crtc_x
<< 16) | crtc_y
);
272 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
),
273 ((crtc_w
+ 1) << 16)|(crtc_h
+ 1));
275 I915_WRITE(PLANE_POS(pipe
, plane
), 0);
277 I915_WRITE(PLANE_POS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
280 I915_WRITE(PLANE_CTL(pipe
, plane
), plane_ctl
);
281 I915_WRITE(PLANE_SURF(pipe
, plane
), surf_addr
);
282 POSTING_READ(PLANE_SURF(pipe
, plane
));
286 skl_disable_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
)
288 struct drm_device
*dev
= dplane
->dev
;
289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
290 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
291 const int pipe
= intel_plane
->pipe
;
292 const int plane
= intel_plane
->plane
+ 1;
294 I915_WRITE(PLANE_CTL(pipe
, plane
), 0);
296 I915_WRITE(PLANE_SURF(pipe
, plane
), 0);
297 POSTING_READ(PLANE_SURF(pipe
, plane
));
301 chv_update_csc(struct intel_plane
*intel_plane
, uint32_t format
)
303 struct drm_i915_private
*dev_priv
= intel_plane
->base
.dev
->dev_private
;
304 int plane
= intel_plane
->plane
;
306 /* Seems RGB data bypasses the CSC always */
307 if (!format_is_yuv(format
))
311 * BT.601 limited range YCbCr -> full range RGB
313 * |r| | 6537 4769 0| |cr |
314 * |g| = |-3330 4769 -1605| x |y-64|
315 * |b| | 0 4769 8263| |cb |
317 * Cb and Cr apparently come in as signed already, so no
318 * need for any offset. For Y we need to remove the offset.
320 I915_WRITE(SPCSCYGOFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
321 I915_WRITE(SPCSCCBOFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
322 I915_WRITE(SPCSCCROFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
324 I915_WRITE(SPCSCC01(plane
), SPCSC_C1(4769) | SPCSC_C0(6537));
325 I915_WRITE(SPCSCC23(plane
), SPCSC_C1(-3330) | SPCSC_C0(0));
326 I915_WRITE(SPCSCC45(plane
), SPCSC_C1(-1605) | SPCSC_C0(4769));
327 I915_WRITE(SPCSCC67(plane
), SPCSC_C1(4769) | SPCSC_C0(0));
328 I915_WRITE(SPCSCC8(plane
), SPCSC_C0(8263));
330 I915_WRITE(SPCSCYGICLAMP(plane
), SPCSC_IMAX(940) | SPCSC_IMIN(64));
331 I915_WRITE(SPCSCCBICLAMP(plane
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
332 I915_WRITE(SPCSCCRICLAMP(plane
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
334 I915_WRITE(SPCSCYGOCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
335 I915_WRITE(SPCSCCBOCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
336 I915_WRITE(SPCSCCROCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
340 vlv_update_plane(struct drm_plane
*dplane
,
341 const struct intel_crtc_state
*crtc_state
,
342 const struct intel_plane_state
*plane_state
)
344 struct drm_device
*dev
= dplane
->dev
;
345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
346 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
347 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
348 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
349 int pipe
= intel_plane
->pipe
;
350 int plane
= intel_plane
->plane
;
352 u32 sprsurf_offset
, linear_offset
;
353 unsigned int rotation
= dplane
->state
->rotation
;
354 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
355 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
356 int crtc_x
= plane_state
->dst
.x1
;
357 int crtc_y
= plane_state
->dst
.y1
;
358 uint32_t crtc_w
= drm_rect_width(&plane_state
->dst
);
359 uint32_t crtc_h
= drm_rect_height(&plane_state
->dst
);
360 uint32_t x
= plane_state
->src
.x1
>> 16;
361 uint32_t y
= plane_state
->src
.y1
>> 16;
362 uint32_t src_w
= drm_rect_width(&plane_state
->src
) >> 16;
363 uint32_t src_h
= drm_rect_height(&plane_state
->src
) >> 16;
367 switch (fb
->pixel_format
) {
368 case DRM_FORMAT_YUYV
:
369 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YUYV
;
371 case DRM_FORMAT_YVYU
:
372 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YVYU
;
374 case DRM_FORMAT_UYVY
:
375 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_UYVY
;
377 case DRM_FORMAT_VYUY
:
378 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_VYUY
;
380 case DRM_FORMAT_RGB565
:
381 sprctl
|= SP_FORMAT_BGR565
;
383 case DRM_FORMAT_XRGB8888
:
384 sprctl
|= SP_FORMAT_BGRX8888
;
386 case DRM_FORMAT_ARGB8888
:
387 sprctl
|= SP_FORMAT_BGRA8888
;
389 case DRM_FORMAT_XBGR2101010
:
390 sprctl
|= SP_FORMAT_RGBX1010102
;
392 case DRM_FORMAT_ABGR2101010
:
393 sprctl
|= SP_FORMAT_RGBA1010102
;
395 case DRM_FORMAT_XBGR8888
:
396 sprctl
|= SP_FORMAT_RGBX8888
;
398 case DRM_FORMAT_ABGR8888
:
399 sprctl
|= SP_FORMAT_RGBA8888
;
403 * If we get here one of the upper layers failed to filter
404 * out the unsupported plane formats
411 * Enable gamma to match primary/cursor plane behaviour.
412 * FIXME should be user controllable via propertiesa.
414 sprctl
|= SP_GAMMA_ENABLE
;
416 if (obj
->tiling_mode
!= I915_TILING_NONE
)
419 /* Sizes are 0 based */
425 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
426 sprsurf_offset
= intel_compute_tile_offset(&x
, &y
, fb
, 0,
427 fb
->pitches
[0], rotation
);
428 linear_offset
-= sprsurf_offset
;
430 if (rotation
== BIT(DRM_ROTATE_180
)) {
431 sprctl
|= SP_ROTATE_180
;
435 linear_offset
+= src_h
* fb
->pitches
[0] + src_w
* cpp
;
439 I915_WRITE(SPKEYMINVAL(pipe
, plane
), key
->min_value
);
440 I915_WRITE(SPKEYMAXVAL(pipe
, plane
), key
->max_value
);
441 I915_WRITE(SPKEYMSK(pipe
, plane
), key
->channel_mask
);
444 if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
445 sprctl
|= SP_SOURCE_KEY
;
447 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
)
448 chv_update_csc(intel_plane
, fb
->pixel_format
);
450 I915_WRITE(SPSTRIDE(pipe
, plane
), fb
->pitches
[0]);
451 I915_WRITE(SPPOS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
453 if (obj
->tiling_mode
!= I915_TILING_NONE
)
454 I915_WRITE(SPTILEOFF(pipe
, plane
), (y
<< 16) | x
);
456 I915_WRITE(SPLINOFF(pipe
, plane
), linear_offset
);
458 I915_WRITE(SPCONSTALPHA(pipe
, plane
), 0);
460 I915_WRITE(SPSIZE(pipe
, plane
), (crtc_h
<< 16) | crtc_w
);
461 I915_WRITE(SPCNTR(pipe
, plane
), sprctl
);
462 I915_WRITE(SPSURF(pipe
, plane
), i915_gem_obj_ggtt_offset(obj
) +
464 POSTING_READ(SPSURF(pipe
, plane
));
468 vlv_disable_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
)
470 struct drm_device
*dev
= dplane
->dev
;
471 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
472 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
473 int pipe
= intel_plane
->pipe
;
474 int plane
= intel_plane
->plane
;
476 I915_WRITE(SPCNTR(pipe
, plane
), 0);
478 I915_WRITE(SPSURF(pipe
, plane
), 0);
479 POSTING_READ(SPSURF(pipe
, plane
));
483 ivb_update_plane(struct drm_plane
*plane
,
484 const struct intel_crtc_state
*crtc_state
,
485 const struct intel_plane_state
*plane_state
)
487 struct drm_device
*dev
= plane
->dev
;
488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
489 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
490 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
491 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
492 enum pipe pipe
= intel_plane
->pipe
;
493 u32 sprctl
, sprscale
= 0;
494 u32 sprsurf_offset
, linear_offset
;
495 unsigned int rotation
= plane_state
->base
.rotation
;
496 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
497 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
498 int crtc_x
= plane_state
->dst
.x1
;
499 int crtc_y
= plane_state
->dst
.y1
;
500 uint32_t crtc_w
= drm_rect_width(&plane_state
->dst
);
501 uint32_t crtc_h
= drm_rect_height(&plane_state
->dst
);
502 uint32_t x
= plane_state
->src
.x1
>> 16;
503 uint32_t y
= plane_state
->src
.y1
>> 16;
504 uint32_t src_w
= drm_rect_width(&plane_state
->src
) >> 16;
505 uint32_t src_h
= drm_rect_height(&plane_state
->src
) >> 16;
507 sprctl
= SPRITE_ENABLE
;
509 switch (fb
->pixel_format
) {
510 case DRM_FORMAT_XBGR8888
:
511 sprctl
|= SPRITE_FORMAT_RGBX888
| SPRITE_RGB_ORDER_RGBX
;
513 case DRM_FORMAT_XRGB8888
:
514 sprctl
|= SPRITE_FORMAT_RGBX888
;
516 case DRM_FORMAT_YUYV
:
517 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YUYV
;
519 case DRM_FORMAT_YVYU
:
520 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YVYU
;
522 case DRM_FORMAT_UYVY
:
523 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_UYVY
;
525 case DRM_FORMAT_VYUY
:
526 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_VYUY
;
533 * Enable gamma to match primary/cursor plane behaviour.
534 * FIXME should be user controllable via propertiesa.
536 sprctl
|= SPRITE_GAMMA_ENABLE
;
538 if (obj
->tiling_mode
!= I915_TILING_NONE
)
539 sprctl
|= SPRITE_TILED
;
541 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
542 sprctl
&= ~SPRITE_TRICKLE_FEED_DISABLE
;
544 sprctl
|= SPRITE_TRICKLE_FEED_DISABLE
;
546 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
547 sprctl
|= SPRITE_PIPE_CSC_ENABLE
;
549 /* Sizes are 0 based */
555 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
556 sprscale
= SPRITE_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
558 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
559 sprsurf_offset
= intel_compute_tile_offset(&x
, &y
, fb
, 0,
560 fb
->pitches
[0], rotation
);
561 linear_offset
-= sprsurf_offset
;
563 if (rotation
== BIT(DRM_ROTATE_180
)) {
564 sprctl
|= SPRITE_ROTATE_180
;
566 /* HSW and BDW does this automagically in hardware */
567 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
570 linear_offset
+= src_h
* fb
->pitches
[0] + src_w
* cpp
;
575 I915_WRITE(SPRKEYVAL(pipe
), key
->min_value
);
576 I915_WRITE(SPRKEYMAX(pipe
), key
->max_value
);
577 I915_WRITE(SPRKEYMSK(pipe
), key
->channel_mask
);
580 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
581 sprctl
|= SPRITE_DEST_KEY
;
582 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
583 sprctl
|= SPRITE_SOURCE_KEY
;
585 I915_WRITE(SPRSTRIDE(pipe
), fb
->pitches
[0]);
586 I915_WRITE(SPRPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
588 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
590 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
591 I915_WRITE(SPROFFSET(pipe
), (y
<< 16) | x
);
592 else if (obj
->tiling_mode
!= I915_TILING_NONE
)
593 I915_WRITE(SPRTILEOFF(pipe
), (y
<< 16) | x
);
595 I915_WRITE(SPRLINOFF(pipe
), linear_offset
);
597 I915_WRITE(SPRSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
598 if (intel_plane
->can_scale
)
599 I915_WRITE(SPRSCALE(pipe
), sprscale
);
600 I915_WRITE(SPRCTL(pipe
), sprctl
);
601 I915_WRITE(SPRSURF(pipe
),
602 i915_gem_obj_ggtt_offset(obj
) + sprsurf_offset
);
603 POSTING_READ(SPRSURF(pipe
));
607 ivb_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
)
609 struct drm_device
*dev
= plane
->dev
;
610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
611 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
612 int pipe
= intel_plane
->pipe
;
614 I915_WRITE(SPRCTL(pipe
), 0);
615 /* Can't leave the scaler enabled... */
616 if (intel_plane
->can_scale
)
617 I915_WRITE(SPRSCALE(pipe
), 0);
619 I915_WRITE(SPRSURF(pipe
), 0);
620 POSTING_READ(SPRSURF(pipe
));
624 ilk_update_plane(struct drm_plane
*plane
,
625 const struct intel_crtc_state
*crtc_state
,
626 const struct intel_plane_state
*plane_state
)
628 struct drm_device
*dev
= plane
->dev
;
629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
630 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
631 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
632 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
633 int pipe
= intel_plane
->pipe
;
634 u32 dvscntr
, dvsscale
;
635 u32 dvssurf_offset
, linear_offset
;
636 unsigned int rotation
= plane_state
->base
.rotation
;
637 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
638 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
639 int crtc_x
= plane_state
->dst
.x1
;
640 int crtc_y
= plane_state
->dst
.y1
;
641 uint32_t crtc_w
= drm_rect_width(&plane_state
->dst
);
642 uint32_t crtc_h
= drm_rect_height(&plane_state
->dst
);
643 uint32_t x
= plane_state
->src
.x1
>> 16;
644 uint32_t y
= plane_state
->src
.y1
>> 16;
645 uint32_t src_w
= drm_rect_width(&plane_state
->src
) >> 16;
646 uint32_t src_h
= drm_rect_height(&plane_state
->src
) >> 16;
648 dvscntr
= DVS_ENABLE
;
650 switch (fb
->pixel_format
) {
651 case DRM_FORMAT_XBGR8888
:
652 dvscntr
|= DVS_FORMAT_RGBX888
| DVS_RGB_ORDER_XBGR
;
654 case DRM_FORMAT_XRGB8888
:
655 dvscntr
|= DVS_FORMAT_RGBX888
;
657 case DRM_FORMAT_YUYV
:
658 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YUYV
;
660 case DRM_FORMAT_YVYU
:
661 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YVYU
;
663 case DRM_FORMAT_UYVY
:
664 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_UYVY
;
666 case DRM_FORMAT_VYUY
:
667 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_VYUY
;
674 * Enable gamma to match primary/cursor plane behaviour.
675 * FIXME should be user controllable via propertiesa.
677 dvscntr
|= DVS_GAMMA_ENABLE
;
679 if (obj
->tiling_mode
!= I915_TILING_NONE
)
680 dvscntr
|= DVS_TILED
;
683 dvscntr
|= DVS_TRICKLE_FEED_DISABLE
; /* must disable */
685 /* Sizes are 0 based */
692 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
693 dvsscale
= DVS_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
695 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
696 dvssurf_offset
= intel_compute_tile_offset(&x
, &y
, fb
, 0,
697 fb
->pitches
[0], rotation
);
698 linear_offset
-= dvssurf_offset
;
700 if (rotation
== BIT(DRM_ROTATE_180
)) {
701 dvscntr
|= DVS_ROTATE_180
;
705 linear_offset
+= src_h
* fb
->pitches
[0] + src_w
* cpp
;
709 I915_WRITE(DVSKEYVAL(pipe
), key
->min_value
);
710 I915_WRITE(DVSKEYMAX(pipe
), key
->max_value
);
711 I915_WRITE(DVSKEYMSK(pipe
), key
->channel_mask
);
714 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
715 dvscntr
|= DVS_DEST_KEY
;
716 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
717 dvscntr
|= DVS_SOURCE_KEY
;
719 I915_WRITE(DVSSTRIDE(pipe
), fb
->pitches
[0]);
720 I915_WRITE(DVSPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
722 if (obj
->tiling_mode
!= I915_TILING_NONE
)
723 I915_WRITE(DVSTILEOFF(pipe
), (y
<< 16) | x
);
725 I915_WRITE(DVSLINOFF(pipe
), linear_offset
);
727 I915_WRITE(DVSSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
728 I915_WRITE(DVSSCALE(pipe
), dvsscale
);
729 I915_WRITE(DVSCNTR(pipe
), dvscntr
);
730 I915_WRITE(DVSSURF(pipe
),
731 i915_gem_obj_ggtt_offset(obj
) + dvssurf_offset
);
732 POSTING_READ(DVSSURF(pipe
));
736 ilk_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
)
738 struct drm_device
*dev
= plane
->dev
;
739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
740 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
741 int pipe
= intel_plane
->pipe
;
743 I915_WRITE(DVSCNTR(pipe
), 0);
744 /* Disable the scaler */
745 I915_WRITE(DVSSCALE(pipe
), 0);
747 I915_WRITE(DVSSURF(pipe
), 0);
748 POSTING_READ(DVSSURF(pipe
));
752 intel_check_sprite_plane(struct drm_plane
*plane
,
753 struct intel_crtc_state
*crtc_state
,
754 struct intel_plane_state
*state
)
756 struct drm_device
*dev
= plane
->dev
;
757 struct drm_crtc
*crtc
= state
->base
.crtc
;
758 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
759 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
760 struct drm_framebuffer
*fb
= state
->base
.fb
;
762 unsigned int crtc_w
, crtc_h
;
763 uint32_t src_x
, src_y
, src_w
, src_h
;
764 struct drm_rect
*src
= &state
->src
;
765 struct drm_rect
*dst
= &state
->dst
;
766 const struct drm_rect
*clip
= &state
->clip
;
768 int max_scale
, min_scale
;
772 state
->visible
= false;
776 /* Don't modify another pipe's plane */
777 if (intel_plane
->pipe
!= intel_crtc
->pipe
) {
778 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
782 /* FIXME check all gen limits */
783 if (fb
->width
< 3 || fb
->height
< 3 || fb
->pitches
[0] > 16384) {
784 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
788 /* setup can_scale, min_scale, max_scale */
789 if (INTEL_INFO(dev
)->gen
>= 9) {
790 /* use scaler when colorkey is not required */
791 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
794 max_scale
= skl_max_scale(intel_crtc
, crtc_state
);
797 min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
798 max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
801 can_scale
= intel_plane
->can_scale
;
802 max_scale
= intel_plane
->max_downscale
<< 16;
803 min_scale
= intel_plane
->can_scale
? 1 : (1 << 16);
807 * FIXME the following code does a bunch of fuzzy adjustments to the
808 * coordinates and sizes. We probably need some way to decide whether
809 * more strict checking should be done instead.
811 drm_rect_rotate(src
, fb
->width
<< 16, fb
->height
<< 16,
812 state
->base
.rotation
);
814 hscale
= drm_rect_calc_hscale_relaxed(src
, dst
, min_scale
, max_scale
);
817 vscale
= drm_rect_calc_vscale_relaxed(src
, dst
, min_scale
, max_scale
);
820 state
->visible
= drm_rect_clip_scaled(src
, dst
, clip
, hscale
, vscale
);
824 crtc_w
= drm_rect_width(dst
);
825 crtc_h
= drm_rect_height(dst
);
827 if (state
->visible
) {
828 /* check again in case clipping clamped the results */
829 hscale
= drm_rect_calc_hscale(src
, dst
, min_scale
, max_scale
);
831 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
832 drm_rect_debug_print("src: ", src
, true);
833 drm_rect_debug_print("dst: ", dst
, false);
838 vscale
= drm_rect_calc_vscale(src
, dst
, min_scale
, max_scale
);
840 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
841 drm_rect_debug_print("src: ", src
, true);
842 drm_rect_debug_print("dst: ", dst
, false);
847 /* Make the source viewport size an exact multiple of the scaling factors. */
848 drm_rect_adjust_size(src
,
849 drm_rect_width(dst
) * hscale
- drm_rect_width(src
),
850 drm_rect_height(dst
) * vscale
- drm_rect_height(src
));
852 drm_rect_rotate_inv(src
, fb
->width
<< 16, fb
->height
<< 16,
853 state
->base
.rotation
);
855 /* sanity check to make sure the src viewport wasn't enlarged */
856 WARN_ON(src
->x1
< (int) state
->base
.src_x
||
857 src
->y1
< (int) state
->base
.src_y
||
858 src
->x2
> (int) state
->base
.src_x
+ state
->base
.src_w
||
859 src
->y2
> (int) state
->base
.src_y
+ state
->base
.src_h
);
862 * Hardware doesn't handle subpixel coordinates.
863 * Adjust to (macro)pixel boundary, but be careful not to
864 * increase the source viewport size, because that could
865 * push the downscaling factor out of bounds.
867 src_x
= src
->x1
>> 16;
868 src_w
= drm_rect_width(src
) >> 16;
869 src_y
= src
->y1
>> 16;
870 src_h
= drm_rect_height(src
) >> 16;
872 if (format_is_yuv(fb
->pixel_format
)) {
877 * Must keep src and dst the
878 * same if we can't scale.
884 state
->visible
= false;
888 /* Check size restrictions when scaling */
889 if (state
->visible
&& (src_w
!= crtc_w
|| src_h
!= crtc_h
)) {
890 unsigned int width_bytes
;
891 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
895 /* FIXME interlacing min height is 6 */
897 if (crtc_w
< 3 || crtc_h
< 3)
898 state
->visible
= false;
900 if (src_w
< 3 || src_h
< 3)
901 state
->visible
= false;
903 width_bytes
= ((src_x
* cpp
) & 63) + src_w
* cpp
;
905 if (INTEL_INFO(dev
)->gen
< 9 && (src_w
> 2048 || src_h
> 2048 ||
906 width_bytes
> 4096 || fb
->pitches
[0] > 4096)) {
907 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
912 if (state
->visible
) {
913 src
->x1
= src_x
<< 16;
914 src
->x2
= (src_x
+ src_w
) << 16;
915 src
->y1
= src_y
<< 16;
916 src
->y2
= (src_y
+ src_h
) << 16;
920 dst
->x2
= crtc_x
+ crtc_w
;
922 dst
->y2
= crtc_y
+ crtc_h
;
927 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
928 struct drm_file
*file_priv
)
930 struct drm_intel_sprite_colorkey
*set
= data
;
931 struct drm_plane
*plane
;
932 struct drm_plane_state
*plane_state
;
933 struct drm_atomic_state
*state
;
934 struct drm_modeset_acquire_ctx ctx
;
937 /* Make sure we don't try to enable both src & dest simultaneously */
938 if ((set
->flags
& (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
)) == (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
))
941 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
942 set
->flags
& I915_SET_COLORKEY_DESTINATION
)
945 plane
= drm_plane_find(dev
, set
->plane_id
);
946 if (!plane
|| plane
->type
!= DRM_PLANE_TYPE_OVERLAY
)
949 drm_modeset_acquire_init(&ctx
, 0);
951 state
= drm_atomic_state_alloc(plane
->dev
);
956 state
->acquire_ctx
= &ctx
;
959 plane_state
= drm_atomic_get_plane_state(state
, plane
);
960 ret
= PTR_ERR_OR_ZERO(plane_state
);
962 to_intel_plane_state(plane_state
)->ckey
= *set
;
963 ret
= drm_atomic_commit(state
);
969 drm_atomic_state_clear(state
);
970 drm_modeset_backoff(&ctx
);
974 drm_atomic_state_free(state
);
977 drm_modeset_drop_locks(&ctx
);
978 drm_modeset_acquire_fini(&ctx
);
982 static const uint32_t ilk_plane_formats
[] = {
990 static const uint32_t snb_plane_formats
[] = {
999 static const uint32_t vlv_plane_formats
[] = {
1001 DRM_FORMAT_ABGR8888
,
1002 DRM_FORMAT_ARGB8888
,
1003 DRM_FORMAT_XBGR8888
,
1004 DRM_FORMAT_XRGB8888
,
1005 DRM_FORMAT_XBGR2101010
,
1006 DRM_FORMAT_ABGR2101010
,
1013 static uint32_t skl_plane_formats
[] = {
1015 DRM_FORMAT_ABGR8888
,
1016 DRM_FORMAT_ARGB8888
,
1017 DRM_FORMAT_XBGR8888
,
1018 DRM_FORMAT_XRGB8888
,
1026 intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
)
1028 struct intel_plane
*intel_plane
= NULL
;
1029 struct intel_plane_state
*state
= NULL
;
1030 unsigned long possible_crtcs
;
1031 const uint32_t *plane_formats
;
1032 int num_plane_formats
;
1035 if (INTEL_INFO(dev
)->gen
< 5)
1038 intel_plane
= kzalloc(sizeof(*intel_plane
), GFP_KERNEL
);
1044 state
= intel_create_plane_state(&intel_plane
->base
);
1049 intel_plane
->base
.state
= &state
->base
;
1051 switch (INTEL_INFO(dev
)->gen
) {
1054 intel_plane
->can_scale
= true;
1055 intel_plane
->max_downscale
= 16;
1056 intel_plane
->update_plane
= ilk_update_plane
;
1057 intel_plane
->disable_plane
= ilk_disable_plane
;
1060 plane_formats
= snb_plane_formats
;
1061 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1063 plane_formats
= ilk_plane_formats
;
1064 num_plane_formats
= ARRAY_SIZE(ilk_plane_formats
);
1070 if (IS_IVYBRIDGE(dev
)) {
1071 intel_plane
->can_scale
= true;
1072 intel_plane
->max_downscale
= 2;
1074 intel_plane
->can_scale
= false;
1075 intel_plane
->max_downscale
= 1;
1078 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1079 intel_plane
->update_plane
= vlv_update_plane
;
1080 intel_plane
->disable_plane
= vlv_disable_plane
;
1082 plane_formats
= vlv_plane_formats
;
1083 num_plane_formats
= ARRAY_SIZE(vlv_plane_formats
);
1085 intel_plane
->update_plane
= ivb_update_plane
;
1086 intel_plane
->disable_plane
= ivb_disable_plane
;
1088 plane_formats
= snb_plane_formats
;
1089 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1093 intel_plane
->can_scale
= true;
1094 intel_plane
->update_plane
= skl_update_plane
;
1095 intel_plane
->disable_plane
= skl_disable_plane
;
1096 state
->scaler_id
= -1;
1098 plane_formats
= skl_plane_formats
;
1099 num_plane_formats
= ARRAY_SIZE(skl_plane_formats
);
1102 MISSING_CASE(INTEL_INFO(dev
)->gen
);
1107 intel_plane
->pipe
= pipe
;
1108 intel_plane
->plane
= plane
;
1109 intel_plane
->frontbuffer_bit
= INTEL_FRONTBUFFER_SPRITE(pipe
, plane
);
1110 intel_plane
->check_plane
= intel_check_sprite_plane
;
1112 possible_crtcs
= (1 << pipe
);
1114 ret
= drm_universal_plane_init(dev
, &intel_plane
->base
, possible_crtcs
,
1116 plane_formats
, num_plane_formats
,
1117 DRM_PLANE_TYPE_OVERLAY
, NULL
);
1121 intel_create_rotation_property(dev
, intel_plane
);
1123 drm_plane_helper_add(&intel_plane
->base
, &intel_plane_helper_funcs
);