projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: cleanup pipe_update trace functions with new crtc debug info v3
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sprite.c
1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
32 #include <drm/drmP.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_plane_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include "i915_drv.h"
41
42 static bool
43 format_is_yuv(uint32_t format)
44 {
45 switch (format) {
46 case DRM_FORMAT_YUYV:
47 case DRM_FORMAT_UYVY:
48 case DRM_FORMAT_VYUY:
49 case DRM_FORMAT_YVYU:
50 return true;
51 default:
52 return false;
53 }
54 }
55
56 static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
57 {
58 /* paranoia */
59 if (!mode->crtc_htotal)
60 return 1;
61
62 return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
63 }
64
65 /**
66 * intel_pipe_update_start() - start update of a set of display registers
67 * @crtc: the crtc of which the registers are going to be updated
68 * @start_vbl_count: vblank counter return pointer used for error checking
69 *
70 * Mark the start of an update to pipe registers that should be updated
71 * atomically regarding vblank. If the next vblank will happens within
72 * the next 100 us, this function waits until the vblank passes.
73 *
74 * After a successful call to this function, interrupts will be disabled
75 * until a subsequent call to intel_pipe_update_end(). That is done to
76 * avoid random delays. The value written to @start_vbl_count should be
77 * supplied to intel_pipe_update_end() for error checking.
78 */
79 void intel_pipe_update_start(struct intel_crtc *crtc)
80 {
81 struct drm_device *dev = crtc->base.dev;
82 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
83 enum pipe pipe = crtc->pipe;
84 long timeout = msecs_to_jiffies_timeout(1);
85 int scanline, min, max, vblank_start;
86 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
87 DEFINE_WAIT(wait);
88
89 vblank_start = mode->crtc_vblank_start;
90 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
91 vblank_start = DIV_ROUND_UP(vblank_start, 2);
92
93 /* FIXME needs to be calibrated sensibly */
94 min = vblank_start - usecs_to_scanlines(mode, 100);
95 max = vblank_start - 1;
96
97 local_irq_disable();
98
99 if (min <= 0 || max <= 0)
100 return;
101
102 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
103 return;
104
105 crtc->debug.min_vbl = min;
106 crtc->debug.max_vbl = max;
107 trace_i915_pipe_update_start(crtc);
108
109 for (;;) {
110 /*
111 * prepare_to_wait() has a memory barrier, which guarantees
112 * other CPUs can see the task state update by the time we
113 * read the scanline.
114 */
115 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
116
117 scanline = intel_get_crtc_scanline(crtc);
118 if (scanline < min || scanline > max)
119 break;
120
121 if (timeout <= 0) {
122 DRM_ERROR("Potential atomic update failure on pipe %c\n",
123 pipe_name(crtc->pipe));
124 break;
125 }
126
127 local_irq_enable();
128
129 timeout = schedule_timeout(timeout);
130
131 local_irq_disable();
132 }
133
134 finish_wait(wq, &wait);
135
136 drm_crtc_vblank_put(&crtc->base);
137
138 crtc->debug.scanline_start = scanline;
139 crtc->debug.start_vbl_time = ktime_get();
140 crtc->debug.start_vbl_count =
141 dev->driver->get_vblank_counter(dev, pipe);
142
143 trace_i915_pipe_update_vblank_evaded(crtc);
144 }
145
146 /**
147 * intel_pipe_update_end() - end update of a set of display registers
148 * @crtc: the crtc of which the registers were updated
149 * @start_vbl_count: start vblank counter (used for error checking)
150 *
151 * Mark the end of an update started with intel_pipe_update_start(). This
152 * re-enables interrupts and verifies the update was actually completed
153 * before a vblank using the value of @start_vbl_count.
154 */
155 void intel_pipe_update_end(struct intel_crtc *crtc)
156 {
157 struct drm_device *dev = crtc->base.dev;
158 enum pipe pipe = crtc->pipe;
159 int scanline_end = intel_get_crtc_scanline(crtc);
160 u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
161 ktime_t end_vbl_time = ktime_get();
162
163 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
164
165 local_irq_enable();
166
167 if (crtc->debug.start_vbl_count &&
168 crtc->debug.start_vbl_count != end_vbl_count) {
169 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
170 pipe_name(pipe), crtc->debug.start_vbl_count,
171 end_vbl_count,
172 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
173 crtc->debug.min_vbl, crtc->debug.max_vbl,
174 crtc->debug.scanline_start, scanline_end);
175 }
176 }
177
178 static void
179 skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
180 struct drm_framebuffer *fb,
181 int crtc_x, int crtc_y,
182 unsigned int crtc_w, unsigned int crtc_h,
183 uint32_t x, uint32_t y,
184 uint32_t src_w, uint32_t src_h)
185 {
186 struct drm_device *dev = drm_plane->dev;
187 struct drm_i915_private *dev_priv = dev->dev_private;
188 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
189 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
190 const int pipe = intel_plane->pipe;
191 const int plane = intel_plane->plane + 1;
192 u32 plane_ctl, stride_div, stride;
193 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
194 const struct drm_intel_sprite_colorkey *key =
195 &to_intel_plane_state(drm_plane->state)->ckey;
196 unsigned long surf_addr;
197 u32 tile_height, plane_offset, plane_size;
198 unsigned int rotation;
199 int x_offset, y_offset;
200 struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
201 int scaler_id;
202
203 plane_ctl = PLANE_CTL_ENABLE |
204 PLANE_CTL_PIPE_CSC_ENABLE;
205
206 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
207 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
208
209 rotation = drm_plane->state->rotation;
210 plane_ctl |= skl_plane_ctl_rotation(rotation);
211
212 intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
213 pixel_size, true,
214 src_w != crtc_w || src_h != crtc_h);
215
216 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
217 fb->pixel_format);
218
219 scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id;
220
221 /* Sizes are 0 based */
222 src_w--;
223 src_h--;
224 crtc_w--;
225 crtc_h--;
226
227 if (key->flags) {
228 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
229 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
230 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
231 }
232
233 if (key->flags & I915_SET_COLORKEY_DESTINATION)
234 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
235 else if (key->flags & I915_SET_COLORKEY_SOURCE)
236 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
237
238 surf_addr = intel_plane_obj_offset(intel_plane, obj);
239
240 if (intel_rotation_90_or_270(rotation)) {
241 /* stride: Surface height in tiles */
242 tile_height = intel_tile_height(dev, fb->pixel_format,
243 fb->modifier[0]);
244 stride = DIV_ROUND_UP(fb->height, tile_height);
245 plane_size = (src_w << 16) | src_h;
246 x_offset = stride * tile_height - y - (src_h + 1);
247 y_offset = x;
248 } else {
249 stride = fb->pitches[0] / stride_div;
250 plane_size = (src_h << 16) | src_w;
251 x_offset = x;
252 y_offset = y;
253 }
254 plane_offset = y_offset << 16 | x_offset;
255
256 I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
257 I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
258 I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
259
260 /* program plane scaler */
261 if (scaler_id >= 0) {
262 uint32_t ps_ctrl = 0;
263
264 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
265 PS_PLANE_SEL(plane));
266 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
267 crtc_state->scaler_state.scalers[scaler_id].mode;
268 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
269 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
270 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
271 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
272 ((crtc_w + 1) << 16)|(crtc_h + 1));
273
274 I915_WRITE(PLANE_POS(pipe, plane), 0);
275 } else {
276 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
277 }
278
279 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
280 I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
281 POSTING_READ(PLANE_SURF(pipe, plane));
282 }
283
284 static void
285 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
286 {
287 struct drm_device *dev = dplane->dev;
288 struct drm_i915_private *dev_priv = dev->dev_private;
289 struct intel_plane *intel_plane = to_intel_plane(dplane);
290 const int pipe = intel_plane->pipe;
291 const int plane = intel_plane->plane + 1;
292
293 I915_WRITE(PLANE_CTL(pipe, plane), 0);
294
295 I915_WRITE(PLANE_SURF(pipe, plane), 0);
296 POSTING_READ(PLANE_SURF(pipe, plane));
297
298 intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
299 }
300
301 static void
302 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
303 {
304 struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
305 int plane = intel_plane->plane;
306
307 /* Seems RGB data bypasses the CSC always */
308 if (!format_is_yuv(format))
309 return;
310
311 /*
312 * BT.601 limited range YCbCr -> full range RGB
313 *
314 * |r| | 6537 4769 0| |cr |
315 * |g| = |-3330 4769 -1605| x |y-64|
316 * |b| | 0 4769 8263| |cb |
317 *
318 * Cb and Cr apparently come in as signed already, so no
319 * need for any offset. For Y we need to remove the offset.
320 */
321 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
322 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
323 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
324
325 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
326 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
327 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
328 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
329 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
330
331 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
332 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
333 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
334
335 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
336 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
337 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
338 }
339
340 static void
341 vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
342 struct drm_framebuffer *fb,
343 int crtc_x, int crtc_y,
344 unsigned int crtc_w, unsigned int crtc_h,
345 uint32_t x, uint32_t y,
346 uint32_t src_w, uint32_t src_h)
347 {
348 struct drm_device *dev = dplane->dev;
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 struct intel_plane *intel_plane = to_intel_plane(dplane);
351 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
352 int pipe = intel_plane->pipe;
353 int plane = intel_plane->plane;
354 u32 sprctl;
355 unsigned long sprsurf_offset, linear_offset;
356 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
357 const struct drm_intel_sprite_colorkey *key =
358 &to_intel_plane_state(dplane->state)->ckey;
359
360 sprctl = SP_ENABLE;
361
362 switch (fb->pixel_format) {
363 case DRM_FORMAT_YUYV:
364 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
365 break;
366 case DRM_FORMAT_YVYU:
367 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
368 break;
369 case DRM_FORMAT_UYVY:
370 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
371 break;
372 case DRM_FORMAT_VYUY:
373 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
374 break;
375 case DRM_FORMAT_RGB565:
376 sprctl |= SP_FORMAT_BGR565;
377 break;
378 case DRM_FORMAT_XRGB8888:
379 sprctl |= SP_FORMAT_BGRX8888;
380 break;
381 case DRM_FORMAT_ARGB8888:
382 sprctl |= SP_FORMAT_BGRA8888;
383 break;
384 case DRM_FORMAT_XBGR2101010:
385 sprctl |= SP_FORMAT_RGBX1010102;
386 break;
387 case DRM_FORMAT_ABGR2101010:
388 sprctl |= SP_FORMAT_RGBA1010102;
389 break;
390 case DRM_FORMAT_XBGR8888:
391 sprctl |= SP_FORMAT_RGBX8888;
392 break;
393 case DRM_FORMAT_ABGR8888:
394 sprctl |= SP_FORMAT_RGBA8888;
395 break;
396 default:
397 /*
398 * If we get here one of the upper layers failed to filter
399 * out the unsupported plane formats
400 */
401 BUG();
402 break;
403 }
404
405 /*
406 * Enable gamma to match primary/cursor plane behaviour.
407 * FIXME should be user controllable via propertiesa.
408 */
409 sprctl |= SP_GAMMA_ENABLE;
410
411 if (obj->tiling_mode != I915_TILING_NONE)
412 sprctl |= SP_TILED;
413
414 /* Sizes are 0 based */
415 src_w--;
416 src_h--;
417 crtc_w--;
418 crtc_h--;
419
420 linear_offset = y * fb->pitches[0] + x * pixel_size;
421 sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
422 &x, &y,
423 obj->tiling_mode,
424 pixel_size,
425 fb->pitches[0]);
426 linear_offset -= sprsurf_offset;
427
428 if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
429 sprctl |= SP_ROTATE_180;
430
431 x += src_w;
432 y += src_h;
433 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
434 }
435
436 if (key->flags) {
437 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
438 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
439 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
440 }
441
442 if (key->flags & I915_SET_COLORKEY_SOURCE)
443 sprctl |= SP_SOURCE_KEY;
444
445 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
446 chv_update_csc(intel_plane, fb->pixel_format);
447
448 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
449 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
450
451 if (obj->tiling_mode != I915_TILING_NONE)
452 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
453 else
454 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
455
456 I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
457
458 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
459 I915_WRITE(SPCNTR(pipe, plane), sprctl);
460 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
461 sprsurf_offset);
462 POSTING_READ(SPSURF(pipe, plane));
463 }
464
465 static void
466 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
467 {
468 struct drm_device *dev = dplane->dev;
469 struct drm_i915_private *dev_priv = dev->dev_private;
470 struct intel_plane *intel_plane = to_intel_plane(dplane);
471 int pipe = intel_plane->pipe;
472 int plane = intel_plane->plane;
473
474 I915_WRITE(SPCNTR(pipe, plane), 0);
475
476 I915_WRITE(SPSURF(pipe, plane), 0);
477 POSTING_READ(SPSURF(pipe, plane));
478 }
479
480 static void
481 ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
482 struct drm_framebuffer *fb,
483 int crtc_x, int crtc_y,
484 unsigned int crtc_w, unsigned int crtc_h,
485 uint32_t x, uint32_t y,
486 uint32_t src_w, uint32_t src_h)
487 {
488 struct drm_device *dev = plane->dev;
489 struct drm_i915_private *dev_priv = dev->dev_private;
490 struct intel_plane *intel_plane = to_intel_plane(plane);
491 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
492 enum pipe pipe = intel_plane->pipe;
493 u32 sprctl, sprscale = 0;
494 unsigned long sprsurf_offset, linear_offset;
495 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
496 const struct drm_intel_sprite_colorkey *key =
497 &to_intel_plane_state(plane->state)->ckey;
498
499 sprctl = SPRITE_ENABLE;
500
501 switch (fb->pixel_format) {
502 case DRM_FORMAT_XBGR8888:
503 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
504 break;
505 case DRM_FORMAT_XRGB8888:
506 sprctl |= SPRITE_FORMAT_RGBX888;
507 break;
508 case DRM_FORMAT_YUYV:
509 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
510 break;
511 case DRM_FORMAT_YVYU:
512 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
513 break;
514 case DRM_FORMAT_UYVY:
515 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
516 break;
517 case DRM_FORMAT_VYUY:
518 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
519 break;
520 default:
521 BUG();
522 }
523
524 /*
525 * Enable gamma to match primary/cursor plane behaviour.
526 * FIXME should be user controllable via propertiesa.
527 */
528 sprctl |= SPRITE_GAMMA_ENABLE;
529
530 if (obj->tiling_mode != I915_TILING_NONE)
531 sprctl |= SPRITE_TILED;
532
533 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
534 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
535 else
536 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
537
538 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
539 sprctl |= SPRITE_PIPE_CSC_ENABLE;
540
541 intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
542 true,
543 src_w != crtc_w || src_h != crtc_h);
544
545 /* Sizes are 0 based */
546 src_w--;
547 src_h--;
548 crtc_w--;
549 crtc_h--;
550
551 if (crtc_w != src_w || crtc_h != src_h)
552 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
553
554 linear_offset = y * fb->pitches[0] + x * pixel_size;
555 sprsurf_offset =
556 intel_gen4_compute_page_offset(dev_priv,
557 &x, &y, obj->tiling_mode,
558 pixel_size, fb->pitches[0]);
559 linear_offset -= sprsurf_offset;
560
561 if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
562 sprctl |= SPRITE_ROTATE_180;
563
564 /* HSW and BDW does this automagically in hardware */
565 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
566 x += src_w;
567 y += src_h;
568 linear_offset += src_h * fb->pitches[0] +
569 src_w * pixel_size;
570 }
571 }
572
573 if (key->flags) {
574 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
575 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
576 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
577 }
578
579 if (key->flags & I915_SET_COLORKEY_DESTINATION)
580 sprctl |= SPRITE_DEST_KEY;
581 else if (key->flags & I915_SET_COLORKEY_SOURCE)
582 sprctl |= SPRITE_SOURCE_KEY;
583
584 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
585 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
586
587 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
588 * register */
589 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
590 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
591 else if (obj->tiling_mode != I915_TILING_NONE)
592 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
593 else
594 I915_WRITE(SPRLINOFF(pipe), linear_offset);
595
596 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
597 if (intel_plane->can_scale)
598 I915_WRITE(SPRSCALE(pipe), sprscale);
599 I915_WRITE(SPRCTL(pipe), sprctl);
600 I915_WRITE(SPRSURF(pipe),
601 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
602 POSTING_READ(SPRSURF(pipe));
603 }
604
605 static void
606 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
607 {
608 struct drm_device *dev = plane->dev;
609 struct drm_i915_private *dev_priv = dev->dev_private;
610 struct intel_plane *intel_plane = to_intel_plane(plane);
611 int pipe = intel_plane->pipe;
612
613 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
614 /* Can't leave the scaler enabled... */
615 if (intel_plane->can_scale)
616 I915_WRITE(SPRSCALE(pipe), 0);
617
618 I915_WRITE(SPRSURF(pipe), 0);
619 POSTING_READ(SPRSURF(pipe));
620 }
621
622 static void
623 ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
624 struct drm_framebuffer *fb,
625 int crtc_x, int crtc_y,
626 unsigned int crtc_w, unsigned int crtc_h,
627 uint32_t x, uint32_t y,
628 uint32_t src_w, uint32_t src_h)
629 {
630 struct drm_device *dev = plane->dev;
631 struct drm_i915_private *dev_priv = dev->dev_private;
632 struct intel_plane *intel_plane = to_intel_plane(plane);
633 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
634 int pipe = intel_plane->pipe;
635 unsigned long dvssurf_offset, linear_offset;
636 u32 dvscntr, dvsscale;
637 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
638 const struct drm_intel_sprite_colorkey *key =
639 &to_intel_plane_state(plane->state)->ckey;
640
641 dvscntr = DVS_ENABLE;
642
643 switch (fb->pixel_format) {
644 case DRM_FORMAT_XBGR8888:
645 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
646 break;
647 case DRM_FORMAT_XRGB8888:
648 dvscntr |= DVS_FORMAT_RGBX888;
649 break;
650 case DRM_FORMAT_YUYV:
651 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
652 break;
653 case DRM_FORMAT_YVYU:
654 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
655 break;
656 case DRM_FORMAT_UYVY:
657 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
658 break;
659 case DRM_FORMAT_VYUY:
660 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
661 break;
662 default:
663 BUG();
664 }
665
666 /*
667 * Enable gamma to match primary/cursor plane behaviour.
668 * FIXME should be user controllable via propertiesa.
669 */
670 dvscntr |= DVS_GAMMA_ENABLE;
671
672 if (obj->tiling_mode != I915_TILING_NONE)
673 dvscntr |= DVS_TILED;
674
675 if (IS_GEN6(dev))
676 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
677
678 intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
679 pixel_size, true,
680 src_w != crtc_w || src_h != crtc_h);
681
682 /* Sizes are 0 based */
683 src_w--;
684 src_h--;
685 crtc_w--;
686 crtc_h--;
687
688 dvsscale = 0;
689 if (crtc_w != src_w || crtc_h != src_h)
690 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
691
692 linear_offset = y * fb->pitches[0] + x * pixel_size;
693 dvssurf_offset =
694 intel_gen4_compute_page_offset(dev_priv,
695 &x, &y, obj->tiling_mode,
696 pixel_size, fb->pitches[0]);
697 linear_offset -= dvssurf_offset;
698
699 if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
700 dvscntr |= DVS_ROTATE_180;
701
702 x += src_w;
703 y += src_h;
704 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
705 }
706
707 if (key->flags) {
708 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
709 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
710 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
711 }
712
713 if (key->flags & I915_SET_COLORKEY_DESTINATION)
714 dvscntr |= DVS_DEST_KEY;
715 else if (key->flags & I915_SET_COLORKEY_SOURCE)
716 dvscntr |= DVS_SOURCE_KEY;
717
718 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
719 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
720
721 if (obj->tiling_mode != I915_TILING_NONE)
722 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
723 else
724 I915_WRITE(DVSLINOFF(pipe), linear_offset);
725
726 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
727 I915_WRITE(DVSSCALE(pipe), dvsscale);
728 I915_WRITE(DVSCNTR(pipe), dvscntr);
729 I915_WRITE(DVSSURF(pipe),
730 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
731 POSTING_READ(DVSSURF(pipe));
732 }
733
734 static void
735 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
736 {
737 struct drm_device *dev = plane->dev;
738 struct drm_i915_private *dev_priv = dev->dev_private;
739 struct intel_plane *intel_plane = to_intel_plane(plane);
740 int pipe = intel_plane->pipe;
741
742 I915_WRITE(DVSCNTR(pipe), 0);
743 /* Disable the scaler */
744 I915_WRITE(DVSSCALE(pipe), 0);
745
746 I915_WRITE(DVSSURF(pipe), 0);
747 POSTING_READ(DVSSURF(pipe));
748 }
749
750 static int
751 intel_check_sprite_plane(struct drm_plane *plane,
752 struct intel_crtc_state *crtc_state,
753 struct intel_plane_state *state)
754 {
755 struct drm_device *dev = plane->dev;
756 struct drm_crtc *crtc = state->base.crtc;
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758 struct intel_plane *intel_plane = to_intel_plane(plane);
759 struct drm_framebuffer *fb = state->base.fb;
760 int crtc_x, crtc_y;
761 unsigned int crtc_w, crtc_h;
762 uint32_t src_x, src_y, src_w, src_h;
763 struct drm_rect *src = &state->src;
764 struct drm_rect *dst = &state->dst;
765 const struct drm_rect *clip = &state->clip;
766 int hscale, vscale;
767 int max_scale, min_scale;
768 bool can_scale;
769 int pixel_size;
770
771 if (!fb) {
772 state->visible = false;
773 return 0;
774 }
775
776 /* Don't modify another pipe's plane */
777 if (intel_plane->pipe != intel_crtc->pipe) {
778 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
779 return -EINVAL;
780 }
781
782 /* FIXME check all gen limits */
783 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
784 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
785 return -EINVAL;
786 }
787
788 /* setup can_scale, min_scale, max_scale */
789 if (INTEL_INFO(dev)->gen >= 9) {
790 /* use scaler when colorkey is not required */
791 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
792 can_scale = 1;
793 min_scale = 1;
794 max_scale = skl_max_scale(intel_crtc, crtc_state);
795 } else {
796 can_scale = 0;
797 min_scale = DRM_PLANE_HELPER_NO_SCALING;
798 max_scale = DRM_PLANE_HELPER_NO_SCALING;
799 }
800 } else {
801 can_scale = intel_plane->can_scale;
802 max_scale = intel_plane->max_downscale << 16;
803 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
804 }
805
806 /*
807 * FIXME the following code does a bunch of fuzzy adjustments to the
808 * coordinates and sizes. We probably need some way to decide whether
809 * more strict checking should be done instead.
810 */
811 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
812 state->base.rotation);
813
814 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
815 BUG_ON(hscale < 0);
816
817 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
818 BUG_ON(vscale < 0);
819
820 state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
821
822 crtc_x = dst->x1;
823 crtc_y = dst->y1;
824 crtc_w = drm_rect_width(dst);
825 crtc_h = drm_rect_height(dst);
826
827 if (state->visible) {
828 /* check again in case clipping clamped the results */
829 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
830 if (hscale < 0) {
831 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
832 drm_rect_debug_print(src, true);
833 drm_rect_debug_print(dst, false);
834
835 return hscale;
836 }
837
838 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
839 if (vscale < 0) {
840 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
841 drm_rect_debug_print(src, true);
842 drm_rect_debug_print(dst, false);
843
844 return vscale;
845 }
846
847 /* Make the source viewport size an exact multiple of the scaling factors. */
848 drm_rect_adjust_size(src,
849 drm_rect_width(dst) * hscale - drm_rect_width(src),
850 drm_rect_height(dst) * vscale - drm_rect_height(src));
851
852 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
853 state->base.rotation);
854
855 /* sanity check to make sure the src viewport wasn't enlarged */
856 WARN_ON(src->x1 < (int) state->base.src_x ||
857 src->y1 < (int) state->base.src_y ||
858 src->x2 > (int) state->base.src_x + state->base.src_w ||
859 src->y2 > (int) state->base.src_y + state->base.src_h);
860
861 /*
862 * Hardware doesn't handle subpixel coordinates.
863 * Adjust to (macro)pixel boundary, but be careful not to
864 * increase the source viewport size, because that could
865 * push the downscaling factor out of bounds.
866 */
867 src_x = src->x1 >> 16;
868 src_w = drm_rect_width(src) >> 16;
869 src_y = src->y1 >> 16;
870 src_h = drm_rect_height(src) >> 16;
871
872 if (format_is_yuv(fb->pixel_format)) {
873 src_x &= ~1;
874 src_w &= ~1;
875
876 /*
877 * Must keep src and dst the
878 * same if we can't scale.
879 */
880 if (!can_scale)
881 crtc_w &= ~1;
882
883 if (crtc_w == 0)
884 state->visible = false;
885 }
886 }
887
888 /* Check size restrictions when scaling */
889 if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
890 unsigned int width_bytes;
891
892 WARN_ON(!can_scale);
893
894 /* FIXME interlacing min height is 6 */
895
896 if (crtc_w < 3 || crtc_h < 3)
897 state->visible = false;
898
899 if (src_w < 3 || src_h < 3)
900 state->visible = false;
901
902 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
903 width_bytes = ((src_x * pixel_size) & 63) +
904 src_w * pixel_size;
905
906 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
907 width_bytes > 4096 || fb->pitches[0] > 4096)) {
908 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
909 return -EINVAL;
910 }
911 }
912
913 if (state->visible) {
914 src->x1 = src_x << 16;
915 src->x2 = (src_x + src_w) << 16;
916 src->y1 = src_y << 16;
917 src->y2 = (src_y + src_h) << 16;
918 }
919
920 dst->x1 = crtc_x;
921 dst->x2 = crtc_x + crtc_w;
922 dst->y1 = crtc_y;
923 dst->y2 = crtc_y + crtc_h;
924
925 return 0;
926 }
927
928 static void
929 intel_commit_sprite_plane(struct drm_plane *plane,
930 struct intel_plane_state *state)
931 {
932 struct drm_crtc *crtc = state->base.crtc;
933 struct intel_plane *intel_plane = to_intel_plane(plane);
934 struct drm_framebuffer *fb = state->base.fb;
935
936 crtc = crtc ? crtc : plane->crtc;
937
938 if (!crtc->state->active)
939 return;
940
941 if (state->visible) {
942 intel_plane->update_plane(plane, crtc, fb,
943 state->dst.x1, state->dst.y1,
944 drm_rect_width(&state->dst),
945 drm_rect_height(&state->dst),
946 state->src.x1 >> 16,
947 state->src.y1 >> 16,
948 drm_rect_width(&state->src) >> 16,
949 drm_rect_height(&state->src) >> 16);
950 } else {
951 intel_plane->disable_plane(plane, crtc);
952 }
953 }
954
955 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
956 struct drm_file *file_priv)
957 {
958 struct drm_intel_sprite_colorkey *set = data;
959 struct drm_plane *plane;
960 struct drm_plane_state *plane_state;
961 struct drm_atomic_state *state;
962 struct drm_modeset_acquire_ctx ctx;
963 int ret = 0;
964
965 /* Make sure we don't try to enable both src & dest simultaneously */
966 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
967 return -EINVAL;
968
969 if (IS_VALLEYVIEW(dev) &&
970 set->flags & I915_SET_COLORKEY_DESTINATION)
971 return -EINVAL;
972
973 plane = drm_plane_find(dev, set->plane_id);
974 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
975 return -ENOENT;
976
977 drm_modeset_acquire_init(&ctx, 0);
978
979 state = drm_atomic_state_alloc(plane->dev);
980 if (!state) {
981 ret = -ENOMEM;
982 goto out;
983 }
984 state->acquire_ctx = &ctx;
985
986 while (1) {
987 plane_state = drm_atomic_get_plane_state(state, plane);
988 ret = PTR_ERR_OR_ZERO(plane_state);
989 if (!ret) {
990 to_intel_plane_state(plane_state)->ckey = *set;
991 ret = drm_atomic_commit(state);
992 }
993
994 if (ret != -EDEADLK)
995 break;
996
997 drm_atomic_state_clear(state);
998 drm_modeset_backoff(&ctx);
999 }
1000
1001 if (ret)
1002 drm_atomic_state_free(state);
1003
1004 out:
1005 drm_modeset_drop_locks(&ctx);
1006 drm_modeset_acquire_fini(&ctx);
1007 return ret;
1008 }
1009
1010 static const uint32_t ilk_plane_formats[] = {
1011 DRM_FORMAT_XRGB8888,
1012 DRM_FORMAT_YUYV,
1013 DRM_FORMAT_YVYU,
1014 DRM_FORMAT_UYVY,
1015 DRM_FORMAT_VYUY,
1016 };
1017
1018 static const uint32_t snb_plane_formats[] = {
1019 DRM_FORMAT_XBGR8888,
1020 DRM_FORMAT_XRGB8888,
1021 DRM_FORMAT_YUYV,
1022 DRM_FORMAT_YVYU,
1023 DRM_FORMAT_UYVY,
1024 DRM_FORMAT_VYUY,
1025 };
1026
1027 static const uint32_t vlv_plane_formats[] = {
1028 DRM_FORMAT_RGB565,
1029 DRM_FORMAT_ABGR8888,
1030 DRM_FORMAT_ARGB8888,
1031 DRM_FORMAT_XBGR8888,
1032 DRM_FORMAT_XRGB8888,
1033 DRM_FORMAT_XBGR2101010,
1034 DRM_FORMAT_ABGR2101010,
1035 DRM_FORMAT_YUYV,
1036 DRM_FORMAT_YVYU,
1037 DRM_FORMAT_UYVY,
1038 DRM_FORMAT_VYUY,
1039 };
1040
1041 static uint32_t skl_plane_formats[] = {
1042 DRM_FORMAT_RGB565,
1043 DRM_FORMAT_ABGR8888,
1044 DRM_FORMAT_ARGB8888,
1045 DRM_FORMAT_XBGR8888,
1046 DRM_FORMAT_XRGB8888,
1047 DRM_FORMAT_YUYV,
1048 DRM_FORMAT_YVYU,
1049 DRM_FORMAT_UYVY,
1050 DRM_FORMAT_VYUY,
1051 };
1052
1053 int
1054 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1055 {
1056 struct intel_plane *intel_plane;
1057 struct intel_plane_state *state;
1058 unsigned long possible_crtcs;
1059 const uint32_t *plane_formats;
1060 int num_plane_formats;
1061 int ret;
1062
1063 if (INTEL_INFO(dev)->gen < 5)
1064 return -ENODEV;
1065
1066 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1067 if (!intel_plane)
1068 return -ENOMEM;
1069
1070 state = intel_create_plane_state(&intel_plane->base);
1071 if (!state) {
1072 kfree(intel_plane);
1073 return -ENOMEM;
1074 }
1075 intel_plane->base.state = &state->base;
1076
1077 switch (INTEL_INFO(dev)->gen) {
1078 case 5:
1079 case 6:
1080 intel_plane->can_scale = true;
1081 intel_plane->max_downscale = 16;
1082 intel_plane->update_plane = ilk_update_plane;
1083 intel_plane->disable_plane = ilk_disable_plane;
1084
1085 if (IS_GEN6(dev)) {
1086 plane_formats = snb_plane_formats;
1087 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1088 } else {
1089 plane_formats = ilk_plane_formats;
1090 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1091 }
1092 break;
1093
1094 case 7:
1095 case 8:
1096 if (IS_IVYBRIDGE(dev)) {
1097 intel_plane->can_scale = true;
1098 intel_plane->max_downscale = 2;
1099 } else {
1100 intel_plane->can_scale = false;
1101 intel_plane->max_downscale = 1;
1102 }
1103
1104 if (IS_VALLEYVIEW(dev)) {
1105 intel_plane->update_plane = vlv_update_plane;
1106 intel_plane->disable_plane = vlv_disable_plane;
1107
1108 plane_formats = vlv_plane_formats;
1109 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1110 } else {
1111 intel_plane->update_plane = ivb_update_plane;
1112 intel_plane->disable_plane = ivb_disable_plane;
1113
1114 plane_formats = snb_plane_formats;
1115 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1116 }
1117 break;
1118 case 9:
1119 intel_plane->can_scale = true;
1120 intel_plane->update_plane = skl_update_plane;
1121 intel_plane->disable_plane = skl_disable_plane;
1122 state->scaler_id = -1;
1123
1124 plane_formats = skl_plane_formats;
1125 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1126 break;
1127 default:
1128 kfree(intel_plane);
1129 return -ENODEV;
1130 }
1131
1132 intel_plane->pipe = pipe;
1133 intel_plane->plane = plane;
1134 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1135 intel_plane->check_plane = intel_check_sprite_plane;
1136 intel_plane->commit_plane = intel_commit_sprite_plane;
1137 possible_crtcs = (1 << pipe);
1138 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1139 &intel_plane_funcs,
1140 plane_formats, num_plane_formats,
1141 DRM_PLANE_TYPE_OVERLAY);
1142 if (ret) {
1143 kfree(intel_plane);
1144 goto out;
1145 }
1146
1147 intel_create_rotation_property(dev, intel_plane);
1148
1149 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1150
1151 out:
1152 return ret;
1153 }
Linux kernel - Deliverables
This page took 0.058744 seconds and 5 git commands to generate.