drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 static bool
  43 format_is_yuv(uint32_t format)
  44 {
  45         switch (format) {
  46         case DRM_FORMAT_YUYV:
  47         case DRM_FORMAT_UYVY:
  48         case DRM_FORMAT_VYUY:
  49         case DRM_FORMAT_YVYU:
  50                 return true;
  51         default:
  52                 return false;
  53         }
  54 }
  55
  56 static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
  57 {
  58         /* paranoia */
  59         if (!mode->crtc_htotal)
  60                 return 1;
  61
  62         return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
  63 }
  64
  65 /**
  66  * intel_pipe_update_start() - start update of a set of display registers
  67  * @crtc: the crtc of which the registers are going to be updated
  68  * @start_vbl_count: vblank counter return pointer used for error checking
  69  *
  70  * Mark the start of an update to pipe registers that should be updated
  71  * atomically regarding vblank. If the next vblank will happens within
  72  * the next 100 us, this function waits until the vblank passes.
  73  *
  74  * After a successful call to this function, interrupts will be disabled
  75  * until a subsequent call to intel_pipe_update_end(). That is done to
  76  * avoid random delays. The value written to @start_vbl_count should be
  77  * supplied to intel_pipe_update_end() for error checking.
  78  *
  79  * Return: true if the call was successful
  80  */
  81 bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
  82 {
  83         struct drm_device *dev = crtc->base.dev;
  84         const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
  85         enum pipe pipe = crtc->pipe;
  86         long timeout = msecs_to_jiffies_timeout(1);
  87         int scanline, min, max, vblank_start;
  88         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  89         DEFINE_WAIT(wait);
  90
  91         vblank_start = mode->crtc_vblank_start;
  92         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  93                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  94
  95         /* FIXME needs to be calibrated sensibly */
  96         min = vblank_start - usecs_to_scanlines(mode, 100);
  97         max = vblank_start - 1;
  98
  99         if (min <= 0 || max <= 0)
 100                 return false;
 101
 102         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 103                 return false;
 104
 105         local_irq_disable();
 106
 107         trace_i915_pipe_update_start(crtc, min, max);
 108
 109         for (;;) {
 110                 /*
 111                  * prepare_to_wait() has a memory barrier, which guarantees
 112                  * other CPUs can see the task state update by the time we
 113                  * read the scanline.
 114                  */
 115                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 116
 117                 scanline = intel_get_crtc_scanline(crtc);
 118                 if (scanline < min || scanline > max)
 119                         break;
 120
 121                 if (timeout <= 0) {
 122                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 123                                   pipe_name(crtc->pipe));
 124                         break;
 125                 }
 126
 127                 local_irq_enable();
 128
 129                 timeout = schedule_timeout(timeout);
 130
 131                 local_irq_disable();
 132         }
 133
 134         finish_wait(wq, &wait);
 135
 136         drm_crtc_vblank_put(&crtc->base);
 137
 138         *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 139
 140         trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count);
 141
 142         return true;
 143 }
 144
 145 /**
 146  * intel_pipe_update_end() - end update of a set of display registers
 147  * @crtc: the crtc of which the registers were updated
 148  * @start_vbl_count: start vblank counter (used for error checking)
 149  *
 150  * Mark the end of an update started with intel_pipe_update_start(). This
 151  * re-enables interrupts and verifies the update was actually completed
 152  * before a vblank using the value of @start_vbl_count.
 153  */
 154 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
 155 {
 156         struct drm_device *dev = crtc->base.dev;
 157         enum pipe pipe = crtc->pipe;
 158         u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 159
 160         trace_i915_pipe_update_end(crtc, end_vbl_count);
 161
 162         local_irq_enable();
 163
 164         if (start_vbl_count != end_vbl_count)
 165                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
 166                           pipe_name(pipe), start_vbl_count, end_vbl_count);
 167 }
 168
 169 static void
 170 skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 171                  struct drm_framebuffer *fb,
 172                  int crtc_x, int crtc_y,
 173                  unsigned int crtc_w, unsigned int crtc_h,
 174                  uint32_t x, uint32_t y,
 175                  uint32_t src_w, uint32_t src_h)
 176 {
 177         struct drm_device *dev = drm_plane->dev;
 178         struct drm_i915_private *dev_priv = dev->dev_private;
 179         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 180         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 181         const int pipe = intel_plane->pipe;
 182         const int plane = intel_plane->plane + 1;
 183         u32 plane_ctl, stride_div, stride;
 184         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 185         const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey;
 186         unsigned long surf_addr;
 187         u32 tile_height, plane_offset, plane_size;
 188         unsigned int rotation;
 189         int x_offset, y_offset;
 190         struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
 191         int scaler_id;
 192
 193         plane_ctl = PLANE_CTL_ENABLE |
 194                 PLANE_CTL_PIPE_CSC_ENABLE;
 195
 196         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
 197         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
 198
 199         rotation = drm_plane->state->rotation;
 200         plane_ctl |= skl_plane_ctl_rotation(rotation);
 201
 202         intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
 203                                        pixel_size, true,
 204                                        src_w != crtc_w || src_h != crtc_h);
 205
 206         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
 207                                                fb->pixel_format);
 208
 209         scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id;
 210
 211         /* Sizes are 0 based */
 212         src_w--;
 213         src_h--;
 214         crtc_w--;
 215         crtc_h--;
 216
 217         if (key->flags) {
 218                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
 219                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
 220                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
 221         }
 222
 223         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 224                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 225         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 226                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 227
 228         surf_addr = intel_plane_obj_offset(intel_plane, obj);
 229
 230         if (intel_rotation_90_or_270(rotation)) {
 231                 /* stride: Surface height in tiles */
 232                 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
 233                                                         fb->modifier[0]);
 234                 stride = DIV_ROUND_UP(fb->height, tile_height);
 235                 plane_size = (src_w << 16) | src_h;
 236                 x_offset = stride * tile_height - y - (src_h + 1);
 237                 y_offset = x;
 238         } else {
 239                 stride = fb->pitches[0] / stride_div;
 240                 plane_size = (src_h << 16) | src_w;
 241                 x_offset = x;
 242                 y_offset = y;
 243         }
 244         plane_offset = y_offset << 16 | x_offset;
 245
 246         I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
 247         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
 248         I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
 249
 250         /* program plane scaler */
 251         if (scaler_id >= 0) {
 252                 uint32_t ps_ctrl = 0;
 253
 254                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
 255                         PS_PLANE_SEL(plane));
 256                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
 257                         crtc_state->scaler_state.scalers[scaler_id].mode;
 258                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
 259                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 260                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 261                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
 262                         ((crtc_w + 1) << 16)|(crtc_h + 1));
 263
 264                 I915_WRITE(PLANE_POS(pipe, plane), 0);
 265         } else {
 266                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
 267         }
 268
 269         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 270         I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
 271         POSTING_READ(PLANE_SURF(pipe, plane));
 272 }
 273
 274 static void
 275 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force)
 276 {
 277         struct drm_device *dev = dplane->dev;
 278         struct drm_i915_private *dev_priv = dev->dev_private;
 279         struct intel_plane *intel_plane = to_intel_plane(dplane);
 280         const int pipe = intel_plane->pipe;
 281         const int plane = intel_plane->plane + 1;
 282
 283         I915_WRITE(PLANE_CTL(pipe, plane), 0);
 284
 285         /* Activate double buffered register update */
 286         I915_WRITE(PLANE_SURF(pipe, plane), 0);
 287         POSTING_READ(PLANE_SURF(pipe, plane));
 288
 289         intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
 290 }
 291
 292 static void
 293 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 294 {
 295         struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
 296         int plane = intel_plane->plane;
 297
 298         /* Seems RGB data bypasses the CSC always */
 299         if (!format_is_yuv(format))
 300                 return;
 301
 302         /*
 303          * BT.601 limited range YCbCr -> full range RGB
 304          *
 305          * |r|   | 6537 4769     0|   |cr  |
 306          * |g| = |-3330 4769 -1605| x |y-64|
 307          * |b|   |    0 4769  8263|   |cb  |
 308          *
 309          * Cb and Cr apparently come in as signed already, so no
 310          * need for any offset. For Y we need to remove the offset.
 311          */
 312         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 313         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 314         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 315
 316         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
 317         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
 318         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
 319         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
 320         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
 321
 322         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 323         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 324         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 325
 326         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 327         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 328         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 329 }
 330
 331 static void
 332 vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 333                  struct drm_framebuffer *fb,
 334                  int crtc_x, int crtc_y,
 335                  unsigned int crtc_w, unsigned int crtc_h,
 336                  uint32_t x, uint32_t y,
 337                  uint32_t src_w, uint32_t src_h)
 338 {
 339         struct drm_device *dev = dplane->dev;
 340         struct drm_i915_private *dev_priv = dev->dev_private;
 341         struct intel_plane *intel_plane = to_intel_plane(dplane);
 342         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 343         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 344         int pipe = intel_plane->pipe;
 345         int plane = intel_plane->plane;
 346         u32 sprctl;
 347         unsigned long sprsurf_offset, linear_offset;
 348         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 349         const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey;
 350
 351         sprctl = SP_ENABLE;
 352
 353         switch (fb->pixel_format) {
 354         case DRM_FORMAT_YUYV:
 355                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 356                 break;
 357         case DRM_FORMAT_YVYU:
 358                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 359                 break;
 360         case DRM_FORMAT_UYVY:
 361                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 362                 break;
 363         case DRM_FORMAT_VYUY:
 364                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 365                 break;
 366         case DRM_FORMAT_RGB565:
 367                 sprctl |= SP_FORMAT_BGR565;
 368                 break;
 369         case DRM_FORMAT_XRGB8888:
 370                 sprctl |= SP_FORMAT_BGRX8888;
 371                 break;
 372         case DRM_FORMAT_ARGB8888:
 373                 sprctl |= SP_FORMAT_BGRA8888;
 374                 break;
 375         case DRM_FORMAT_XBGR2101010:
 376                 sprctl |= SP_FORMAT_RGBX1010102;
 377                 break;
 378         case DRM_FORMAT_ABGR2101010:
 379                 sprctl |= SP_FORMAT_RGBA1010102;
 380                 break;
 381         case DRM_FORMAT_XBGR8888:
 382                 sprctl |= SP_FORMAT_RGBX8888;
 383                 break;
 384         case DRM_FORMAT_ABGR8888:
 385                 sprctl |= SP_FORMAT_RGBA8888;
 386                 break;
 387         default:
 388                 /*
 389                  * If we get here one of the upper layers failed to filter
 390                  * out the unsupported plane formats
 391                  */
 392                 BUG();
 393                 break;
 394         }
 395
 396         /*
 397          * Enable gamma to match primary/cursor plane behaviour.
 398          * FIXME should be user controllable via propertiesa.
 399          */
 400         sprctl |= SP_GAMMA_ENABLE;
 401
 402         if (obj->tiling_mode != I915_TILING_NONE)
 403                 sprctl |= SP_TILED;
 404
 405         intel_update_sprite_watermarks(dplane, crtc, src_w, src_h,
 406                                        pixel_size, true,
 407                                        src_w != crtc_w || src_h != crtc_h);
 408
 409         /* Sizes are 0 based */
 410         src_w--;
 411         src_h--;
 412         crtc_w--;
 413         crtc_h--;
 414
 415         linear_offset = y * fb->pitches[0] + x * pixel_size;
 416         sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
 417                                                         obj->tiling_mode,
 418                                                         pixel_size,
 419                                                         fb->pitches[0]);
 420         linear_offset -= sprsurf_offset;
 421
 422         if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
 423                 sprctl |= SP_ROTATE_180;
 424
 425                 x += src_w;
 426                 y += src_h;
 427                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 428         }
 429
 430         if (key->flags) {
 431                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 432                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 433                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 434         }
 435
 436         if (key->flags & I915_SET_COLORKEY_SOURCE)
 437                 sprctl |= SP_SOURCE_KEY;
 438
 439         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
 440                 chv_update_csc(intel_plane, fb->pixel_format);
 441
 442         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 443         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 444
 445         if (obj->tiling_mode != I915_TILING_NONE)
 446                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 447         else
 448                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 449
 450         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
 451
 452         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 453         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 454         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
 455                    sprsurf_offset);
 456
 457         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 458 }
 459
 460 static void
 461 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force)
 462 {
 463         struct drm_device *dev = dplane->dev;
 464         struct drm_i915_private *dev_priv = dev->dev_private;
 465         struct intel_plane *intel_plane = to_intel_plane(dplane);
 466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 467         int pipe = intel_plane->pipe;
 468         int plane = intel_plane->plane;
 469
 470         I915_WRITE(SPCNTR(pipe, plane), 0);
 471
 472         /* Activate double buffered register update */
 473         I915_WRITE(SPSURF(pipe, plane), 0);
 474
 475         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 476
 477         intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
 478 }
 479
 480
 481 static void
 482 ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 483                  struct drm_framebuffer *fb,
 484                  int crtc_x, int crtc_y,
 485                  unsigned int crtc_w, unsigned int crtc_h,
 486                  uint32_t x, uint32_t y,
 487                  uint32_t src_w, uint32_t src_h)
 488 {
 489         struct drm_device *dev = plane->dev;
 490         struct drm_i915_private *dev_priv = dev->dev_private;
 491         struct intel_plane *intel_plane = to_intel_plane(plane);
 492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 493         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 494         enum pipe pipe = intel_plane->pipe;
 495         u32 sprctl, sprscale = 0;
 496         unsigned long sprsurf_offset, linear_offset;
 497         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 498         const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey;
 499
 500         sprctl = SPRITE_ENABLE;
 501
 502         switch (fb->pixel_format) {
 503         case DRM_FORMAT_XBGR8888:
 504                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 505                 break;
 506         case DRM_FORMAT_XRGB8888:
 507                 sprctl |= SPRITE_FORMAT_RGBX888;
 508                 break;
 509         case DRM_FORMAT_YUYV:
 510                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 511                 break;
 512         case DRM_FORMAT_YVYU:
 513                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 514                 break;
 515         case DRM_FORMAT_UYVY:
 516                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 517                 break;
 518         case DRM_FORMAT_VYUY:
 519                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 520                 break;
 521         default:
 522                 BUG();
 523         }
 524
 525         /*
 526          * Enable gamma to match primary/cursor plane behaviour.
 527          * FIXME should be user controllable via propertiesa.
 528          */
 529         sprctl |= SPRITE_GAMMA_ENABLE;
 530
 531         if (obj->tiling_mode != I915_TILING_NONE)
 532                 sprctl |= SPRITE_TILED;
 533
 534         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 535                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 536         else
 537                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 538
 539         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 540                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 541
 542         intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
 543                                        true,
 544                                        src_w != crtc_w || src_h != crtc_h);
 545
 546         /* Sizes are 0 based */
 547         src_w--;
 548         src_h--;
 549         crtc_w--;
 550         crtc_h--;
 551
 552         if (crtc_w != src_w || crtc_h != src_h)
 553                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 554
 555         linear_offset = y * fb->pitches[0] + x * pixel_size;
 556         sprsurf_offset =
 557                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
 558                                                pixel_size, fb->pitches[0]);
 559         linear_offset -= sprsurf_offset;
 560
 561         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
 562                 sprctl |= SPRITE_ROTATE_180;
 563
 564                 /* HSW and BDW does this automagically in hardware */
 565                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
 566                         x += src_w;
 567                         y += src_h;
 568                         linear_offset += src_h * fb->pitches[0] +
 569                                 src_w * pixel_size;
 570                 }
 571         }
 572
 573         if (key->flags) {
 574                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
 575                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
 576                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
 577         }
 578
 579         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 580                 sprctl |= SPRITE_DEST_KEY;
 581         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 582                 sprctl |= SPRITE_SOURCE_KEY;
 583
 584         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 585         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 586
 587         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 588          * register */
 589         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 590                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 591         else if (obj->tiling_mode != I915_TILING_NONE)
 592                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 593         else
 594                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 595
 596         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 597         if (intel_plane->can_scale)
 598                 I915_WRITE(SPRSCALE(pipe), sprscale);
 599         I915_WRITE(SPRCTL(pipe), sprctl);
 600         I915_WRITE(SPRSURF(pipe),
 601                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
 602
 603         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 604 }
 605
 606 static void
 607 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force)
 608 {
 609         struct drm_device *dev = plane->dev;
 610         struct drm_i915_private *dev_priv = dev->dev_private;
 611         struct intel_plane *intel_plane = to_intel_plane(plane);
 612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 613         int pipe = intel_plane->pipe;
 614
 615         I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
 616         /* Can't leave the scaler enabled... */
 617         if (intel_plane->can_scale)
 618                 I915_WRITE(SPRSCALE(pipe), 0);
 619         /* Activate double buffered register update */
 620         I915_WRITE(SPRSURF(pipe), 0);
 621
 622         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 623 }
 624
 625 static void
 626 ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 627                  struct drm_framebuffer *fb,
 628                  int crtc_x, int crtc_y,
 629                  unsigned int crtc_w, unsigned int crtc_h,
 630                  uint32_t x, uint32_t y,
 631                  uint32_t src_w, uint32_t src_h)
 632 {
 633         struct drm_device *dev = plane->dev;
 634         struct drm_i915_private *dev_priv = dev->dev_private;
 635         struct intel_plane *intel_plane = to_intel_plane(plane);
 636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 637         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 638         int pipe = intel_plane->pipe;
 639         unsigned long dvssurf_offset, linear_offset;
 640         u32 dvscntr, dvsscale;
 641         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 642         const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey;
 643
 644         dvscntr = DVS_ENABLE;
 645
 646         switch (fb->pixel_format) {
 647         case DRM_FORMAT_XBGR8888:
 648                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 649                 break;
 650         case DRM_FORMAT_XRGB8888:
 651                 dvscntr |= DVS_FORMAT_RGBX888;
 652                 break;
 653         case DRM_FORMAT_YUYV:
 654                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 655                 break;
 656         case DRM_FORMAT_YVYU:
 657                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 658                 break;
 659         case DRM_FORMAT_UYVY:
 660                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 661                 break;
 662         case DRM_FORMAT_VYUY:
 663                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 664                 break;
 665         default:
 666                 BUG();
 667         }
 668
 669         /*
 670          * Enable gamma to match primary/cursor plane behaviour.
 671          * FIXME should be user controllable via propertiesa.
 672          */
 673         dvscntr |= DVS_GAMMA_ENABLE;
 674
 675         if (obj->tiling_mode != I915_TILING_NONE)
 676                 dvscntr |= DVS_TILED;
 677
 678         if (IS_GEN6(dev))
 679                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 680
 681         intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
 682                                        pixel_size, true,
 683                                        src_w != crtc_w || src_h != crtc_h);
 684
 685         /* Sizes are 0 based */
 686         src_w--;
 687         src_h--;
 688         crtc_w--;
 689         crtc_h--;
 690
 691         dvsscale = 0;
 692         if (crtc_w != src_w || crtc_h != src_h)
 693                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 694
 695         linear_offset = y * fb->pitches[0] + x * pixel_size;
 696         dvssurf_offset =
 697                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
 698                                                pixel_size, fb->pitches[0]);
 699         linear_offset -= dvssurf_offset;
 700
 701         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
 702                 dvscntr |= DVS_ROTATE_180;
 703
 704                 x += src_w;
 705                 y += src_h;
 706                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 707         }
 708
 709         if (key->flags) {
 710                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
 711                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
 712                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
 713         }
 714
 715         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 716                 dvscntr |= DVS_DEST_KEY;
 717         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 718                 dvscntr |= DVS_SOURCE_KEY;
 719
 720         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 721         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 722
 723         if (obj->tiling_mode != I915_TILING_NONE)
 724                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 725         else
 726                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 727
 728         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 729         I915_WRITE(DVSSCALE(pipe), dvsscale);
 730         I915_WRITE(DVSCNTR(pipe), dvscntr);
 731         I915_WRITE(DVSSURF(pipe),
 732                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
 733
 734         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 735 }
 736
 737 static void
 738 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force)
 739 {
 740         struct drm_device *dev = plane->dev;
 741         struct drm_i915_private *dev_priv = dev->dev_private;
 742         struct intel_plane *intel_plane = to_intel_plane(plane);
 743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 744         int pipe = intel_plane->pipe;
 745
 746         I915_WRITE(DVSCNTR(pipe), 0);
 747         /* Disable the scaler */
 748         I915_WRITE(DVSSCALE(pipe), 0);
 749
 750         /* Flush double buffered register updates */
 751         I915_WRITE(DVSSURF(pipe), 0);
 752
 753         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 754 }
 755
 756 /**
 757  * intel_post_enable_primary - Perform operations after enabling primary plane
 758  * @crtc: the CRTC whose primary plane was just enabled
 759  *
 760  * Performs potentially sleeping operations that must be done after the primary
 761  * plane is enabled, such as updating FBC and IPS.  Note that this may be
 762  * called due to an explicit primary plane update, or due to an implicit
 763  * re-enable that is caused when a sprite plane is updated to no longer
 764  * completely hide the primary plane.
 765  */
 766 void
 767 intel_post_enable_primary(struct drm_crtc *crtc)
 768 {
 769         struct drm_device *dev = crtc->dev;
 770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 771
 772         /*
 773          * BDW signals flip done immediately if the plane
 774          * is disabled, even if the plane enable is already
 775          * armed to occur at the next vblank :(
 776          */
 777         if (IS_BROADWELL(dev))
 778                 intel_wait_for_vblank(dev, intel_crtc->pipe);
 779
 780         /*
 781          * FIXME IPS should be fine as long as one plane is
 782          * enabled, but in practice it seems to have problems
 783          * when going from primary only to sprite only and vice
 784          * versa.
 785          */
 786         hsw_enable_ips(intel_crtc);
 787
 788         mutex_lock(&dev->struct_mutex);
 789         intel_fbc_update(dev);
 790         mutex_unlock(&dev->struct_mutex);
 791 }
 792
 793 /**
 794  * intel_pre_disable_primary - Perform operations before disabling primary plane
 795  * @crtc: the CRTC whose primary plane is to be disabled
 796  *
 797  * Performs potentially sleeping operations that must be done before the
 798  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
 799  * be called due to an explicit primary plane update, or due to an implicit
 800  * disable that is caused when a sprite plane completely hides the primary
 801  * plane.
 802  */
 803 void
 804 intel_pre_disable_primary(struct drm_crtc *crtc)
 805 {
 806         struct drm_device *dev = crtc->dev;
 807         struct drm_i915_private *dev_priv = dev->dev_private;
 808         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 809
 810         mutex_lock(&dev->struct_mutex);
 811         if (dev_priv->fbc.crtc == intel_crtc)
 812                 intel_fbc_disable(dev);
 813         mutex_unlock(&dev->struct_mutex);
 814
 815         /*
 816          * FIXME IPS should be fine as long as one plane is
 817          * enabled, but in practice it seems to have problems
 818          * when going from primary only to sprite only and vice
 819          * versa.
 820          */
 821         hsw_disable_ips(intel_crtc);
 822 }
 823
 824 static int
 825 intel_check_sprite_plane(struct drm_plane *plane,
 826                          struct intel_plane_state *state)
 827 {
 828         struct drm_device *dev = plane->dev;
 829         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
 830         struct intel_crtc_state *crtc_state;
 831         struct intel_plane *intel_plane = to_intel_plane(plane);
 832         struct drm_framebuffer *fb = state->base.fb;
 833         int crtc_x, crtc_y;
 834         unsigned int crtc_w, crtc_h;
 835         uint32_t src_x, src_y, src_w, src_h;
 836         struct drm_rect *src = &state->src;
 837         struct drm_rect *dst = &state->dst;
 838         const struct drm_rect *clip = &state->clip;
 839         int hscale, vscale;
 840         int max_scale, min_scale;
 841         int pixel_size;
 842         int ret;
 843
 844         intel_crtc = intel_crtc ? intel_crtc : to_intel_crtc(plane->crtc);
 845         crtc_state = state->base.state ?
 846                 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
 847
 848         if (!fb) {
 849                 state->visible = false;
 850                 goto finish;
 851         }
 852
 853         /* Don't modify another pipe's plane */
 854         if (intel_plane->pipe != intel_crtc->pipe) {
 855                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 856                 return -EINVAL;
 857         }
 858
 859         /* FIXME check all gen limits */
 860         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 861                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 862                 return -EINVAL;
 863         }
 864
 865         /*
 866          * FIXME the following code does a bunch of fuzzy adjustments to the
 867          * coordinates and sizes. We probably need some way to decide whether
 868          * more strict checking should be done instead.
 869          */
 870         max_scale = intel_plane->max_downscale << 16;
 871         min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 872
 873         if (INTEL_INFO(dev)->gen >= 9) {
 874                 min_scale = 1;
 875                 max_scale = skl_max_scale(intel_crtc, crtc_state);
 876         }
 877
 878         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 879                         state->base.rotation);
 880
 881         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 882         BUG_ON(hscale < 0);
 883
 884         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 885         BUG_ON(vscale < 0);
 886
 887         state->visible =  drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 888
 889         crtc_x = dst->x1;
 890         crtc_y = dst->y1;
 891         crtc_w = drm_rect_width(dst);
 892         crtc_h = drm_rect_height(dst);
 893
 894         if (state->visible) {
 895                 /* check again in case clipping clamped the results */
 896                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 897                 if (hscale < 0) {
 898                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 899                         drm_rect_debug_print(src, true);
 900                         drm_rect_debug_print(dst, false);
 901
 902                         return hscale;
 903                 }
 904
 905                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 906                 if (vscale < 0) {
 907                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 908                         drm_rect_debug_print(src, true);
 909                         drm_rect_debug_print(dst, false);
 910
 911                         return vscale;
 912                 }
 913
 914                 /* Make the source viewport size an exact multiple of the scaling factors. */
 915                 drm_rect_adjust_size(src,
 916                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 917                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 918
 919                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 920                                     state->base.rotation);
 921
 922                 /* sanity check to make sure the src viewport wasn't enlarged */
 923                 WARN_ON(src->x1 < (int) state->base.src_x ||
 924                         src->y1 < (int) state->base.src_y ||
 925                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 926                         src->y2 > (int) state->base.src_y + state->base.src_h);
 927
 928                 /*
 929                  * Hardware doesn't handle subpixel coordinates.
 930                  * Adjust to (macro)pixel boundary, but be careful not to
 931                  * increase the source viewport size, because that could
 932                  * push the downscaling factor out of bounds.
 933                  */
 934                 src_x = src->x1 >> 16;
 935                 src_w = drm_rect_width(src) >> 16;
 936                 src_y = src->y1 >> 16;
 937                 src_h = drm_rect_height(src) >> 16;
 938
 939                 if (format_is_yuv(fb->pixel_format)) {
 940                         src_x &= ~1;
 941                         src_w &= ~1;
 942
 943                         /*
 944                          * Must keep src and dst the
 945                          * same if we can't scale.
 946                          */
 947                         if (!intel_plane->can_scale)
 948                                 crtc_w &= ~1;
 949
 950                         if (crtc_w == 0)
 951                                 state->visible = false;
 952                 }
 953         }
 954
 955         /* Check size restrictions when scaling */
 956         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
 957                 unsigned int width_bytes;
 958
 959                 WARN_ON(!intel_plane->can_scale);
 960
 961                 /* FIXME interlacing min height is 6 */
 962
 963                 if (crtc_w < 3 || crtc_h < 3)
 964                         state->visible = false;
 965
 966                 if (src_w < 3 || src_h < 3)
 967                         state->visible = false;
 968
 969                 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 970                 width_bytes = ((src_x * pixel_size) & 63) +
 971                                         src_w * pixel_size;
 972
 973                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
 974                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 975                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 976                         return -EINVAL;
 977                 }
 978         }
 979
 980         if (state->visible) {
 981                 src->x1 = src_x << 16;
 982                 src->x2 = (src_x + src_w) << 16;
 983                 src->y1 = src_y << 16;
 984                 src->y2 = (src_y + src_h) << 16;
 985         }
 986
 987         dst->x1 = crtc_x;
 988         dst->x2 = crtc_x + crtc_w;
 989         dst->y1 = crtc_y;
 990         dst->y2 = crtc_y + crtc_h;
 991
 992 finish:
 993         /*
 994          * If the sprite is completely covering the primary plane,
 995          * we can disable the primary and save power.
 996          */
 997         if (intel_crtc->active) {
 998                 intel_crtc->atomic.fb_bits |=
 999                         INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe);
1000
1001                 if (intel_wm_need_update(plane, &state->base))
1002                         intel_crtc->atomic.update_wm = true;
1003
1004                 if (!state->visible) {
1005                         /*
1006                          * Avoid underruns when disabling the sprite.
1007                          * FIXME remove once watermark updates are done properly.
1008                          */
1009                         intel_crtc->atomic.wait_vblank = true;
1010                         intel_crtc->atomic.update_sprite_watermarks |=
1011                                 (1 << drm_plane_index(plane));
1012                 }
1013         }
1014
1015         if (INTEL_INFO(dev)->gen >= 9) {
1016                 ret = skl_update_scaler_users(intel_crtc, crtc_state, intel_plane,
1017                         state, 0);
1018                 if (ret)
1019                         return ret;
1020         }
1021
1022         return 0;
1023 }
1024
1025 static void
1026 intel_commit_sprite_plane(struct drm_plane *plane,
1027                           struct intel_plane_state *state)
1028 {
1029         struct drm_crtc *crtc = state->base.crtc;
1030         struct intel_crtc *intel_crtc;
1031         struct intel_plane *intel_plane = to_intel_plane(plane);
1032         struct drm_framebuffer *fb = state->base.fb;
1033         int crtc_x, crtc_y;
1034         unsigned int crtc_w, crtc_h;
1035         uint32_t src_x, src_y, src_w, src_h;
1036
1037         crtc = crtc ? crtc : plane->crtc;
1038         intel_crtc = to_intel_crtc(crtc);
1039
1040         plane->fb = fb;
1041
1042         if (intel_crtc->active) {
1043                 if (state->visible) {
1044                         crtc_x = state->dst.x1;
1045                         crtc_y = state->dst.y1;
1046                         crtc_w = drm_rect_width(&state->dst);
1047                         crtc_h = drm_rect_height(&state->dst);
1048                         src_x = state->src.x1 >> 16;
1049                         src_y = state->src.y1 >> 16;
1050                         src_w = drm_rect_width(&state->src) >> 16;
1051                         src_h = drm_rect_height(&state->src) >> 16;
1052                         intel_plane->update_plane(plane, crtc, fb,
1053                                                   crtc_x, crtc_y, crtc_w, crtc_h,
1054                                                   src_x, src_y, src_w, src_h);
1055                 } else {
1056                         intel_plane->disable_plane(plane, crtc, false);
1057                 }
1058         }
1059 }
1060
1061 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1062                               struct drm_file *file_priv)
1063 {
1064         struct drm_intel_sprite_colorkey *set = data;
1065         struct drm_plane *plane;
1066         struct intel_plane *intel_plane;
1067         int ret = 0;
1068
1069         /* Make sure we don't try to enable both src & dest simultaneously */
1070         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1071                 return -EINVAL;
1072
1073         if (IS_VALLEYVIEW(dev) &&
1074             set->flags & I915_SET_COLORKEY_DESTINATION)
1075                 return -EINVAL;
1076
1077         drm_modeset_lock_all(dev);
1078
1079         plane = drm_plane_find(dev, set->plane_id);
1080         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) {
1081                 ret = -ENOENT;
1082                 goto out_unlock;
1083         }
1084
1085         intel_plane = to_intel_plane(plane);
1086
1087         if (INTEL_INFO(dev)->gen >= 9) {
1088                 /* plane scaling and colorkey are mutually exclusive */
1089                 if (to_intel_plane_state(plane->state)->scaler_id >= 0) {
1090                         DRM_ERROR("colorkey not allowed with scaler\n");
1091                         ret = -EINVAL;
1092                         goto out_unlock;
1093                 }
1094         }
1095
1096         intel_plane->ckey = *set;
1097
1098         /*
1099          * The only way this could fail would be due to
1100          * the current plane state being unsupportable already,
1101          * and we dont't consider that an error for the
1102          * colorkey ioctl. So just ignore any error.
1103          */
1104         intel_plane_restore(plane);
1105
1106 out_unlock:
1107         drm_modeset_unlock_all(dev);
1108         return ret;
1109 }
1110
1111 int intel_plane_restore(struct drm_plane *plane)
1112 {
1113         if (!plane->crtc || !plane->state->fb)
1114                 return 0;
1115
1116         return drm_plane_helper_update(plane, plane->crtc, plane->state->fb,
1117                                        plane->state->crtc_x, plane->state->crtc_y,
1118                                        plane->state->crtc_w, plane->state->crtc_h,
1119                                        plane->state->src_x, plane->state->src_y,
1120                                        plane->state->src_w, plane->state->src_h);
1121 }
1122
1123 static uint32_t ilk_plane_formats[] = {
1124         DRM_FORMAT_XRGB8888,
1125         DRM_FORMAT_YUYV,
1126         DRM_FORMAT_YVYU,
1127         DRM_FORMAT_UYVY,
1128         DRM_FORMAT_VYUY,
1129 };
1130
1131 static uint32_t snb_plane_formats[] = {
1132         DRM_FORMAT_XBGR8888,
1133         DRM_FORMAT_XRGB8888,
1134         DRM_FORMAT_YUYV,
1135         DRM_FORMAT_YVYU,
1136         DRM_FORMAT_UYVY,
1137         DRM_FORMAT_VYUY,
1138 };
1139
1140 static uint32_t vlv_plane_formats[] = {
1141         DRM_FORMAT_RGB565,
1142         DRM_FORMAT_ABGR8888,
1143         DRM_FORMAT_ARGB8888,
1144         DRM_FORMAT_XBGR8888,
1145         DRM_FORMAT_XRGB8888,
1146         DRM_FORMAT_XBGR2101010,
1147         DRM_FORMAT_ABGR2101010,
1148         DRM_FORMAT_YUYV,
1149         DRM_FORMAT_YVYU,
1150         DRM_FORMAT_UYVY,
1151         DRM_FORMAT_VYUY,
1152 };
1153
1154 static uint32_t skl_plane_formats[] = {
1155         DRM_FORMAT_RGB565,
1156         DRM_FORMAT_ABGR8888,
1157         DRM_FORMAT_ARGB8888,
1158         DRM_FORMAT_XBGR8888,
1159         DRM_FORMAT_XRGB8888,
1160         DRM_FORMAT_YUYV,
1161         DRM_FORMAT_YVYU,
1162         DRM_FORMAT_UYVY,
1163         DRM_FORMAT_VYUY,
1164 };
1165
1166 int
1167 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1168 {
1169         struct intel_plane *intel_plane;
1170         struct intel_plane_state *state;
1171         unsigned long possible_crtcs;
1172         const uint32_t *plane_formats;
1173         int num_plane_formats;
1174         int ret;
1175
1176         if (INTEL_INFO(dev)->gen < 5)
1177                 return -ENODEV;
1178
1179         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1180         if (!intel_plane)
1181                 return -ENOMEM;
1182
1183         state = intel_create_plane_state(&intel_plane->base);
1184         if (!state) {
1185                 kfree(intel_plane);
1186                 return -ENOMEM;
1187         }
1188         intel_plane->base.state = &state->base;
1189
1190         switch (INTEL_INFO(dev)->gen) {
1191         case 5:
1192         case 6:
1193                 intel_plane->can_scale = true;
1194                 intel_plane->max_downscale = 16;
1195                 intel_plane->update_plane = ilk_update_plane;
1196                 intel_plane->disable_plane = ilk_disable_plane;
1197
1198                 if (IS_GEN6(dev)) {
1199                         plane_formats = snb_plane_formats;
1200                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1201                 } else {
1202                         plane_formats = ilk_plane_formats;
1203                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1204                 }
1205                 break;
1206
1207         case 7:
1208         case 8:
1209                 if (IS_IVYBRIDGE(dev)) {
1210                         intel_plane->can_scale = true;
1211                         intel_plane->max_downscale = 2;
1212                 } else {
1213                         intel_plane->can_scale = false;
1214                         intel_plane->max_downscale = 1;
1215                 }
1216
1217                 if (IS_VALLEYVIEW(dev)) {
1218                         intel_plane->update_plane = vlv_update_plane;
1219                         intel_plane->disable_plane = vlv_disable_plane;
1220
1221                         plane_formats = vlv_plane_formats;
1222                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1223                 } else {
1224                         intel_plane->update_plane = ivb_update_plane;
1225                         intel_plane->disable_plane = ivb_disable_plane;
1226
1227                         plane_formats = snb_plane_formats;
1228                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1229                 }
1230                 break;
1231         case 9:
1232                 intel_plane->can_scale = true;
1233                 intel_plane->update_plane = skl_update_plane;
1234                 intel_plane->disable_plane = skl_disable_plane;
1235                 state->scaler_id = -1;
1236
1237                 plane_formats = skl_plane_formats;
1238                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1239                 break;
1240         default:
1241                 kfree(intel_plane);
1242                 return -ENODEV;
1243         }
1244
1245         intel_plane->pipe = pipe;
1246         intel_plane->plane = plane;
1247         intel_plane->check_plane = intel_check_sprite_plane;
1248         intel_plane->commit_plane = intel_commit_sprite_plane;
1249         intel_plane->ckey.flags = I915_SET_COLORKEY_NONE;
1250         possible_crtcs = (1 << pipe);
1251         ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1252                                        &intel_plane_funcs,
1253                                        plane_formats, num_plane_formats,
1254                                        DRM_PLANE_TYPE_OVERLAY);
1255         if (ret) {
1256                 kfree(intel_plane);
1257                 goto out;
1258         }
1259
1260         intel_create_rotation_property(dev, intel_plane);
1261
1262         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1263
1264  out:
1265         return ret;
1266 }