2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
34 #include "drm_fourcc.h"
35 #include "intel_drv.h"
40 ivb_update_plane(struct drm_plane
*plane
, struct drm_framebuffer
*fb
,
41 struct drm_i915_gem_object
*obj
, int crtc_x
, int crtc_y
,
42 unsigned int crtc_w
, unsigned int crtc_h
,
43 uint32_t x
, uint32_t y
,
44 uint32_t src_w
, uint32_t src_h
)
46 struct drm_device
*dev
= plane
->dev
;
47 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
48 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
49 int pipe
= intel_plane
->pipe
;
50 u32 sprctl
, sprscale
= 0;
53 sprctl
= I915_READ(SPRCTL(pipe
));
55 /* Mask out pixel format bits in case we change it */
56 sprctl
&= ~SPRITE_PIXFORMAT_MASK
;
57 sprctl
&= ~SPRITE_RGB_ORDER_RGBX
;
58 sprctl
&= ~SPRITE_YUV_BYTE_ORDER_MASK
;
60 switch (fb
->pixel_format
) {
61 case DRM_FORMAT_XBGR8888
:
62 sprctl
|= SPRITE_FORMAT_RGBX888
;
65 case DRM_FORMAT_XRGB8888
:
66 sprctl
|= SPRITE_FORMAT_RGBX888
| SPRITE_RGB_ORDER_RGBX
;
70 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YUYV
;
74 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YVYU
;
78 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_UYVY
;
82 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_VYUY
;
86 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
87 sprctl
|= DVS_FORMAT_RGBX888
;
92 if (obj
->tiling_mode
!= I915_TILING_NONE
)
93 sprctl
|= SPRITE_TILED
;
96 sprctl
|= SPRITE_TRICKLE_FEED_DISABLE
;
97 sprctl
|= SPRITE_ENABLE
;
99 /* Sizes are 0 based */
105 intel_update_sprite_watermarks(dev
, pipe
, crtc_w
, pixel_size
);
108 * IVB workaround: must disable low power watermarks for at least
109 * one frame before enabling scaling. LP watermarks can be re-enabled
110 * when scaling is disabled.
112 if (crtc_w
!= src_w
|| crtc_h
!= src_h
) {
113 if (!dev_priv
->sprite_scaling_enabled
) {
114 dev_priv
->sprite_scaling_enabled
= true;
115 intel_update_watermarks(dev
);
116 intel_wait_for_vblank(dev
, pipe
);
118 sprscale
= SPRITE_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
120 if (dev_priv
->sprite_scaling_enabled
) {
121 dev_priv
->sprite_scaling_enabled
= false;
122 /* potentially re-enable LP watermarks */
123 intel_update_watermarks(dev
);
127 I915_WRITE(SPRSTRIDE(pipe
), fb
->pitches
[0]);
128 I915_WRITE(SPRPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
129 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
130 I915_WRITE(SPRTILEOFF(pipe
), (y
<< 16) | x
);
132 unsigned long offset
;
134 offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
135 I915_WRITE(SPRLINOFF(pipe
), offset
);
137 I915_WRITE(SPRSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
138 I915_WRITE(SPRSCALE(pipe
), sprscale
);
139 I915_WRITE(SPRCTL(pipe
), sprctl
);
140 I915_MODIFY_DISPBASE(SPRSURF(pipe
), obj
->gtt_offset
);
141 POSTING_READ(SPRSURF(pipe
));
145 ivb_disable_plane(struct drm_plane
*plane
)
147 struct drm_device
*dev
= plane
->dev
;
148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
150 int pipe
= intel_plane
->pipe
;
152 I915_WRITE(SPRCTL(pipe
), I915_READ(SPRCTL(pipe
)) & ~SPRITE_ENABLE
);
153 /* Can't leave the scaler enabled... */
154 I915_WRITE(SPRSCALE(pipe
), 0);
155 /* Activate double buffered register update */
156 I915_MODIFY_DISPBASE(SPRSURF(pipe
), 0);
157 POSTING_READ(SPRSURF(pipe
));
159 dev_priv
->sprite_scaling_enabled
= false;
160 intel_update_watermarks(dev
);
164 ivb_update_colorkey(struct drm_plane
*plane
,
165 struct drm_intel_sprite_colorkey
*key
)
167 struct drm_device
*dev
= plane
->dev
;
168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
169 struct intel_plane
*intel_plane
;
173 intel_plane
= to_intel_plane(plane
);
175 I915_WRITE(SPRKEYVAL(intel_plane
->pipe
), key
->min_value
);
176 I915_WRITE(SPRKEYMAX(intel_plane
->pipe
), key
->max_value
);
177 I915_WRITE(SPRKEYMSK(intel_plane
->pipe
), key
->channel_mask
);
179 sprctl
= I915_READ(SPRCTL(intel_plane
->pipe
));
180 sprctl
&= ~(SPRITE_SOURCE_KEY
| SPRITE_DEST_KEY
);
181 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
182 sprctl
|= SPRITE_DEST_KEY
;
183 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
184 sprctl
|= SPRITE_SOURCE_KEY
;
185 I915_WRITE(SPRCTL(intel_plane
->pipe
), sprctl
);
187 POSTING_READ(SPRKEYMSK(intel_plane
->pipe
));
193 ivb_get_colorkey(struct drm_plane
*plane
, struct drm_intel_sprite_colorkey
*key
)
195 struct drm_device
*dev
= plane
->dev
;
196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
197 struct intel_plane
*intel_plane
;
200 intel_plane
= to_intel_plane(plane
);
202 key
->min_value
= I915_READ(SPRKEYVAL(intel_plane
->pipe
));
203 key
->max_value
= I915_READ(SPRKEYMAX(intel_plane
->pipe
));
204 key
->channel_mask
= I915_READ(SPRKEYMSK(intel_plane
->pipe
));
207 sprctl
= I915_READ(SPRCTL(intel_plane
->pipe
));
209 if (sprctl
& SPRITE_DEST_KEY
)
210 key
->flags
= I915_SET_COLORKEY_DESTINATION
;
211 else if (sprctl
& SPRITE_SOURCE_KEY
)
212 key
->flags
= I915_SET_COLORKEY_SOURCE
;
214 key
->flags
= I915_SET_COLORKEY_NONE
;
218 ilk_update_plane(struct drm_plane
*plane
, struct drm_framebuffer
*fb
,
219 struct drm_i915_gem_object
*obj
, int crtc_x
, int crtc_y
,
220 unsigned int crtc_w
, unsigned int crtc_h
,
221 uint32_t x
, uint32_t y
,
222 uint32_t src_w
, uint32_t src_h
)
224 struct drm_device
*dev
= plane
->dev
;
225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
226 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
227 int pipe
= intel_plane
->pipe
, pixel_size
;
228 u32 dvscntr
, dvsscale
;
230 dvscntr
= I915_READ(DVSCNTR(pipe
));
232 /* Mask out pixel format bits in case we change it */
233 dvscntr
&= ~DVS_PIXFORMAT_MASK
;
234 dvscntr
&= ~DVS_RGB_ORDER_XBGR
;
235 dvscntr
&= ~DVS_YUV_BYTE_ORDER_MASK
;
237 switch (fb
->pixel_format
) {
238 case DRM_FORMAT_XBGR8888
:
239 dvscntr
|= DVS_FORMAT_RGBX888
| DVS_RGB_ORDER_XBGR
;
242 case DRM_FORMAT_XRGB8888
:
243 dvscntr
|= DVS_FORMAT_RGBX888
;
246 case DRM_FORMAT_YUYV
:
247 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YUYV
;
250 case DRM_FORMAT_YVYU
:
251 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YVYU
;
254 case DRM_FORMAT_UYVY
:
255 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_UYVY
;
258 case DRM_FORMAT_VYUY
:
259 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_VYUY
;
263 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
264 dvscntr
|= DVS_FORMAT_RGBX888
;
269 if (obj
->tiling_mode
!= I915_TILING_NONE
)
270 dvscntr
|= DVS_TILED
;
273 dvscntr
|= DVS_TRICKLE_FEED_DISABLE
; /* must disable */
274 dvscntr
|= DVS_ENABLE
;
276 /* Sizes are 0 based */
282 intel_update_sprite_watermarks(dev
, pipe
, crtc_w
, pixel_size
);
285 if (IS_GEN5(dev
) || crtc_w
!= src_w
|| crtc_h
!= src_h
)
286 dvsscale
= DVS_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
288 I915_WRITE(DVSSTRIDE(pipe
), fb
->pitches
[0]);
289 I915_WRITE(DVSPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
290 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
291 I915_WRITE(DVSTILEOFF(pipe
), (y
<< 16) | x
);
293 unsigned long offset
;
295 offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
296 I915_WRITE(DVSLINOFF(pipe
), offset
);
298 I915_WRITE(DVSSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
299 I915_WRITE(DVSSCALE(pipe
), dvsscale
);
300 I915_WRITE(DVSCNTR(pipe
), dvscntr
);
301 I915_MODIFY_DISPBASE(DVSSURF(pipe
), obj
->gtt_offset
);
302 POSTING_READ(DVSSURF(pipe
));
306 ilk_disable_plane(struct drm_plane
*plane
)
308 struct drm_device
*dev
= plane
->dev
;
309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
310 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
311 int pipe
= intel_plane
->pipe
;
313 I915_WRITE(DVSCNTR(pipe
), I915_READ(DVSCNTR(pipe
)) & ~DVS_ENABLE
);
314 /* Disable the scaler */
315 I915_WRITE(DVSSCALE(pipe
), 0);
316 /* Flush double buffered register updates */
317 I915_MODIFY_DISPBASE(DVSSURF(pipe
), 0);
318 POSTING_READ(DVSSURF(pipe
));
322 intel_enable_primary(struct drm_crtc
*crtc
)
324 struct drm_device
*dev
= crtc
->dev
;
325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
326 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
327 int reg
= DSPCNTR(intel_crtc
->plane
);
329 if (!intel_crtc
->primary_disabled
)
332 intel_crtc
->primary_disabled
= false;
333 intel_update_fbc(dev
);
335 I915_WRITE(reg
, I915_READ(reg
) | DISPLAY_PLANE_ENABLE
);
339 intel_disable_primary(struct drm_crtc
*crtc
)
341 struct drm_device
*dev
= crtc
->dev
;
342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
343 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
344 int reg
= DSPCNTR(intel_crtc
->plane
);
346 if (intel_crtc
->primary_disabled
)
349 I915_WRITE(reg
, I915_READ(reg
) & ~DISPLAY_PLANE_ENABLE
);
351 intel_crtc
->primary_disabled
= true;
352 intel_update_fbc(dev
);
356 ilk_update_colorkey(struct drm_plane
*plane
,
357 struct drm_intel_sprite_colorkey
*key
)
359 struct drm_device
*dev
= plane
->dev
;
360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
361 struct intel_plane
*intel_plane
;
365 intel_plane
= to_intel_plane(plane
);
367 I915_WRITE(DVSKEYVAL(intel_plane
->pipe
), key
->min_value
);
368 I915_WRITE(DVSKEYMAX(intel_plane
->pipe
), key
->max_value
);
369 I915_WRITE(DVSKEYMSK(intel_plane
->pipe
), key
->channel_mask
);
371 dvscntr
= I915_READ(DVSCNTR(intel_plane
->pipe
));
372 dvscntr
&= ~(DVS_SOURCE_KEY
| DVS_DEST_KEY
);
373 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
374 dvscntr
|= DVS_DEST_KEY
;
375 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
376 dvscntr
|= DVS_SOURCE_KEY
;
377 I915_WRITE(DVSCNTR(intel_plane
->pipe
), dvscntr
);
379 POSTING_READ(DVSKEYMSK(intel_plane
->pipe
));
385 ilk_get_colorkey(struct drm_plane
*plane
, struct drm_intel_sprite_colorkey
*key
)
387 struct drm_device
*dev
= plane
->dev
;
388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
389 struct intel_plane
*intel_plane
;
392 intel_plane
= to_intel_plane(plane
);
394 key
->min_value
= I915_READ(DVSKEYVAL(intel_plane
->pipe
));
395 key
->max_value
= I915_READ(DVSKEYMAX(intel_plane
->pipe
));
396 key
->channel_mask
= I915_READ(DVSKEYMSK(intel_plane
->pipe
));
399 dvscntr
= I915_READ(DVSCNTR(intel_plane
->pipe
));
401 if (dvscntr
& DVS_DEST_KEY
)
402 key
->flags
= I915_SET_COLORKEY_DESTINATION
;
403 else if (dvscntr
& DVS_SOURCE_KEY
)
404 key
->flags
= I915_SET_COLORKEY_SOURCE
;
406 key
->flags
= I915_SET_COLORKEY_NONE
;
410 intel_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
411 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
412 unsigned int crtc_w
, unsigned int crtc_h
,
413 uint32_t src_x
, uint32_t src_y
,
414 uint32_t src_w
, uint32_t src_h
)
416 struct drm_device
*dev
= plane
->dev
;
417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
418 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
419 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
420 struct intel_framebuffer
*intel_fb
;
421 struct drm_i915_gem_object
*obj
, *old_obj
;
422 int pipe
= intel_plane
->pipe
;
424 int x
= src_x
>> 16, y
= src_y
>> 16;
425 int primary_w
= crtc
->mode
.hdisplay
, primary_h
= crtc
->mode
.vdisplay
;
426 bool disable_primary
= false;
428 intel_fb
= to_intel_framebuffer(fb
);
431 old_obj
= intel_plane
->obj
;
436 /* Pipe must be running... */
437 if (!(I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
))
440 if (crtc_x
>= primary_w
|| crtc_y
>= primary_h
)
443 /* Don't modify another pipe's plane */
444 if (intel_plane
->pipe
!= intel_crtc
->pipe
)
448 * Clamp the width & height into the visible area. Note we don't
449 * try to scale the source if part of the visible region is offscreen.
450 * The caller must handle that by adjusting source offset and size.
452 if ((crtc_x
< 0) && ((crtc_x
+ crtc_w
) > 0)) {
456 if ((crtc_x
+ crtc_w
) <= 0) /* Nothing to display */
458 if ((crtc_x
+ crtc_w
) > primary_w
)
459 crtc_w
= primary_w
- crtc_x
;
461 if ((crtc_y
< 0) && ((crtc_y
+ crtc_h
) > 0)) {
465 if ((crtc_y
+ crtc_h
) <= 0) /* Nothing to display */
467 if (crtc_y
+ crtc_h
> primary_h
)
468 crtc_h
= primary_h
- crtc_y
;
470 if (!crtc_w
|| !crtc_h
) /* Again, nothing to display */
474 * We can take a larger source and scale it down, but
475 * only so much... 16x is the max on SNB.
477 if (((src_w
* src_h
) / (crtc_w
* crtc_h
)) > intel_plane
->max_downscale
)
481 * If the sprite is completely covering the primary plane,
482 * we can disable the primary and save power.
484 if ((crtc_x
== 0) && (crtc_y
== 0) &&
485 (crtc_w
== primary_w
) && (crtc_h
== primary_h
))
486 disable_primary
= true;
488 mutex_lock(&dev
->struct_mutex
);
490 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
494 intel_plane
->obj
= obj
;
497 * Be sure to re-enable the primary before the sprite is no longer
500 if (!disable_primary
)
501 intel_enable_primary(crtc
);
503 intel_plane
->update_plane(plane
, fb
, obj
, crtc_x
, crtc_y
,
504 crtc_w
, crtc_h
, x
, y
, src_w
, src_h
);
507 intel_disable_primary(crtc
);
509 /* Unpin old obj after new one is active to avoid ugliness */
512 * It's fairly common to simply update the position of
513 * an existing object. In that case, we don't need to
514 * wait for vblank to avoid ugliness, we only need to
515 * do the pin & ref bookkeeping.
517 if (old_obj
!= obj
) {
518 mutex_unlock(&dev
->struct_mutex
);
519 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
520 mutex_lock(&dev
->struct_mutex
);
522 intel_unpin_fb_obj(old_obj
);
526 mutex_unlock(&dev
->struct_mutex
);
532 intel_disable_plane(struct drm_plane
*plane
)
534 struct drm_device
*dev
= plane
->dev
;
535 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
539 intel_enable_primary(plane
->crtc
);
540 intel_plane
->disable_plane(plane
);
542 if (!intel_plane
->obj
)
545 mutex_lock(&dev
->struct_mutex
);
546 intel_unpin_fb_obj(intel_plane
->obj
);
547 intel_plane
->obj
= NULL
;
548 mutex_unlock(&dev
->struct_mutex
);
554 static void intel_destroy_plane(struct drm_plane
*plane
)
556 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
557 intel_disable_plane(plane
);
558 drm_plane_cleanup(plane
);
562 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
563 struct drm_file
*file_priv
)
565 struct drm_intel_sprite_colorkey
*set
= data
;
566 struct drm_mode_object
*obj
;
567 struct drm_plane
*plane
;
568 struct intel_plane
*intel_plane
;
571 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
574 /* Make sure we don't try to enable both src & dest simultaneously */
575 if ((set
->flags
& (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
)) == (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
))
578 mutex_lock(&dev
->mode_config
.mutex
);
580 obj
= drm_mode_object_find(dev
, set
->plane_id
, DRM_MODE_OBJECT_PLANE
);
586 plane
= obj_to_plane(obj
);
587 intel_plane
= to_intel_plane(plane
);
588 ret
= intel_plane
->update_colorkey(plane
, set
);
591 mutex_unlock(&dev
->mode_config
.mutex
);
595 int intel_sprite_get_colorkey(struct drm_device
*dev
, void *data
,
596 struct drm_file
*file_priv
)
598 struct drm_intel_sprite_colorkey
*get
= data
;
599 struct drm_mode_object
*obj
;
600 struct drm_plane
*plane
;
601 struct intel_plane
*intel_plane
;
604 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
607 mutex_lock(&dev
->mode_config
.mutex
);
609 obj
= drm_mode_object_find(dev
, get
->plane_id
, DRM_MODE_OBJECT_PLANE
);
615 plane
= obj_to_plane(obj
);
616 intel_plane
= to_intel_plane(plane
);
617 intel_plane
->get_colorkey(plane
, get
);
620 mutex_unlock(&dev
->mode_config
.mutex
);
624 static const struct drm_plane_funcs intel_plane_funcs
= {
625 .update_plane
= intel_update_plane
,
626 .disable_plane
= intel_disable_plane
,
627 .destroy
= intel_destroy_plane
,
630 static uint32_t ilk_plane_formats
[] = {
638 static uint32_t snb_plane_formats
[] = {
648 intel_plane_init(struct drm_device
*dev
, enum pipe pipe
)
650 struct intel_plane
*intel_plane
;
651 unsigned long possible_crtcs
;
652 const uint32_t *plane_formats
;
653 int num_plane_formats
;
656 if (INTEL_INFO(dev
)->gen
< 5)
659 intel_plane
= kzalloc(sizeof(struct intel_plane
), GFP_KERNEL
);
663 switch (INTEL_INFO(dev
)->gen
) {
666 intel_plane
->max_downscale
= 16;
667 intel_plane
->update_plane
= ilk_update_plane
;
668 intel_plane
->disable_plane
= ilk_disable_plane
;
669 intel_plane
->update_colorkey
= ilk_update_colorkey
;
670 intel_plane
->get_colorkey
= ilk_get_colorkey
;
673 plane_formats
= snb_plane_formats
;
674 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
676 plane_formats
= ilk_plane_formats
;
677 num_plane_formats
= ARRAY_SIZE(ilk_plane_formats
);
682 intel_plane
->max_downscale
= 2;
683 intel_plane
->update_plane
= ivb_update_plane
;
684 intel_plane
->disable_plane
= ivb_disable_plane
;
685 intel_plane
->update_colorkey
= ivb_update_colorkey
;
686 intel_plane
->get_colorkey
= ivb_get_colorkey
;
688 plane_formats
= snb_plane_formats
;
689 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
696 intel_plane
->pipe
= pipe
;
697 possible_crtcs
= (1 << pipe
);
698 ret
= drm_plane_init(dev
, &intel_plane
->base
, possible_crtcs
,
700 plane_formats
, num_plane_formats
,