2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
41 format_is_yuv(uint32_t format
)
54 static int usecs_to_scanlines(const struct drm_display_mode
*mode
, int usecs
)
57 if (!mode
->crtc_htotal
)
60 return DIV_ROUND_UP(usecs
* mode
->crtc_clock
, 1000 * mode
->crtc_htotal
);
63 static bool intel_pipe_update_start(struct intel_crtc
*crtc
, uint32_t *start_vbl_count
)
65 struct drm_device
*dev
= crtc
->base
.dev
;
66 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
67 enum pipe pipe
= crtc
->pipe
;
68 long timeout
= msecs_to_jiffies_timeout(1);
69 int scanline
, min
, max
, vblank_start
;
70 wait_queue_head_t
*wq
= drm_crtc_vblank_waitqueue(&crtc
->base
);
73 WARN_ON(!drm_modeset_is_locked(&crtc
->base
.mutex
));
75 vblank_start
= mode
->crtc_vblank_start
;
76 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
77 vblank_start
= DIV_ROUND_UP(vblank_start
, 2);
79 /* FIXME needs to be calibrated sensibly */
80 min
= vblank_start
- usecs_to_scanlines(mode
, 100);
81 max
= vblank_start
- 1;
83 if (min
<= 0 || max
<= 0)
86 if (WARN_ON(drm_vblank_get(dev
, pipe
)))
91 trace_i915_pipe_update_start(crtc
, min
, max
);
95 * prepare_to_wait() has a memory barrier, which guarantees
96 * other CPUs can see the task state update by the time we
99 prepare_to_wait(wq
, &wait
, TASK_UNINTERRUPTIBLE
);
101 scanline
= intel_get_crtc_scanline(crtc
);
102 if (scanline
< min
|| scanline
> max
)
106 DRM_ERROR("Potential atomic update failure on pipe %c\n",
107 pipe_name(crtc
->pipe
));
113 timeout
= schedule_timeout(timeout
);
118 finish_wait(wq
, &wait
);
120 drm_vblank_put(dev
, pipe
);
122 *start_vbl_count
= dev
->driver
->get_vblank_counter(dev
, pipe
);
124 trace_i915_pipe_update_vblank_evaded(crtc
, min
, max
, *start_vbl_count
);
129 static void intel_pipe_update_end(struct intel_crtc
*crtc
, u32 start_vbl_count
)
131 struct drm_device
*dev
= crtc
->base
.dev
;
132 enum pipe pipe
= crtc
->pipe
;
133 u32 end_vbl_count
= dev
->driver
->get_vblank_counter(dev
, pipe
);
135 trace_i915_pipe_update_end(crtc
, end_vbl_count
);
139 if (start_vbl_count
!= end_vbl_count
)
140 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
141 pipe_name(pipe
), start_vbl_count
, end_vbl_count
);
144 static void intel_update_primary_plane(struct intel_crtc
*crtc
)
146 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
147 int reg
= DSPCNTR(crtc
->plane
);
149 if (crtc
->primary_enabled
)
150 I915_WRITE(reg
, I915_READ(reg
) | DISPLAY_PLANE_ENABLE
);
152 I915_WRITE(reg
, I915_READ(reg
) & ~DISPLAY_PLANE_ENABLE
);
156 skl_update_plane(struct drm_plane
*drm_plane
, struct drm_crtc
*crtc
,
157 struct drm_framebuffer
*fb
,
158 struct drm_i915_gem_object
*obj
, int crtc_x
, int crtc_y
,
159 unsigned int crtc_w
, unsigned int crtc_h
,
160 uint32_t x
, uint32_t y
,
161 uint32_t src_w
, uint32_t src_h
)
163 struct drm_device
*dev
= drm_plane
->dev
;
164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
165 struct intel_plane
*intel_plane
= to_intel_plane(drm_plane
);
166 const int pipe
= intel_plane
->pipe
;
167 const int plane
= intel_plane
->plane
+ 1;
168 u32 plane_ctl
, stride
;
169 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
171 plane_ctl
= I915_READ(PLANE_CTL(pipe
, plane
));
173 /* Mask out pixel format bits in case we change it */
174 plane_ctl
&= ~PLANE_CTL_FORMAT_MASK
;
175 plane_ctl
&= ~PLANE_CTL_ORDER_RGBX
;
176 plane_ctl
&= ~PLANE_CTL_YUV422_ORDER_MASK
;
177 plane_ctl
&= ~PLANE_CTL_TILED_MASK
;
178 plane_ctl
&= ~PLANE_CTL_ALPHA_MASK
;
179 plane_ctl
&= ~PLANE_CTL_ROTATE_MASK
;
181 /* Trickle feed has to be enabled */
182 plane_ctl
&= ~PLANE_CTL_TRICKLE_FEED_DISABLE
;
184 switch (fb
->pixel_format
) {
185 case DRM_FORMAT_RGB565
:
186 plane_ctl
|= PLANE_CTL_FORMAT_RGB_565
;
188 case DRM_FORMAT_XBGR8888
:
189 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
191 case DRM_FORMAT_XRGB8888
:
192 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
195 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
196 * to be already pre-multiplied. We need to add a knob (or a different
197 * DRM_FORMAT) for user-space to configure that.
199 case DRM_FORMAT_ABGR8888
:
200 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
|
201 PLANE_CTL_ORDER_RGBX
|
202 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
204 case DRM_FORMAT_ARGB8888
:
205 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
|
206 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
208 case DRM_FORMAT_YUYV
:
209 plane_ctl
|= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
211 case DRM_FORMAT_YVYU
:
212 plane_ctl
|= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
214 case DRM_FORMAT_UYVY
:
215 plane_ctl
|= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
217 case DRM_FORMAT_VYUY
:
218 plane_ctl
|= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
224 switch (obj
->tiling_mode
) {
225 case I915_TILING_NONE
:
226 stride
= fb
->pitches
[0] >> 6;
229 plane_ctl
|= PLANE_CTL_TILED_X
;
230 stride
= fb
->pitches
[0] >> 9;
235 if (intel_plane
->rotation
== BIT(DRM_ROTATE_180
))
236 plane_ctl
|= PLANE_CTL_ROTATE_180
;
238 plane_ctl
|= PLANE_CTL_ENABLE
;
239 plane_ctl
|= PLANE_CTL_PIPE_CSC_ENABLE
;
241 intel_update_sprite_watermarks(drm_plane
, crtc
, src_w
, src_h
,
243 src_w
!= crtc_w
|| src_h
!= crtc_h
);
245 /* Sizes are 0 based */
251 I915_WRITE(PLANE_OFFSET(pipe
, plane
), (y
<< 16) | x
);
252 I915_WRITE(PLANE_STRIDE(pipe
, plane
), stride
);
253 I915_WRITE(PLANE_POS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
254 I915_WRITE(PLANE_SIZE(pipe
, plane
), (crtc_h
<< 16) | crtc_w
);
255 I915_WRITE(PLANE_CTL(pipe
, plane
), plane_ctl
);
256 I915_WRITE(PLANE_SURF(pipe
, plane
), i915_gem_obj_ggtt_offset(obj
));
257 POSTING_READ(PLANE_SURF(pipe
, plane
));
261 skl_disable_plane(struct drm_plane
*drm_plane
, struct drm_crtc
*crtc
)
263 struct drm_device
*dev
= drm_plane
->dev
;
264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
265 struct intel_plane
*intel_plane
= to_intel_plane(drm_plane
);
266 const int pipe
= intel_plane
->pipe
;
267 const int plane
= intel_plane
->plane
+ 1;
269 I915_WRITE(PLANE_CTL(pipe
, plane
),
270 I915_READ(PLANE_CTL(pipe
, plane
)) & ~PLANE_CTL_ENABLE
);
272 /* Activate double buffered register update */
273 I915_WRITE(PLANE_CTL(pipe
, plane
), 0);
274 POSTING_READ(PLANE_CTL(pipe
, plane
));
276 intel_update_sprite_watermarks(drm_plane
, crtc
, 0, 0, 0, false, false);
280 skl_update_colorkey(struct drm_plane
*drm_plane
,
281 struct drm_intel_sprite_colorkey
*key
)
283 struct drm_device
*dev
= drm_plane
->dev
;
284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
285 struct intel_plane
*intel_plane
= to_intel_plane(drm_plane
);
286 const int pipe
= intel_plane
->pipe
;
287 const int plane
= intel_plane
->plane
;
290 I915_WRITE(PLANE_KEYVAL(pipe
, plane
), key
->min_value
);
291 I915_WRITE(PLANE_KEYMAX(pipe
, plane
), key
->max_value
);
292 I915_WRITE(PLANE_KEYMSK(pipe
, plane
), key
->channel_mask
);
294 plane_ctl
= I915_READ(PLANE_CTL(pipe
, plane
));
295 plane_ctl
&= ~PLANE_CTL_KEY_ENABLE_MASK
;
296 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
297 plane_ctl
|= PLANE_CTL_KEY_ENABLE_DESTINATION
;
298 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
299 plane_ctl
|= PLANE_CTL_KEY_ENABLE_SOURCE
;
300 I915_WRITE(PLANE_CTL(pipe
, plane
), plane_ctl
);
302 POSTING_READ(PLANE_CTL(pipe
, plane
));
308 skl_get_colorkey(struct drm_plane
*drm_plane
,
309 struct drm_intel_sprite_colorkey
*key
)
311 struct drm_device
*dev
= drm_plane
->dev
;
312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
313 struct intel_plane
*intel_plane
= to_intel_plane(drm_plane
);
314 const int pipe
= intel_plane
->pipe
;
315 const int plane
= intel_plane
->plane
;
318 key
->min_value
= I915_READ(PLANE_KEYVAL(pipe
, plane
));
319 key
->max_value
= I915_READ(PLANE_KEYMAX(pipe
, plane
));
320 key
->channel_mask
= I915_READ(PLANE_KEYMSK(pipe
, plane
));
322 plane_ctl
= I915_READ(PLANE_CTL(pipe
, plane
));
324 switch (plane_ctl
& PLANE_CTL_KEY_ENABLE_MASK
) {
325 case PLANE_CTL_KEY_ENABLE_DESTINATION
:
326 key
->flags
= I915_SET_COLORKEY_DESTINATION
;
328 case PLANE_CTL_KEY_ENABLE_SOURCE
:
329 key
->flags
= I915_SET_COLORKEY_SOURCE
;
332 key
->flags
= I915_SET_COLORKEY_NONE
;
337 chv_update_csc(struct intel_plane
*intel_plane
, uint32_t format
)
339 struct drm_i915_private
*dev_priv
= intel_plane
->base
.dev
->dev_private
;
340 int plane
= intel_plane
->plane
;
342 /* Seems RGB data bypasses the CSC always */
343 if (!format_is_yuv(format
))
347 * BT.601 limited range YCbCr -> full range RGB
349 * |r| | 6537 4769 0| |cr |
350 * |g| = |-3330 4769 -1605| x |y-64|
351 * |b| | 0 4769 8263| |cb |
353 * Cb and Cr apparently come in as signed already, so no
354 * need for any offset. For Y we need to remove the offset.
356 I915_WRITE(SPCSCYGOFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
357 I915_WRITE(SPCSCCBOFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
358 I915_WRITE(SPCSCCROFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
360 I915_WRITE(SPCSCC01(plane
), SPCSC_C1(4769) | SPCSC_C0(6537));
361 I915_WRITE(SPCSCC23(plane
), SPCSC_C1(-3330) | SPCSC_C0(0));
362 I915_WRITE(SPCSCC45(plane
), SPCSC_C1(-1605) | SPCSC_C0(4769));
363 I915_WRITE(SPCSCC67(plane
), SPCSC_C1(4769) | SPCSC_C0(0));
364 I915_WRITE(SPCSCC8(plane
), SPCSC_C0(8263));
366 I915_WRITE(SPCSCYGICLAMP(plane
), SPCSC_IMAX(940) | SPCSC_IMIN(64));
367 I915_WRITE(SPCSCCBICLAMP(plane
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
368 I915_WRITE(SPCSCCRICLAMP(plane
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
370 I915_WRITE(SPCSCYGOCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
371 I915_WRITE(SPCSCCBOCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
372 I915_WRITE(SPCSCCROCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
376 vlv_update_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
,
377 struct drm_framebuffer
*fb
,
378 struct drm_i915_gem_object
*obj
, int crtc_x
, int crtc_y
,
379 unsigned int crtc_w
, unsigned int crtc_h
,
380 uint32_t x
, uint32_t y
,
381 uint32_t src_w
, uint32_t src_h
)
383 struct drm_device
*dev
= dplane
->dev
;
384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
385 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
386 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
387 int pipe
= intel_plane
->pipe
;
388 int plane
= intel_plane
->plane
;
390 unsigned long sprsurf_offset
, linear_offset
;
391 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
395 sprctl
= I915_READ(SPCNTR(pipe
, plane
));
397 /* Mask out pixel format bits in case we change it */
398 sprctl
&= ~SP_PIXFORMAT_MASK
;
399 sprctl
&= ~SP_YUV_BYTE_ORDER_MASK
;
401 sprctl
&= ~SP_ROTATE_180
;
403 switch (fb
->pixel_format
) {
404 case DRM_FORMAT_YUYV
:
405 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YUYV
;
407 case DRM_FORMAT_YVYU
:
408 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YVYU
;
410 case DRM_FORMAT_UYVY
:
411 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_UYVY
;
413 case DRM_FORMAT_VYUY
:
414 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_VYUY
;
416 case DRM_FORMAT_RGB565
:
417 sprctl
|= SP_FORMAT_BGR565
;
419 case DRM_FORMAT_XRGB8888
:
420 sprctl
|= SP_FORMAT_BGRX8888
;
422 case DRM_FORMAT_ARGB8888
:
423 sprctl
|= SP_FORMAT_BGRA8888
;
425 case DRM_FORMAT_XBGR2101010
:
426 sprctl
|= SP_FORMAT_RGBX1010102
;
428 case DRM_FORMAT_ABGR2101010
:
429 sprctl
|= SP_FORMAT_RGBA1010102
;
431 case DRM_FORMAT_XBGR8888
:
432 sprctl
|= SP_FORMAT_RGBX8888
;
434 case DRM_FORMAT_ABGR8888
:
435 sprctl
|= SP_FORMAT_RGBA8888
;
439 * If we get here one of the upper layers failed to filter
440 * out the unsupported plane formats
447 * Enable gamma to match primary/cursor plane behaviour.
448 * FIXME should be user controllable via propertiesa.
450 sprctl
|= SP_GAMMA_ENABLE
;
452 if (obj
->tiling_mode
!= I915_TILING_NONE
)
457 intel_update_sprite_watermarks(dplane
, crtc
, src_w
, src_h
,
459 src_w
!= crtc_w
|| src_h
!= crtc_h
);
461 /* Sizes are 0 based */
467 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
468 sprsurf_offset
= intel_gen4_compute_page_offset(&x
, &y
,
472 linear_offset
-= sprsurf_offset
;
474 if (intel_plane
->rotation
== BIT(DRM_ROTATE_180
)) {
475 sprctl
|= SP_ROTATE_180
;
479 linear_offset
+= src_h
* fb
->pitches
[0] + src_w
* pixel_size
;
482 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
484 intel_update_primary_plane(intel_crtc
);
486 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
)
487 chv_update_csc(intel_plane
, fb
->pixel_format
);
489 I915_WRITE(SPSTRIDE(pipe
, plane
), fb
->pitches
[0]);
490 I915_WRITE(SPPOS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
492 if (obj
->tiling_mode
!= I915_TILING_NONE
)
493 I915_WRITE(SPTILEOFF(pipe
, plane
), (y
<< 16) | x
);
495 I915_WRITE(SPLINOFF(pipe
, plane
), linear_offset
);
497 I915_WRITE(SPCONSTALPHA(pipe
, plane
), 0);
499 I915_WRITE(SPSIZE(pipe
, plane
), (crtc_h
<< 16) | crtc_w
);
500 I915_WRITE(SPCNTR(pipe
, plane
), sprctl
);
501 I915_WRITE(SPSURF(pipe
, plane
), i915_gem_obj_ggtt_offset(obj
) +
504 intel_flush_primary_plane(dev_priv
, intel_crtc
->plane
);
507 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
511 vlv_disable_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
)
513 struct drm_device
*dev
= dplane
->dev
;
514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
515 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
516 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
517 int pipe
= intel_plane
->pipe
;
518 int plane
= intel_plane
->plane
;
522 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
524 intel_update_primary_plane(intel_crtc
);
526 I915_WRITE(SPCNTR(pipe
, plane
), I915_READ(SPCNTR(pipe
, plane
)) &
528 /* Activate double buffered register update */
529 I915_WRITE(SPSURF(pipe
, plane
), 0);
531 intel_flush_primary_plane(dev_priv
, intel_crtc
->plane
);
534 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
536 intel_update_sprite_watermarks(dplane
, crtc
, 0, 0, 0, false, false);
540 vlv_update_colorkey(struct drm_plane
*dplane
,
541 struct drm_intel_sprite_colorkey
*key
)
543 struct drm_device
*dev
= dplane
->dev
;
544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
545 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
546 int pipe
= intel_plane
->pipe
;
547 int plane
= intel_plane
->plane
;
550 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
553 I915_WRITE(SPKEYMINVAL(pipe
, plane
), key
->min_value
);
554 I915_WRITE(SPKEYMAXVAL(pipe
, plane
), key
->max_value
);
555 I915_WRITE(SPKEYMSK(pipe
, plane
), key
->channel_mask
);
557 sprctl
= I915_READ(SPCNTR(pipe
, plane
));
558 sprctl
&= ~SP_SOURCE_KEY
;
559 if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
560 sprctl
|= SP_SOURCE_KEY
;
561 I915_WRITE(SPCNTR(pipe
, plane
), sprctl
);
563 POSTING_READ(SPKEYMSK(pipe
, plane
));
569 vlv_get_colorkey(struct drm_plane
*dplane
,
570 struct drm_intel_sprite_colorkey
*key
)
572 struct drm_device
*dev
= dplane
->dev
;
573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
574 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
575 int pipe
= intel_plane
->pipe
;
576 int plane
= intel_plane
->plane
;
579 key
->min_value
= I915_READ(SPKEYMINVAL(pipe
, plane
));
580 key
->max_value
= I915_READ(SPKEYMAXVAL(pipe
, plane
));
581 key
->channel_mask
= I915_READ(SPKEYMSK(pipe
, plane
));
583 sprctl
= I915_READ(SPCNTR(pipe
, plane
));
584 if (sprctl
& SP_SOURCE_KEY
)
585 key
->flags
= I915_SET_COLORKEY_SOURCE
;
587 key
->flags
= I915_SET_COLORKEY_NONE
;
591 ivb_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
592 struct drm_framebuffer
*fb
,
593 struct drm_i915_gem_object
*obj
, int crtc_x
, int crtc_y
,
594 unsigned int crtc_w
, unsigned int crtc_h
,
595 uint32_t x
, uint32_t y
,
596 uint32_t src_w
, uint32_t src_h
)
598 struct drm_device
*dev
= plane
->dev
;
599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
600 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
601 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
602 int pipe
= intel_plane
->pipe
;
603 u32 sprctl
, sprscale
= 0;
604 unsigned long sprsurf_offset
, linear_offset
;
605 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
609 sprctl
= I915_READ(SPRCTL(pipe
));
611 /* Mask out pixel format bits in case we change it */
612 sprctl
&= ~SPRITE_PIXFORMAT_MASK
;
613 sprctl
&= ~SPRITE_RGB_ORDER_RGBX
;
614 sprctl
&= ~SPRITE_YUV_BYTE_ORDER_MASK
;
615 sprctl
&= ~SPRITE_TILED
;
616 sprctl
&= ~SPRITE_ROTATE_180
;
618 switch (fb
->pixel_format
) {
619 case DRM_FORMAT_XBGR8888
:
620 sprctl
|= SPRITE_FORMAT_RGBX888
| SPRITE_RGB_ORDER_RGBX
;
622 case DRM_FORMAT_XRGB8888
:
623 sprctl
|= SPRITE_FORMAT_RGBX888
;
625 case DRM_FORMAT_YUYV
:
626 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YUYV
;
628 case DRM_FORMAT_YVYU
:
629 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YVYU
;
631 case DRM_FORMAT_UYVY
:
632 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_UYVY
;
634 case DRM_FORMAT_VYUY
:
635 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_VYUY
;
642 * Enable gamma to match primary/cursor plane behaviour.
643 * FIXME should be user controllable via propertiesa.
645 sprctl
|= SPRITE_GAMMA_ENABLE
;
647 if (obj
->tiling_mode
!= I915_TILING_NONE
)
648 sprctl
|= SPRITE_TILED
;
650 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
651 sprctl
&= ~SPRITE_TRICKLE_FEED_DISABLE
;
653 sprctl
|= SPRITE_TRICKLE_FEED_DISABLE
;
655 sprctl
|= SPRITE_ENABLE
;
657 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
658 sprctl
|= SPRITE_PIPE_CSC_ENABLE
;
660 intel_update_sprite_watermarks(plane
, crtc
, src_w
, src_h
, pixel_size
,
662 src_w
!= crtc_w
|| src_h
!= crtc_h
);
664 /* Sizes are 0 based */
670 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
671 sprscale
= SPRITE_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
673 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
675 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
676 pixel_size
, fb
->pitches
[0]);
677 linear_offset
-= sprsurf_offset
;
679 if (intel_plane
->rotation
== BIT(DRM_ROTATE_180
)) {
680 sprctl
|= SPRITE_ROTATE_180
;
682 /* HSW and BDW does this automagically in hardware */
683 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
686 linear_offset
+= src_h
* fb
->pitches
[0] +
691 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
693 intel_update_primary_plane(intel_crtc
);
695 I915_WRITE(SPRSTRIDE(pipe
), fb
->pitches
[0]);
696 I915_WRITE(SPRPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
698 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
700 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
701 I915_WRITE(SPROFFSET(pipe
), (y
<< 16) | x
);
702 else if (obj
->tiling_mode
!= I915_TILING_NONE
)
703 I915_WRITE(SPRTILEOFF(pipe
), (y
<< 16) | x
);
705 I915_WRITE(SPRLINOFF(pipe
), linear_offset
);
707 I915_WRITE(SPRSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
708 if (intel_plane
->can_scale
)
709 I915_WRITE(SPRSCALE(pipe
), sprscale
);
710 I915_WRITE(SPRCTL(pipe
), sprctl
);
711 I915_WRITE(SPRSURF(pipe
),
712 i915_gem_obj_ggtt_offset(obj
) + sprsurf_offset
);
714 intel_flush_primary_plane(dev_priv
, intel_crtc
->plane
);
717 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
721 ivb_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
)
723 struct drm_device
*dev
= plane
->dev
;
724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
725 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
726 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
727 int pipe
= intel_plane
->pipe
;
731 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
733 intel_update_primary_plane(intel_crtc
);
735 I915_WRITE(SPRCTL(pipe
), I915_READ(SPRCTL(pipe
)) & ~SPRITE_ENABLE
);
736 /* Can't leave the scaler enabled... */
737 if (intel_plane
->can_scale
)
738 I915_WRITE(SPRSCALE(pipe
), 0);
739 /* Activate double buffered register update */
740 I915_WRITE(SPRSURF(pipe
), 0);
742 intel_flush_primary_plane(dev_priv
, intel_crtc
->plane
);
745 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
748 * Avoid underruns when disabling the sprite.
749 * FIXME remove once watermark updates are done properly.
751 intel_wait_for_vblank(dev
, pipe
);
753 intel_update_sprite_watermarks(plane
, crtc
, 0, 0, 0, false, false);
757 ivb_update_colorkey(struct drm_plane
*plane
,
758 struct drm_intel_sprite_colorkey
*key
)
760 struct drm_device
*dev
= plane
->dev
;
761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
762 struct intel_plane
*intel_plane
;
766 intel_plane
= to_intel_plane(plane
);
768 I915_WRITE(SPRKEYVAL(intel_plane
->pipe
), key
->min_value
);
769 I915_WRITE(SPRKEYMAX(intel_plane
->pipe
), key
->max_value
);
770 I915_WRITE(SPRKEYMSK(intel_plane
->pipe
), key
->channel_mask
);
772 sprctl
= I915_READ(SPRCTL(intel_plane
->pipe
));
773 sprctl
&= ~(SPRITE_SOURCE_KEY
| SPRITE_DEST_KEY
);
774 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
775 sprctl
|= SPRITE_DEST_KEY
;
776 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
777 sprctl
|= SPRITE_SOURCE_KEY
;
778 I915_WRITE(SPRCTL(intel_plane
->pipe
), sprctl
);
780 POSTING_READ(SPRKEYMSK(intel_plane
->pipe
));
786 ivb_get_colorkey(struct drm_plane
*plane
, struct drm_intel_sprite_colorkey
*key
)
788 struct drm_device
*dev
= plane
->dev
;
789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
790 struct intel_plane
*intel_plane
;
793 intel_plane
= to_intel_plane(plane
);
795 key
->min_value
= I915_READ(SPRKEYVAL(intel_plane
->pipe
));
796 key
->max_value
= I915_READ(SPRKEYMAX(intel_plane
->pipe
));
797 key
->channel_mask
= I915_READ(SPRKEYMSK(intel_plane
->pipe
));
800 sprctl
= I915_READ(SPRCTL(intel_plane
->pipe
));
802 if (sprctl
& SPRITE_DEST_KEY
)
803 key
->flags
= I915_SET_COLORKEY_DESTINATION
;
804 else if (sprctl
& SPRITE_SOURCE_KEY
)
805 key
->flags
= I915_SET_COLORKEY_SOURCE
;
807 key
->flags
= I915_SET_COLORKEY_NONE
;
811 ilk_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
812 struct drm_framebuffer
*fb
,
813 struct drm_i915_gem_object
*obj
, int crtc_x
, int crtc_y
,
814 unsigned int crtc_w
, unsigned int crtc_h
,
815 uint32_t x
, uint32_t y
,
816 uint32_t src_w
, uint32_t src_h
)
818 struct drm_device
*dev
= plane
->dev
;
819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
820 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
821 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
822 int pipe
= intel_plane
->pipe
;
823 unsigned long dvssurf_offset
, linear_offset
;
824 u32 dvscntr
, dvsscale
;
825 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
829 dvscntr
= I915_READ(DVSCNTR(pipe
));
831 /* Mask out pixel format bits in case we change it */
832 dvscntr
&= ~DVS_PIXFORMAT_MASK
;
833 dvscntr
&= ~DVS_RGB_ORDER_XBGR
;
834 dvscntr
&= ~DVS_YUV_BYTE_ORDER_MASK
;
835 dvscntr
&= ~DVS_TILED
;
836 dvscntr
&= ~DVS_ROTATE_180
;
838 switch (fb
->pixel_format
) {
839 case DRM_FORMAT_XBGR8888
:
840 dvscntr
|= DVS_FORMAT_RGBX888
| DVS_RGB_ORDER_XBGR
;
842 case DRM_FORMAT_XRGB8888
:
843 dvscntr
|= DVS_FORMAT_RGBX888
;
845 case DRM_FORMAT_YUYV
:
846 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YUYV
;
848 case DRM_FORMAT_YVYU
:
849 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YVYU
;
851 case DRM_FORMAT_UYVY
:
852 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_UYVY
;
854 case DRM_FORMAT_VYUY
:
855 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_VYUY
;
862 * Enable gamma to match primary/cursor plane behaviour.
863 * FIXME should be user controllable via propertiesa.
865 dvscntr
|= DVS_GAMMA_ENABLE
;
867 if (obj
->tiling_mode
!= I915_TILING_NONE
)
868 dvscntr
|= DVS_TILED
;
871 dvscntr
|= DVS_TRICKLE_FEED_DISABLE
; /* must disable */
872 dvscntr
|= DVS_ENABLE
;
874 intel_update_sprite_watermarks(plane
, crtc
, src_w
, src_h
,
876 src_w
!= crtc_w
|| src_h
!= crtc_h
);
878 /* Sizes are 0 based */
885 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
886 dvsscale
= DVS_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
888 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
890 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
891 pixel_size
, fb
->pitches
[0]);
892 linear_offset
-= dvssurf_offset
;
894 if (intel_plane
->rotation
== BIT(DRM_ROTATE_180
)) {
895 dvscntr
|= DVS_ROTATE_180
;
899 linear_offset
+= src_h
* fb
->pitches
[0] + src_w
* pixel_size
;
902 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
904 intel_update_primary_plane(intel_crtc
);
906 I915_WRITE(DVSSTRIDE(pipe
), fb
->pitches
[0]);
907 I915_WRITE(DVSPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
909 if (obj
->tiling_mode
!= I915_TILING_NONE
)
910 I915_WRITE(DVSTILEOFF(pipe
), (y
<< 16) | x
);
912 I915_WRITE(DVSLINOFF(pipe
), linear_offset
);
914 I915_WRITE(DVSSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
915 I915_WRITE(DVSSCALE(pipe
), dvsscale
);
916 I915_WRITE(DVSCNTR(pipe
), dvscntr
);
917 I915_WRITE(DVSSURF(pipe
),
918 i915_gem_obj_ggtt_offset(obj
) + dvssurf_offset
);
920 intel_flush_primary_plane(dev_priv
, intel_crtc
->plane
);
923 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
927 ilk_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
)
929 struct drm_device
*dev
= plane
->dev
;
930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
931 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
932 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
933 int pipe
= intel_plane
->pipe
;
937 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
939 intel_update_primary_plane(intel_crtc
);
941 I915_WRITE(DVSCNTR(pipe
), I915_READ(DVSCNTR(pipe
)) & ~DVS_ENABLE
);
942 /* Disable the scaler */
943 I915_WRITE(DVSSCALE(pipe
), 0);
944 /* Flush double buffered register updates */
945 I915_WRITE(DVSSURF(pipe
), 0);
947 intel_flush_primary_plane(dev_priv
, intel_crtc
->plane
);
950 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
953 * Avoid underruns when disabling the sprite.
954 * FIXME remove once watermark updates are done properly.
956 intel_wait_for_vblank(dev
, pipe
);
958 intel_update_sprite_watermarks(plane
, crtc
, 0, 0, 0, false, false);
962 intel_post_enable_primary(struct drm_crtc
*crtc
)
964 struct drm_device
*dev
= crtc
->dev
;
965 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
968 * BDW signals flip done immediately if the plane
969 * is disabled, even if the plane enable is already
970 * armed to occur at the next vblank :(
972 if (IS_BROADWELL(dev
))
973 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
976 * FIXME IPS should be fine as long as one plane is
977 * enabled, but in practice it seems to have problems
978 * when going from primary only to sprite only and vice
981 hsw_enable_ips(intel_crtc
);
983 mutex_lock(&dev
->struct_mutex
);
984 intel_update_fbc(dev
);
985 mutex_unlock(&dev
->struct_mutex
);
989 intel_pre_disable_primary(struct drm_crtc
*crtc
)
991 struct drm_device
*dev
= crtc
->dev
;
992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
993 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
995 mutex_lock(&dev
->struct_mutex
);
996 if (dev_priv
->fbc
.plane
== intel_crtc
->plane
)
997 intel_disable_fbc(dev
);
998 mutex_unlock(&dev
->struct_mutex
);
1001 * FIXME IPS should be fine as long as one plane is
1002 * enabled, but in practice it seems to have problems
1003 * when going from primary only to sprite only and vice
1006 hsw_disable_ips(intel_crtc
);
1010 ilk_update_colorkey(struct drm_plane
*plane
,
1011 struct drm_intel_sprite_colorkey
*key
)
1013 struct drm_device
*dev
= plane
->dev
;
1014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1015 struct intel_plane
*intel_plane
;
1019 intel_plane
= to_intel_plane(plane
);
1021 I915_WRITE(DVSKEYVAL(intel_plane
->pipe
), key
->min_value
);
1022 I915_WRITE(DVSKEYMAX(intel_plane
->pipe
), key
->max_value
);
1023 I915_WRITE(DVSKEYMSK(intel_plane
->pipe
), key
->channel_mask
);
1025 dvscntr
= I915_READ(DVSCNTR(intel_plane
->pipe
));
1026 dvscntr
&= ~(DVS_SOURCE_KEY
| DVS_DEST_KEY
);
1027 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
1028 dvscntr
|= DVS_DEST_KEY
;
1029 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
1030 dvscntr
|= DVS_SOURCE_KEY
;
1031 I915_WRITE(DVSCNTR(intel_plane
->pipe
), dvscntr
);
1033 POSTING_READ(DVSKEYMSK(intel_plane
->pipe
));
1039 ilk_get_colorkey(struct drm_plane
*plane
, struct drm_intel_sprite_colorkey
*key
)
1041 struct drm_device
*dev
= plane
->dev
;
1042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1043 struct intel_plane
*intel_plane
;
1046 intel_plane
= to_intel_plane(plane
);
1048 key
->min_value
= I915_READ(DVSKEYVAL(intel_plane
->pipe
));
1049 key
->max_value
= I915_READ(DVSKEYMAX(intel_plane
->pipe
));
1050 key
->channel_mask
= I915_READ(DVSKEYMSK(intel_plane
->pipe
));
1053 dvscntr
= I915_READ(DVSCNTR(intel_plane
->pipe
));
1055 if (dvscntr
& DVS_DEST_KEY
)
1056 key
->flags
= I915_SET_COLORKEY_DESTINATION
;
1057 else if (dvscntr
& DVS_SOURCE_KEY
)
1058 key
->flags
= I915_SET_COLORKEY_SOURCE
;
1060 key
->flags
= I915_SET_COLORKEY_NONE
;
1063 static bool colorkey_enabled(struct intel_plane
*intel_plane
)
1065 struct drm_intel_sprite_colorkey key
;
1067 intel_plane
->get_colorkey(&intel_plane
->base
, &key
);
1069 return key
.flags
!= I915_SET_COLORKEY_NONE
;
1073 intel_check_sprite_plane(struct drm_plane
*plane
,
1074 struct intel_plane_state
*state
)
1076 struct intel_crtc
*intel_crtc
= to_intel_crtc(state
->crtc
);
1077 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
1078 struct drm_framebuffer
*fb
= state
->fb
;
1079 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
1081 unsigned int crtc_w
, crtc_h
;
1082 uint32_t src_x
, src_y
, src_w
, src_h
;
1083 struct drm_rect
*src
= &state
->src
;
1084 struct drm_rect
*dst
= &state
->dst
;
1085 struct drm_rect
*orig_src
= &state
->orig_src
;
1086 const struct drm_rect
*clip
= &state
->clip
;
1088 int max_scale
, min_scale
;
1089 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
1091 /* Don't modify another pipe's plane */
1092 if (intel_plane
->pipe
!= intel_crtc
->pipe
) {
1093 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
1097 /* FIXME check all gen limits */
1098 if (fb
->width
< 3 || fb
->height
< 3 || fb
->pitches
[0] > 16384) {
1099 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
1103 /* Sprite planes can be linear or x-tiled surfaces */
1104 switch (obj
->tiling_mode
) {
1105 case I915_TILING_NONE
:
1109 DRM_DEBUG_KMS("Unsupported tiling mode\n");
1114 * FIXME the following code does a bunch of fuzzy adjustments to the
1115 * coordinates and sizes. We probably need some way to decide whether
1116 * more strict checking should be done instead.
1118 max_scale
= intel_plane
->max_downscale
<< 16;
1119 min_scale
= intel_plane
->can_scale
? 1 : (1 << 16);
1121 drm_rect_rotate(src
, fb
->width
<< 16, fb
->height
<< 16,
1122 intel_plane
->rotation
);
1124 hscale
= drm_rect_calc_hscale_relaxed(src
, dst
, min_scale
, max_scale
);
1127 vscale
= drm_rect_calc_vscale_relaxed(src
, dst
, min_scale
, max_scale
);
1130 state
->visible
= drm_rect_clip_scaled(src
, dst
, clip
, hscale
, vscale
);
1134 crtc_w
= drm_rect_width(dst
);
1135 crtc_h
= drm_rect_height(dst
);
1137 if (state
->visible
) {
1138 /* check again in case clipping clamped the results */
1139 hscale
= drm_rect_calc_hscale(src
, dst
, min_scale
, max_scale
);
1141 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
1142 drm_rect_debug_print(src
, true);
1143 drm_rect_debug_print(dst
, false);
1148 vscale
= drm_rect_calc_vscale(src
, dst
, min_scale
, max_scale
);
1150 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
1151 drm_rect_debug_print(src
, true);
1152 drm_rect_debug_print(dst
, false);
1157 /* Make the source viewport size an exact multiple of the scaling factors. */
1158 drm_rect_adjust_size(src
,
1159 drm_rect_width(dst
) * hscale
- drm_rect_width(src
),
1160 drm_rect_height(dst
) * vscale
- drm_rect_height(src
));
1162 drm_rect_rotate_inv(src
, fb
->width
<< 16, fb
->height
<< 16,
1163 intel_plane
->rotation
);
1165 /* sanity check to make sure the src viewport wasn't enlarged */
1166 WARN_ON(src
->x1
< (int) orig_src
->x1
||
1167 src
->y1
< (int) orig_src
->y1
||
1168 src
->x2
> (int) orig_src
->x2
||
1169 src
->y2
> (int) orig_src
->y2
);
1172 * Hardware doesn't handle subpixel coordinates.
1173 * Adjust to (macro)pixel boundary, but be careful not to
1174 * increase the source viewport size, because that could
1175 * push the downscaling factor out of bounds.
1177 src_x
= src
->x1
>> 16;
1178 src_w
= drm_rect_width(src
) >> 16;
1179 src_y
= src
->y1
>> 16;
1180 src_h
= drm_rect_height(src
) >> 16;
1182 if (format_is_yuv(fb
->pixel_format
)) {
1187 * Must keep src and dst the
1188 * same if we can't scale.
1190 if (!intel_plane
->can_scale
)
1194 state
->visible
= false;
1198 /* Check size restrictions when scaling */
1199 if (state
->visible
&& (src_w
!= crtc_w
|| src_h
!= crtc_h
)) {
1200 unsigned int width_bytes
;
1202 WARN_ON(!intel_plane
->can_scale
);
1204 /* FIXME interlacing min height is 6 */
1206 if (crtc_w
< 3 || crtc_h
< 3)
1207 state
->visible
= false;
1209 if (src_w
< 3 || src_h
< 3)
1210 state
->visible
= false;
1212 width_bytes
= ((src_x
* pixel_size
) & 63) +
1215 if (src_w
> 2048 || src_h
> 2048 ||
1216 width_bytes
> 4096 || fb
->pitches
[0] > 4096) {
1217 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1222 if (state
->visible
) {
1224 src
->x2
= src_x
+ src_w
;
1226 src
->y2
= src_y
+ src_h
;
1230 dst
->x2
= crtc_x
+ crtc_w
;
1232 dst
->y2
= crtc_y
+ crtc_h
;
1238 intel_prepare_sprite_plane(struct drm_plane
*plane
,
1239 struct intel_plane_state
*state
)
1241 struct drm_device
*dev
= plane
->dev
;
1242 struct drm_crtc
*crtc
= state
->crtc
;
1243 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1244 enum pipe pipe
= intel_crtc
->pipe
;
1245 struct drm_framebuffer
*fb
= state
->fb
;
1246 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
1247 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
1250 if (old_obj
!= obj
) {
1251 mutex_lock(&dev
->struct_mutex
);
1253 /* Note that this will apply the VT-d workaround for scanouts,
1254 * which is more restrictive than required for sprites. (The
1255 * primary plane requires 256KiB alignment with 64 PTE padding,
1256 * the sprite planes only require 128KiB alignment and 32 PTE
1259 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
1261 i915_gem_track_fb(old_obj
, obj
,
1262 INTEL_FRONTBUFFER_SPRITE(pipe
));
1263 mutex_unlock(&dev
->struct_mutex
);
1272 intel_commit_sprite_plane(struct drm_plane
*plane
,
1273 struct intel_plane_state
*state
)
1275 struct drm_device
*dev
= plane
->dev
;
1276 struct drm_crtc
*crtc
= state
->crtc
;
1277 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1278 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
1279 enum pipe pipe
= intel_crtc
->pipe
;
1280 struct drm_framebuffer
*fb
= state
->fb
;
1281 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
1282 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
1284 unsigned int crtc_w
, crtc_h
;
1285 uint32_t src_x
, src_y
, src_w
, src_h
;
1286 struct drm_rect
*dst
= &state
->dst
;
1287 const struct drm_rect
*clip
= &state
->clip
;
1288 bool primary_enabled
;
1291 * If the sprite is completely covering the primary plane,
1292 * we can disable the primary and save power.
1294 primary_enabled
= !drm_rect_equals(dst
, clip
) || colorkey_enabled(intel_plane
);
1295 WARN_ON(!primary_enabled
&& !state
->visible
&& intel_crtc
->active
);
1297 intel_plane
->crtc_x
= state
->orig_dst
.x1
;
1298 intel_plane
->crtc_y
= state
->orig_dst
.y1
;
1299 intel_plane
->crtc_w
= drm_rect_width(&state
->orig_dst
);
1300 intel_plane
->crtc_h
= drm_rect_height(&state
->orig_dst
);
1301 intel_plane
->src_x
= state
->orig_src
.x1
;
1302 intel_plane
->src_y
= state
->orig_src
.y1
;
1303 intel_plane
->src_w
= drm_rect_width(&state
->orig_src
);
1304 intel_plane
->src_h
= drm_rect_height(&state
->orig_src
);
1305 intel_plane
->obj
= obj
;
1307 if (intel_crtc
->active
) {
1308 bool primary_was_enabled
= intel_crtc
->primary_enabled
;
1310 intel_crtc
->primary_enabled
= primary_enabled
;
1312 if (primary_was_enabled
!= primary_enabled
)
1313 intel_crtc_wait_for_pending_flips(crtc
);
1315 if (primary_was_enabled
&& !primary_enabled
)
1316 intel_pre_disable_primary(crtc
);
1318 if (state
->visible
) {
1319 crtc_x
= state
->dst
.x1
;
1320 crtc_y
= state
->dst
.y1
;
1321 crtc_w
= drm_rect_width(&state
->dst
);
1322 crtc_h
= drm_rect_height(&state
->dst
);
1323 src_x
= state
->src
.x1
;
1324 src_y
= state
->src
.y1
;
1325 src_w
= drm_rect_width(&state
->src
);
1326 src_h
= drm_rect_height(&state
->src
);
1327 intel_plane
->update_plane(plane
, crtc
, fb
, obj
,
1328 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
1329 src_x
, src_y
, src_w
, src_h
);
1331 intel_plane
->disable_plane(plane
, crtc
);
1335 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_SPRITE(pipe
));
1337 if (!primary_was_enabled
&& primary_enabled
)
1338 intel_post_enable_primary(crtc
);
1341 /* Unpin old obj after new one is active to avoid ugliness */
1342 if (old_obj
&& old_obj
!= obj
) {
1345 * It's fairly common to simply update the position of
1346 * an existing object. In that case, we don't need to
1347 * wait for vblank to avoid ugliness, we only need to
1348 * do the pin & ref bookkeeping.
1350 if (intel_crtc
->active
)
1351 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1353 mutex_lock(&dev
->struct_mutex
);
1354 intel_unpin_fb_obj(old_obj
);
1355 mutex_unlock(&dev
->struct_mutex
);
1360 intel_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
1361 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
1362 unsigned int crtc_w
, unsigned int crtc_h
,
1363 uint32_t src_x
, uint32_t src_y
,
1364 uint32_t src_w
, uint32_t src_h
)
1366 struct intel_plane_state state
;
1367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1373 /* sample coordinates in 16.16 fixed point */
1374 state
.src
.x1
= src_x
;
1375 state
.src
.x2
= src_x
+ src_w
;
1376 state
.src
.y1
= src_y
;
1377 state
.src
.y2
= src_y
+ src_h
;
1379 /* integer pixels */
1380 state
.dst
.x1
= crtc_x
;
1381 state
.dst
.x2
= crtc_x
+ crtc_w
;
1382 state
.dst
.y1
= crtc_y
;
1383 state
.dst
.y2
= crtc_y
+ crtc_h
;
1387 state
.clip
.x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0;
1388 state
.clip
.y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0;
1389 state
.orig_src
= state
.src
;
1390 state
.orig_dst
= state
.dst
;
1392 ret
= intel_check_sprite_plane(plane
, &state
);
1396 ret
= intel_prepare_sprite_plane(plane
, &state
);
1400 intel_commit_sprite_plane(plane
, &state
);
1405 intel_disable_plane(struct drm_plane
*plane
)
1407 struct drm_device
*dev
= plane
->dev
;
1408 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
1409 struct intel_crtc
*intel_crtc
;
1415 if (WARN_ON(!plane
->crtc
))
1418 intel_crtc
= to_intel_crtc(plane
->crtc
);
1419 pipe
= intel_crtc
->pipe
;
1421 if (intel_crtc
->active
) {
1422 bool primary_was_enabled
= intel_crtc
->primary_enabled
;
1424 intel_crtc
->primary_enabled
= true;
1426 intel_plane
->disable_plane(plane
, plane
->crtc
);
1428 if (!primary_was_enabled
&& intel_crtc
->primary_enabled
)
1429 intel_post_enable_primary(plane
->crtc
);
1432 if (intel_plane
->obj
) {
1433 if (intel_crtc
->active
)
1434 intel_wait_for_vblank(dev
, intel_plane
->pipe
);
1436 mutex_lock(&dev
->struct_mutex
);
1437 intel_unpin_fb_obj(intel_plane
->obj
);
1438 i915_gem_track_fb(intel_plane
->obj
, NULL
,
1439 INTEL_FRONTBUFFER_SPRITE(pipe
));
1440 mutex_unlock(&dev
->struct_mutex
);
1442 intel_plane
->obj
= NULL
;
1448 static void intel_destroy_plane(struct drm_plane
*plane
)
1450 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
1451 intel_disable_plane(plane
);
1452 drm_plane_cleanup(plane
);
1456 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1457 struct drm_file
*file_priv
)
1459 struct drm_intel_sprite_colorkey
*set
= data
;
1460 struct drm_plane
*plane
;
1461 struct intel_plane
*intel_plane
;
1464 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
1467 /* Make sure we don't try to enable both src & dest simultaneously */
1468 if ((set
->flags
& (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
)) == (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
))
1471 drm_modeset_lock_all(dev
);
1473 plane
= drm_plane_find(dev
, set
->plane_id
);
1479 intel_plane
= to_intel_plane(plane
);
1480 ret
= intel_plane
->update_colorkey(plane
, set
);
1483 drm_modeset_unlock_all(dev
);
1487 int intel_sprite_get_colorkey(struct drm_device
*dev
, void *data
,
1488 struct drm_file
*file_priv
)
1490 struct drm_intel_sprite_colorkey
*get
= data
;
1491 struct drm_plane
*plane
;
1492 struct intel_plane
*intel_plane
;
1495 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
1498 drm_modeset_lock_all(dev
);
1500 plane
= drm_plane_find(dev
, get
->plane_id
);
1506 intel_plane
= to_intel_plane(plane
);
1507 intel_plane
->get_colorkey(plane
, get
);
1510 drm_modeset_unlock_all(dev
);
1514 int intel_plane_set_property(struct drm_plane
*plane
,
1515 struct drm_property
*prop
,
1518 struct drm_device
*dev
= plane
->dev
;
1519 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
1523 if (prop
== dev
->mode_config
.rotation_property
) {
1524 /* exactly one rotation angle please */
1525 if (hweight32(val
& 0xf) != 1)
1528 if (intel_plane
->rotation
== val
)
1531 old_val
= intel_plane
->rotation
;
1532 intel_plane
->rotation
= val
;
1533 ret
= intel_plane_restore(plane
);
1535 intel_plane
->rotation
= old_val
;
1541 int intel_plane_restore(struct drm_plane
*plane
)
1543 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
1545 if (!plane
->crtc
|| !plane
->fb
)
1548 return plane
->funcs
->update_plane(plane
, plane
->crtc
, plane
->fb
,
1549 intel_plane
->crtc_x
, intel_plane
->crtc_y
,
1550 intel_plane
->crtc_w
, intel_plane
->crtc_h
,
1551 intel_plane
->src_x
, intel_plane
->src_y
,
1552 intel_plane
->src_w
, intel_plane
->src_h
);
1555 void intel_plane_disable(struct drm_plane
*plane
)
1557 if (!plane
->crtc
|| !plane
->fb
)
1560 intel_disable_plane(plane
);
1563 static const struct drm_plane_funcs intel_plane_funcs
= {
1564 .update_plane
= intel_update_plane
,
1565 .disable_plane
= intel_disable_plane
,
1566 .destroy
= intel_destroy_plane
,
1567 .set_property
= intel_plane_set_property
,
1570 static uint32_t ilk_plane_formats
[] = {
1571 DRM_FORMAT_XRGB8888
,
1578 static uint32_t snb_plane_formats
[] = {
1579 DRM_FORMAT_XBGR8888
,
1580 DRM_FORMAT_XRGB8888
,
1587 static uint32_t vlv_plane_formats
[] = {
1589 DRM_FORMAT_ABGR8888
,
1590 DRM_FORMAT_ARGB8888
,
1591 DRM_FORMAT_XBGR8888
,
1592 DRM_FORMAT_XRGB8888
,
1593 DRM_FORMAT_XBGR2101010
,
1594 DRM_FORMAT_ABGR2101010
,
1601 static uint32_t skl_plane_formats
[] = {
1603 DRM_FORMAT_ABGR8888
,
1604 DRM_FORMAT_ARGB8888
,
1605 DRM_FORMAT_XBGR8888
,
1606 DRM_FORMAT_XRGB8888
,
1614 intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
)
1616 struct intel_plane
*intel_plane
;
1617 unsigned long possible_crtcs
;
1618 const uint32_t *plane_formats
;
1619 int num_plane_formats
;
1622 if (INTEL_INFO(dev
)->gen
< 5)
1625 intel_plane
= kzalloc(sizeof(*intel_plane
), GFP_KERNEL
);
1629 switch (INTEL_INFO(dev
)->gen
) {
1632 intel_plane
->can_scale
= true;
1633 intel_plane
->max_downscale
= 16;
1634 intel_plane
->update_plane
= ilk_update_plane
;
1635 intel_plane
->disable_plane
= ilk_disable_plane
;
1636 intel_plane
->update_colorkey
= ilk_update_colorkey
;
1637 intel_plane
->get_colorkey
= ilk_get_colorkey
;
1640 plane_formats
= snb_plane_formats
;
1641 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1643 plane_formats
= ilk_plane_formats
;
1644 num_plane_formats
= ARRAY_SIZE(ilk_plane_formats
);
1650 if (IS_IVYBRIDGE(dev
)) {
1651 intel_plane
->can_scale
= true;
1652 intel_plane
->max_downscale
= 2;
1654 intel_plane
->can_scale
= false;
1655 intel_plane
->max_downscale
= 1;
1658 if (IS_VALLEYVIEW(dev
)) {
1659 intel_plane
->update_plane
= vlv_update_plane
;
1660 intel_plane
->disable_plane
= vlv_disable_plane
;
1661 intel_plane
->update_colorkey
= vlv_update_colorkey
;
1662 intel_plane
->get_colorkey
= vlv_get_colorkey
;
1664 plane_formats
= vlv_plane_formats
;
1665 num_plane_formats
= ARRAY_SIZE(vlv_plane_formats
);
1667 intel_plane
->update_plane
= ivb_update_plane
;
1668 intel_plane
->disable_plane
= ivb_disable_plane
;
1669 intel_plane
->update_colorkey
= ivb_update_colorkey
;
1670 intel_plane
->get_colorkey
= ivb_get_colorkey
;
1672 plane_formats
= snb_plane_formats
;
1673 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1678 * FIXME: Skylake planes can be scaled (with some restrictions),
1679 * but this is for another time.
1681 intel_plane
->can_scale
= false;
1682 intel_plane
->max_downscale
= 1;
1683 intel_plane
->update_plane
= skl_update_plane
;
1684 intel_plane
->disable_plane
= skl_disable_plane
;
1685 intel_plane
->update_colorkey
= skl_update_colorkey
;
1686 intel_plane
->get_colorkey
= skl_get_colorkey
;
1688 plane_formats
= skl_plane_formats
;
1689 num_plane_formats
= ARRAY_SIZE(skl_plane_formats
);
1696 intel_plane
->pipe
= pipe
;
1697 intel_plane
->plane
= plane
;
1698 intel_plane
->rotation
= BIT(DRM_ROTATE_0
);
1699 possible_crtcs
= (1 << pipe
);
1700 ret
= drm_universal_plane_init(dev
, &intel_plane
->base
, possible_crtcs
,
1702 plane_formats
, num_plane_formats
,
1703 DRM_PLANE_TYPE_OVERLAY
);
1709 if (!dev
->mode_config
.rotation_property
)
1710 dev
->mode_config
.rotation_property
=
1711 drm_mode_create_rotation_property(dev
,
1713 BIT(DRM_ROTATE_180
));
1715 if (dev
->mode_config
.rotation_property
)
1716 drm_object_attach_property(&intel_plane
->base
.base
,
1717 dev
->mode_config
.rotation_property
,
1718 intel_plane
->rotation
);