2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
41 vlv_update_plane(struct drm_plane
*dplane
, struct drm_framebuffer
*fb
,
42 struct drm_i915_gem_object
*obj
, int crtc_x
, int crtc_y
,
43 unsigned int crtc_w
, unsigned int crtc_h
,
44 uint32_t x
, uint32_t y
,
45 uint32_t src_w
, uint32_t src_h
)
47 struct drm_device
*dev
= dplane
->dev
;
48 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
49 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
50 int pipe
= intel_plane
->pipe
;
51 int plane
= intel_plane
->plane
;
53 unsigned long sprsurf_offset
, linear_offset
;
54 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
56 sprctl
= I915_READ(SPCNTR(pipe
, plane
));
58 /* Mask out pixel format bits in case we change it */
59 sprctl
&= ~SP_PIXFORMAT_MASK
;
60 sprctl
&= ~SP_YUV_BYTE_ORDER_MASK
;
63 switch (fb
->pixel_format
) {
65 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YUYV
;
68 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YVYU
;
71 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_UYVY
;
74 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_VYUY
;
76 case DRM_FORMAT_RGB565
:
77 sprctl
|= SP_FORMAT_BGR565
;
79 case DRM_FORMAT_XRGB8888
:
80 sprctl
|= SP_FORMAT_BGRX8888
;
82 case DRM_FORMAT_ARGB8888
:
83 sprctl
|= SP_FORMAT_BGRA8888
;
85 case DRM_FORMAT_XBGR2101010
:
86 sprctl
|= SP_FORMAT_RGBX1010102
;
88 case DRM_FORMAT_ABGR2101010
:
89 sprctl
|= SP_FORMAT_RGBA1010102
;
91 case DRM_FORMAT_XBGR8888
:
92 sprctl
|= SP_FORMAT_RGBX8888
;
94 case DRM_FORMAT_ABGR8888
:
95 sprctl
|= SP_FORMAT_RGBA8888
;
99 * If we get here one of the upper layers failed to filter
100 * out the unsupported plane formats
106 if (obj
->tiling_mode
!= I915_TILING_NONE
)
111 /* Sizes are 0 based */
117 intel_update_sprite_watermarks(dev
, pipe
, crtc_w
, pixel_size
, true);
119 I915_WRITE(SPSTRIDE(pipe
, plane
), fb
->pitches
[0]);
120 I915_WRITE(SPPOS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
122 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
123 sprsurf_offset
= intel_gen4_compute_page_offset(&x
, &y
,
127 linear_offset
-= sprsurf_offset
;
129 if (obj
->tiling_mode
!= I915_TILING_NONE
)
130 I915_WRITE(SPTILEOFF(pipe
, plane
), (y
<< 16) | x
);
132 I915_WRITE(SPLINOFF(pipe
, plane
), linear_offset
);
134 I915_WRITE(SPSIZE(pipe
, plane
), (crtc_h
<< 16) | crtc_w
);
135 I915_WRITE(SPCNTR(pipe
, plane
), sprctl
);
136 I915_MODIFY_DISPBASE(SPSURF(pipe
, plane
), i915_gem_obj_ggtt_offset(obj
) +
138 POSTING_READ(SPSURF(pipe
, plane
));
142 vlv_disable_plane(struct drm_plane
*dplane
)
144 struct drm_device
*dev
= dplane
->dev
;
145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
146 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
147 int pipe
= intel_plane
->pipe
;
148 int plane
= intel_plane
->plane
;
150 I915_WRITE(SPCNTR(pipe
, plane
), I915_READ(SPCNTR(pipe
, plane
)) &
152 /* Activate double buffered register update */
153 I915_MODIFY_DISPBASE(SPSURF(pipe
, plane
), 0);
154 POSTING_READ(SPSURF(pipe
, plane
));
158 vlv_update_colorkey(struct drm_plane
*dplane
,
159 struct drm_intel_sprite_colorkey
*key
)
161 struct drm_device
*dev
= dplane
->dev
;
162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
163 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
164 int pipe
= intel_plane
->pipe
;
165 int plane
= intel_plane
->plane
;
168 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
171 I915_WRITE(SPKEYMINVAL(pipe
, plane
), key
->min_value
);
172 I915_WRITE(SPKEYMAXVAL(pipe
, plane
), key
->max_value
);
173 I915_WRITE(SPKEYMSK(pipe
, plane
), key
->channel_mask
);
175 sprctl
= I915_READ(SPCNTR(pipe
, plane
));
176 sprctl
&= ~SP_SOURCE_KEY
;
177 if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
178 sprctl
|= SP_SOURCE_KEY
;
179 I915_WRITE(SPCNTR(pipe
, plane
), sprctl
);
181 POSTING_READ(SPKEYMSK(pipe
, plane
));
187 vlv_get_colorkey(struct drm_plane
*dplane
,
188 struct drm_intel_sprite_colorkey
*key
)
190 struct drm_device
*dev
= dplane
->dev
;
191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
192 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
193 int pipe
= intel_plane
->pipe
;
194 int plane
= intel_plane
->plane
;
197 key
->min_value
= I915_READ(SPKEYMINVAL(pipe
, plane
));
198 key
->max_value
= I915_READ(SPKEYMAXVAL(pipe
, plane
));
199 key
->channel_mask
= I915_READ(SPKEYMSK(pipe
, plane
));
201 sprctl
= I915_READ(SPCNTR(pipe
, plane
));
202 if (sprctl
& SP_SOURCE_KEY
)
203 key
->flags
= I915_SET_COLORKEY_SOURCE
;
205 key
->flags
= I915_SET_COLORKEY_NONE
;
209 ivb_update_plane(struct drm_plane
*plane
, struct drm_framebuffer
*fb
,
210 struct drm_i915_gem_object
*obj
, int crtc_x
, int crtc_y
,
211 unsigned int crtc_w
, unsigned int crtc_h
,
212 uint32_t x
, uint32_t y
,
213 uint32_t src_w
, uint32_t src_h
)
215 struct drm_device
*dev
= plane
->dev
;
216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
217 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
218 int pipe
= intel_plane
->pipe
;
219 u32 sprctl
, sprscale
= 0;
220 unsigned long sprsurf_offset
, linear_offset
;
221 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
222 bool scaling_was_enabled
= dev_priv
->sprite_scaling_enabled
;
224 sprctl
= I915_READ(SPRCTL(pipe
));
226 /* Mask out pixel format bits in case we change it */
227 sprctl
&= ~SPRITE_PIXFORMAT_MASK
;
228 sprctl
&= ~SPRITE_RGB_ORDER_RGBX
;
229 sprctl
&= ~SPRITE_YUV_BYTE_ORDER_MASK
;
230 sprctl
&= ~SPRITE_TILED
;
232 switch (fb
->pixel_format
) {
233 case DRM_FORMAT_XBGR8888
:
234 sprctl
|= SPRITE_FORMAT_RGBX888
| SPRITE_RGB_ORDER_RGBX
;
236 case DRM_FORMAT_XRGB8888
:
237 sprctl
|= SPRITE_FORMAT_RGBX888
;
239 case DRM_FORMAT_YUYV
:
240 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YUYV
;
242 case DRM_FORMAT_YVYU
:
243 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YVYU
;
245 case DRM_FORMAT_UYVY
:
246 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_UYVY
;
248 case DRM_FORMAT_VYUY
:
249 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_VYUY
;
255 if (obj
->tiling_mode
!= I915_TILING_NONE
)
256 sprctl
|= SPRITE_TILED
;
259 sprctl
|= SPRITE_TRICKLE_FEED_DISABLE
;
260 sprctl
|= SPRITE_ENABLE
;
263 sprctl
|= SPRITE_PIPE_CSC_ENABLE
;
265 /* Sizes are 0 based */
271 intel_update_sprite_watermarks(dev
, pipe
, crtc_w
, pixel_size
, true);
274 * IVB workaround: must disable low power watermarks for at least
275 * one frame before enabling scaling. LP watermarks can be re-enabled
276 * when scaling is disabled.
278 if (crtc_w
!= src_w
|| crtc_h
!= src_h
) {
279 dev_priv
->sprite_scaling_enabled
|= 1 << pipe
;
281 if (!scaling_was_enabled
) {
282 intel_update_watermarks(dev
);
283 intel_wait_for_vblank(dev
, pipe
);
285 sprscale
= SPRITE_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
287 dev_priv
->sprite_scaling_enabled
&= ~(1 << pipe
);
289 I915_WRITE(SPRSTRIDE(pipe
), fb
->pitches
[0]);
290 I915_WRITE(SPRPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
292 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
294 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
295 pixel_size
, fb
->pitches
[0]);
296 linear_offset
-= sprsurf_offset
;
298 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
301 I915_WRITE(SPROFFSET(pipe
), (y
<< 16) | x
);
302 else if (obj
->tiling_mode
!= I915_TILING_NONE
)
303 I915_WRITE(SPRTILEOFF(pipe
), (y
<< 16) | x
);
305 I915_WRITE(SPRLINOFF(pipe
), linear_offset
);
307 I915_WRITE(SPRSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
308 if (intel_plane
->can_scale
)
309 I915_WRITE(SPRSCALE(pipe
), sprscale
);
310 I915_WRITE(SPRCTL(pipe
), sprctl
);
311 I915_MODIFY_DISPBASE(SPRSURF(pipe
),
312 i915_gem_obj_ggtt_offset(obj
) + sprsurf_offset
);
313 POSTING_READ(SPRSURF(pipe
));
315 /* potentially re-enable LP watermarks */
316 if (scaling_was_enabled
&& !dev_priv
->sprite_scaling_enabled
)
317 intel_update_watermarks(dev
);
321 ivb_disable_plane(struct drm_plane
*plane
)
323 struct drm_device
*dev
= plane
->dev
;
324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
325 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
326 int pipe
= intel_plane
->pipe
;
327 bool scaling_was_enabled
= dev_priv
->sprite_scaling_enabled
;
329 I915_WRITE(SPRCTL(pipe
), I915_READ(SPRCTL(pipe
)) & ~SPRITE_ENABLE
);
330 /* Can't leave the scaler enabled... */
331 if (intel_plane
->can_scale
)
332 I915_WRITE(SPRSCALE(pipe
), 0);
333 /* Activate double buffered register update */
334 I915_MODIFY_DISPBASE(SPRSURF(pipe
), 0);
335 POSTING_READ(SPRSURF(pipe
));
337 dev_priv
->sprite_scaling_enabled
&= ~(1 << pipe
);
339 intel_update_sprite_watermarks(dev
, pipe
, 0, 0, false);
341 /* potentially re-enable LP watermarks */
342 if (scaling_was_enabled
&& !dev_priv
->sprite_scaling_enabled
)
343 intel_update_watermarks(dev
);
347 ivb_update_colorkey(struct drm_plane
*plane
,
348 struct drm_intel_sprite_colorkey
*key
)
350 struct drm_device
*dev
= plane
->dev
;
351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
352 struct intel_plane
*intel_plane
;
356 intel_plane
= to_intel_plane(plane
);
358 I915_WRITE(SPRKEYVAL(intel_plane
->pipe
), key
->min_value
);
359 I915_WRITE(SPRKEYMAX(intel_plane
->pipe
), key
->max_value
);
360 I915_WRITE(SPRKEYMSK(intel_plane
->pipe
), key
->channel_mask
);
362 sprctl
= I915_READ(SPRCTL(intel_plane
->pipe
));
363 sprctl
&= ~(SPRITE_SOURCE_KEY
| SPRITE_DEST_KEY
);
364 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
365 sprctl
|= SPRITE_DEST_KEY
;
366 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
367 sprctl
|= SPRITE_SOURCE_KEY
;
368 I915_WRITE(SPRCTL(intel_plane
->pipe
), sprctl
);
370 POSTING_READ(SPRKEYMSK(intel_plane
->pipe
));
376 ivb_get_colorkey(struct drm_plane
*plane
, struct drm_intel_sprite_colorkey
*key
)
378 struct drm_device
*dev
= plane
->dev
;
379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
380 struct intel_plane
*intel_plane
;
383 intel_plane
= to_intel_plane(plane
);
385 key
->min_value
= I915_READ(SPRKEYVAL(intel_plane
->pipe
));
386 key
->max_value
= I915_READ(SPRKEYMAX(intel_plane
->pipe
));
387 key
->channel_mask
= I915_READ(SPRKEYMSK(intel_plane
->pipe
));
390 sprctl
= I915_READ(SPRCTL(intel_plane
->pipe
));
392 if (sprctl
& SPRITE_DEST_KEY
)
393 key
->flags
= I915_SET_COLORKEY_DESTINATION
;
394 else if (sprctl
& SPRITE_SOURCE_KEY
)
395 key
->flags
= I915_SET_COLORKEY_SOURCE
;
397 key
->flags
= I915_SET_COLORKEY_NONE
;
401 ilk_update_plane(struct drm_plane
*plane
, struct drm_framebuffer
*fb
,
402 struct drm_i915_gem_object
*obj
, int crtc_x
, int crtc_y
,
403 unsigned int crtc_w
, unsigned int crtc_h
,
404 uint32_t x
, uint32_t y
,
405 uint32_t src_w
, uint32_t src_h
)
407 struct drm_device
*dev
= plane
->dev
;
408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
409 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
410 int pipe
= intel_plane
->pipe
;
411 unsigned long dvssurf_offset
, linear_offset
;
412 u32 dvscntr
, dvsscale
;
413 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
415 dvscntr
= I915_READ(DVSCNTR(pipe
));
417 /* Mask out pixel format bits in case we change it */
418 dvscntr
&= ~DVS_PIXFORMAT_MASK
;
419 dvscntr
&= ~DVS_RGB_ORDER_XBGR
;
420 dvscntr
&= ~DVS_YUV_BYTE_ORDER_MASK
;
421 dvscntr
&= ~DVS_TILED
;
423 switch (fb
->pixel_format
) {
424 case DRM_FORMAT_XBGR8888
:
425 dvscntr
|= DVS_FORMAT_RGBX888
| DVS_RGB_ORDER_XBGR
;
427 case DRM_FORMAT_XRGB8888
:
428 dvscntr
|= DVS_FORMAT_RGBX888
;
430 case DRM_FORMAT_YUYV
:
431 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YUYV
;
433 case DRM_FORMAT_YVYU
:
434 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YVYU
;
436 case DRM_FORMAT_UYVY
:
437 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_UYVY
;
439 case DRM_FORMAT_VYUY
:
440 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_VYUY
;
446 if (obj
->tiling_mode
!= I915_TILING_NONE
)
447 dvscntr
|= DVS_TILED
;
450 dvscntr
|= DVS_TRICKLE_FEED_DISABLE
; /* must disable */
451 dvscntr
|= DVS_ENABLE
;
453 /* Sizes are 0 based */
459 intel_update_sprite_watermarks(dev
, pipe
, crtc_w
, pixel_size
, true);
462 if (IS_GEN5(dev
) || crtc_w
!= src_w
|| crtc_h
!= src_h
)
463 dvsscale
= DVS_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
465 I915_WRITE(DVSSTRIDE(pipe
), fb
->pitches
[0]);
466 I915_WRITE(DVSPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
468 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
470 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
471 pixel_size
, fb
->pitches
[0]);
472 linear_offset
-= dvssurf_offset
;
474 if (obj
->tiling_mode
!= I915_TILING_NONE
)
475 I915_WRITE(DVSTILEOFF(pipe
), (y
<< 16) | x
);
477 I915_WRITE(DVSLINOFF(pipe
), linear_offset
);
479 I915_WRITE(DVSSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
480 I915_WRITE(DVSSCALE(pipe
), dvsscale
);
481 I915_WRITE(DVSCNTR(pipe
), dvscntr
);
482 I915_MODIFY_DISPBASE(DVSSURF(pipe
),
483 i915_gem_obj_ggtt_offset(obj
) + dvssurf_offset
);
484 POSTING_READ(DVSSURF(pipe
));
488 ilk_disable_plane(struct drm_plane
*plane
)
490 struct drm_device
*dev
= plane
->dev
;
491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
492 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
493 int pipe
= intel_plane
->pipe
;
495 I915_WRITE(DVSCNTR(pipe
), I915_READ(DVSCNTR(pipe
)) & ~DVS_ENABLE
);
496 /* Disable the scaler */
497 I915_WRITE(DVSSCALE(pipe
), 0);
498 /* Flush double buffered register updates */
499 I915_MODIFY_DISPBASE(DVSSURF(pipe
), 0);
500 POSTING_READ(DVSSURF(pipe
));
504 intel_enable_primary(struct drm_crtc
*crtc
)
506 struct drm_device
*dev
= crtc
->dev
;
507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
508 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
509 int reg
= DSPCNTR(intel_crtc
->plane
);
511 if (!intel_crtc
->primary_disabled
)
514 intel_crtc
->primary_disabled
= false;
515 intel_update_fbc(dev
);
517 I915_WRITE(reg
, I915_READ(reg
) | DISPLAY_PLANE_ENABLE
);
521 intel_disable_primary(struct drm_crtc
*crtc
)
523 struct drm_device
*dev
= crtc
->dev
;
524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
525 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
526 int reg
= DSPCNTR(intel_crtc
->plane
);
528 if (intel_crtc
->primary_disabled
)
531 I915_WRITE(reg
, I915_READ(reg
) & ~DISPLAY_PLANE_ENABLE
);
533 intel_crtc
->primary_disabled
= true;
534 intel_update_fbc(dev
);
538 ilk_update_colorkey(struct drm_plane
*plane
,
539 struct drm_intel_sprite_colorkey
*key
)
541 struct drm_device
*dev
= plane
->dev
;
542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
543 struct intel_plane
*intel_plane
;
547 intel_plane
= to_intel_plane(plane
);
549 I915_WRITE(DVSKEYVAL(intel_plane
->pipe
), key
->min_value
);
550 I915_WRITE(DVSKEYMAX(intel_plane
->pipe
), key
->max_value
);
551 I915_WRITE(DVSKEYMSK(intel_plane
->pipe
), key
->channel_mask
);
553 dvscntr
= I915_READ(DVSCNTR(intel_plane
->pipe
));
554 dvscntr
&= ~(DVS_SOURCE_KEY
| DVS_DEST_KEY
);
555 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
556 dvscntr
|= DVS_DEST_KEY
;
557 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
558 dvscntr
|= DVS_SOURCE_KEY
;
559 I915_WRITE(DVSCNTR(intel_plane
->pipe
), dvscntr
);
561 POSTING_READ(DVSKEYMSK(intel_plane
->pipe
));
567 ilk_get_colorkey(struct drm_plane
*plane
, struct drm_intel_sprite_colorkey
*key
)
569 struct drm_device
*dev
= plane
->dev
;
570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
571 struct intel_plane
*intel_plane
;
574 intel_plane
= to_intel_plane(plane
);
576 key
->min_value
= I915_READ(DVSKEYVAL(intel_plane
->pipe
));
577 key
->max_value
= I915_READ(DVSKEYMAX(intel_plane
->pipe
));
578 key
->channel_mask
= I915_READ(DVSKEYMSK(intel_plane
->pipe
));
581 dvscntr
= I915_READ(DVSCNTR(intel_plane
->pipe
));
583 if (dvscntr
& DVS_DEST_KEY
)
584 key
->flags
= I915_SET_COLORKEY_DESTINATION
;
585 else if (dvscntr
& DVS_SOURCE_KEY
)
586 key
->flags
= I915_SET_COLORKEY_SOURCE
;
588 key
->flags
= I915_SET_COLORKEY_NONE
;
592 format_is_yuv(uint32_t format
)
595 case DRM_FORMAT_YUYV
:
596 case DRM_FORMAT_UYVY
:
597 case DRM_FORMAT_VYUY
:
598 case DRM_FORMAT_YVYU
:
606 intel_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
607 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
608 unsigned int crtc_w
, unsigned int crtc_h
,
609 uint32_t src_x
, uint32_t src_y
,
610 uint32_t src_w
, uint32_t src_h
)
612 struct drm_device
*dev
= plane
->dev
;
613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
614 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
615 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
616 struct intel_framebuffer
*intel_fb
;
617 struct drm_i915_gem_object
*obj
, *old_obj
;
618 int pipe
= intel_plane
->pipe
;
619 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
622 bool disable_primary
= false;
625 int max_scale
, min_scale
;
626 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
627 struct drm_rect src
= {
628 /* sample coordinates in 16.16 fixed point */
634 struct drm_rect dst
= {
637 .x2
= crtc_x
+ crtc_w
,
639 .y2
= crtc_y
+ crtc_h
,
641 const struct drm_rect clip
= {
642 .x2
= crtc
->mode
.hdisplay
,
643 .y2
= crtc
->mode
.vdisplay
,
646 intel_fb
= to_intel_framebuffer(fb
);
649 old_obj
= intel_plane
->obj
;
651 intel_plane
->crtc_x
= crtc_x
;
652 intel_plane
->crtc_y
= crtc_y
;
653 intel_plane
->crtc_w
= crtc_w
;
654 intel_plane
->crtc_h
= crtc_h
;
655 intel_plane
->src_x
= src_x
;
656 intel_plane
->src_y
= src_y
;
657 intel_plane
->src_w
= src_w
;
658 intel_plane
->src_h
= src_h
;
660 /* Pipe must be running... */
661 if (!(I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_ENABLE
)) {
662 DRM_DEBUG_KMS("Pipe disabled\n");
666 /* Don't modify another pipe's plane */
667 if (intel_plane
->pipe
!= intel_crtc
->pipe
) {
668 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
672 /* FIXME check all gen limits */
673 if (fb
->width
< 3 || fb
->height
< 3 || fb
->pitches
[0] > 16384) {
674 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
678 /* Sprite planes can be linear or x-tiled surfaces */
679 switch (obj
->tiling_mode
) {
680 case I915_TILING_NONE
:
684 DRM_DEBUG_KMS("Unsupported tiling mode\n");
689 * FIXME the following code does a bunch of fuzzy adjustments to the
690 * coordinates and sizes. We probably need some way to decide whether
691 * more strict checking should be done instead.
693 max_scale
= intel_plane
->max_downscale
<< 16;
694 min_scale
= intel_plane
->can_scale
? 1 : (1 << 16);
696 hscale
= drm_rect_calc_hscale_relaxed(&src
, &dst
, min_scale
, max_scale
);
699 vscale
= drm_rect_calc_vscale_relaxed(&src
, &dst
, min_scale
, max_scale
);
702 visible
= drm_rect_clip_scaled(&src
, &dst
, &clip
, hscale
, vscale
);
706 crtc_w
= drm_rect_width(&dst
);
707 crtc_h
= drm_rect_height(&dst
);
710 /* check again in case clipping clamped the results */
711 hscale
= drm_rect_calc_hscale(&src
, &dst
, min_scale
, max_scale
);
713 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
714 drm_rect_debug_print(&src
, true);
715 drm_rect_debug_print(&dst
, false);
720 vscale
= drm_rect_calc_vscale(&src
, &dst
, min_scale
, max_scale
);
722 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
723 drm_rect_debug_print(&src
, true);
724 drm_rect_debug_print(&dst
, false);
729 /* Make the source viewport size an exact multiple of the scaling factors. */
730 drm_rect_adjust_size(&src
,
731 drm_rect_width(&dst
) * hscale
- drm_rect_width(&src
),
732 drm_rect_height(&dst
) * vscale
- drm_rect_height(&src
));
734 /* sanity check to make sure the src viewport wasn't enlarged */
735 WARN_ON(src
.x1
< (int) src_x
||
736 src
.y1
< (int) src_y
||
737 src
.x2
> (int) (src_x
+ src_w
) ||
738 src
.y2
> (int) (src_y
+ src_h
));
741 * Hardware doesn't handle subpixel coordinates.
742 * Adjust to (macro)pixel boundary, but be careful not to
743 * increase the source viewport size, because that could
744 * push the downscaling factor out of bounds.
746 src_x
= src
.x1
>> 16;
747 src_w
= drm_rect_width(&src
) >> 16;
748 src_y
= src
.y1
>> 16;
749 src_h
= drm_rect_height(&src
) >> 16;
751 if (format_is_yuv(fb
->pixel_format
)) {
756 * Must keep src and dst the
757 * same if we can't scale.
759 if (!intel_plane
->can_scale
)
767 /* Check size restrictions when scaling */
768 if (visible
&& (src_w
!= crtc_w
|| src_h
!= crtc_h
)) {
769 unsigned int width_bytes
;
771 WARN_ON(!intel_plane
->can_scale
);
773 /* FIXME interlacing min height is 6 */
775 if (crtc_w
< 3 || crtc_h
< 3)
778 if (src_w
< 3 || src_h
< 3)
781 width_bytes
= ((src_x
* pixel_size
) & 63) + src_w
* pixel_size
;
783 if (src_w
> 2048 || src_h
> 2048 ||
784 width_bytes
> 4096 || fb
->pitches
[0] > 4096) {
785 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
791 dst
.x2
= crtc_x
+ crtc_w
;
793 dst
.y2
= crtc_y
+ crtc_h
;
796 * If the sprite is completely covering the primary plane,
797 * we can disable the primary and save power.
799 disable_primary
= drm_rect_equals(&dst
, &clip
);
800 WARN_ON(disable_primary
&& !visible
);
802 mutex_lock(&dev
->struct_mutex
);
804 /* Note that this will apply the VT-d workaround for scanouts,
805 * which is more restrictive than required for sprites. (The
806 * primary plane requires 256KiB alignment with 64 PTE padding,
807 * the sprite planes only require 128KiB alignment and 32 PTE padding.
809 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
813 intel_plane
->obj
= obj
;
816 * Be sure to re-enable the primary before the sprite is no longer
819 if (!disable_primary
)
820 intel_enable_primary(crtc
);
823 intel_plane
->update_plane(plane
, fb
, obj
,
824 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
825 src_x
, src_y
, src_w
, src_h
);
827 intel_plane
->disable_plane(plane
);
830 intel_disable_primary(crtc
);
832 /* Unpin old obj after new one is active to avoid ugliness */
835 * It's fairly common to simply update the position of
836 * an existing object. In that case, we don't need to
837 * wait for vblank to avoid ugliness, we only need to
838 * do the pin & ref bookkeeping.
840 if (old_obj
!= obj
) {
841 mutex_unlock(&dev
->struct_mutex
);
842 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
843 mutex_lock(&dev
->struct_mutex
);
845 intel_unpin_fb_obj(old_obj
);
849 mutex_unlock(&dev
->struct_mutex
);
854 intel_disable_plane(struct drm_plane
*plane
)
856 struct drm_device
*dev
= plane
->dev
;
857 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
861 intel_enable_primary(plane
->crtc
);
862 intel_plane
->disable_plane(plane
);
864 if (!intel_plane
->obj
)
867 intel_wait_for_vblank(dev
, intel_plane
->pipe
);
869 mutex_lock(&dev
->struct_mutex
);
870 intel_unpin_fb_obj(intel_plane
->obj
);
871 intel_plane
->obj
= NULL
;
872 mutex_unlock(&dev
->struct_mutex
);
878 static void intel_destroy_plane(struct drm_plane
*plane
)
880 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
881 intel_disable_plane(plane
);
882 drm_plane_cleanup(plane
);
886 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
887 struct drm_file
*file_priv
)
889 struct drm_intel_sprite_colorkey
*set
= data
;
890 struct drm_mode_object
*obj
;
891 struct drm_plane
*plane
;
892 struct intel_plane
*intel_plane
;
895 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
898 /* Make sure we don't try to enable both src & dest simultaneously */
899 if ((set
->flags
& (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
)) == (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
))
902 drm_modeset_lock_all(dev
);
904 obj
= drm_mode_object_find(dev
, set
->plane_id
, DRM_MODE_OBJECT_PLANE
);
910 plane
= obj_to_plane(obj
);
911 intel_plane
= to_intel_plane(plane
);
912 ret
= intel_plane
->update_colorkey(plane
, set
);
915 drm_modeset_unlock_all(dev
);
919 int intel_sprite_get_colorkey(struct drm_device
*dev
, void *data
,
920 struct drm_file
*file_priv
)
922 struct drm_intel_sprite_colorkey
*get
= data
;
923 struct drm_mode_object
*obj
;
924 struct drm_plane
*plane
;
925 struct intel_plane
*intel_plane
;
928 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
931 drm_modeset_lock_all(dev
);
933 obj
= drm_mode_object_find(dev
, get
->plane_id
, DRM_MODE_OBJECT_PLANE
);
939 plane
= obj_to_plane(obj
);
940 intel_plane
= to_intel_plane(plane
);
941 intel_plane
->get_colorkey(plane
, get
);
944 drm_modeset_unlock_all(dev
);
948 void intel_plane_restore(struct drm_plane
*plane
)
950 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
952 if (!plane
->crtc
|| !plane
->fb
)
955 intel_update_plane(plane
, plane
->crtc
, plane
->fb
,
956 intel_plane
->crtc_x
, intel_plane
->crtc_y
,
957 intel_plane
->crtc_w
, intel_plane
->crtc_h
,
958 intel_plane
->src_x
, intel_plane
->src_y
,
959 intel_plane
->src_w
, intel_plane
->src_h
);
962 void intel_plane_disable(struct drm_plane
*plane
)
964 if (!plane
->crtc
|| !plane
->fb
)
967 intel_disable_plane(plane
);
970 static const struct drm_plane_funcs intel_plane_funcs
= {
971 .update_plane
= intel_update_plane
,
972 .disable_plane
= intel_disable_plane
,
973 .destroy
= intel_destroy_plane
,
976 static uint32_t ilk_plane_formats
[] = {
984 static uint32_t snb_plane_formats
[] = {
993 static uint32_t vlv_plane_formats
[] = {
999 DRM_FORMAT_XBGR2101010
,
1000 DRM_FORMAT_ABGR2101010
,
1008 intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
)
1010 struct intel_plane
*intel_plane
;
1011 unsigned long possible_crtcs
;
1012 const uint32_t *plane_formats
;
1013 int num_plane_formats
;
1016 if (INTEL_INFO(dev
)->gen
< 5)
1019 intel_plane
= kzalloc(sizeof(struct intel_plane
), GFP_KERNEL
);
1023 switch (INTEL_INFO(dev
)->gen
) {
1026 intel_plane
->can_scale
= true;
1027 intel_plane
->max_downscale
= 16;
1028 intel_plane
->update_plane
= ilk_update_plane
;
1029 intel_plane
->disable_plane
= ilk_disable_plane
;
1030 intel_plane
->update_colorkey
= ilk_update_colorkey
;
1031 intel_plane
->get_colorkey
= ilk_get_colorkey
;
1034 plane_formats
= snb_plane_formats
;
1035 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1037 plane_formats
= ilk_plane_formats
;
1038 num_plane_formats
= ARRAY_SIZE(ilk_plane_formats
);
1043 if (IS_IVYBRIDGE(dev
)) {
1044 intel_plane
->can_scale
= true;
1045 intel_plane
->max_downscale
= 2;
1047 intel_plane
->can_scale
= false;
1048 intel_plane
->max_downscale
= 1;
1051 if (IS_VALLEYVIEW(dev
)) {
1052 intel_plane
->update_plane
= vlv_update_plane
;
1053 intel_plane
->disable_plane
= vlv_disable_plane
;
1054 intel_plane
->update_colorkey
= vlv_update_colorkey
;
1055 intel_plane
->get_colorkey
= vlv_get_colorkey
;
1057 plane_formats
= vlv_plane_formats
;
1058 num_plane_formats
= ARRAY_SIZE(vlv_plane_formats
);
1060 intel_plane
->update_plane
= ivb_update_plane
;
1061 intel_plane
->disable_plane
= ivb_disable_plane
;
1062 intel_plane
->update_colorkey
= ivb_update_colorkey
;
1063 intel_plane
->get_colorkey
= ivb_get_colorkey
;
1065 plane_formats
= snb_plane_formats
;
1066 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1075 intel_plane
->pipe
= pipe
;
1076 intel_plane
->plane
= plane
;
1077 possible_crtcs
= (1 << pipe
);
1078 ret
= drm_plane_init(dev
, &intel_plane
->base
, possible_crtcs
,
1080 plane_formats
, num_plane_formats
,