drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
  41 {
  42         /* paranoia */
  43         if (!mode->crtc_htotal)
  44                 return 1;
  45
  46         return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
  47 }
  48
  49 static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
  50 {
  51         struct drm_device *dev = crtc->base.dev;
  52         const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
  53         enum pipe pipe = crtc->pipe;
  54         long timeout = msecs_to_jiffies_timeout(1);
  55         int scanline, min, max, vblank_start;
  56         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  57         DEFINE_WAIT(wait);
  58
  59         WARN_ON(!drm_modeset_is_locked(&crtc->base.mutex));
  60
  61         vblank_start = mode->crtc_vblank_start;
  62         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  63                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  64
  65         /* FIXME needs to be calibrated sensibly */
  66         min = vblank_start - usecs_to_scanlines(mode, 100);
  67         max = vblank_start - 1;
  68
  69         if (min <= 0 || max <= 0)
  70                 return false;
  71
  72         if (WARN_ON(drm_vblank_get(dev, pipe)))
  73                 return false;
  74
  75         local_irq_disable();
  76
  77         trace_i915_pipe_update_start(crtc, min, max);
  78
  79         for (;;) {
  80                 /*
  81                  * prepare_to_wait() has a memory barrier, which guarantees
  82                  * other CPUs can see the task state update by the time we
  83                  * read the scanline.
  84                  */
  85                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
  86
  87                 scanline = intel_get_crtc_scanline(crtc);
  88                 if (scanline < min || scanline > max)
  89                         break;
  90
  91                 if (timeout <= 0) {
  92                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
  93                                   pipe_name(crtc->pipe));
  94                         break;
  95                 }
  96
  97                 local_irq_enable();
  98
  99                 timeout = schedule_timeout(timeout);
 100
 101                 local_irq_disable();
 102         }
 103
 104         finish_wait(wq, &wait);
 105
 106         drm_vblank_put(dev, pipe);
 107
 108         *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 109
 110         trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count);
 111
 112         return true;
 113 }
 114
 115 static void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
 116 {
 117         struct drm_device *dev = crtc->base.dev;
 118         enum pipe pipe = crtc->pipe;
 119         u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 120
 121         trace_i915_pipe_update_end(crtc, end_vbl_count);
 122
 123         local_irq_enable();
 124
 125         if (start_vbl_count != end_vbl_count)
 126                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
 127                           pipe_name(pipe), start_vbl_count, end_vbl_count);
 128 }
 129
 130 static void intel_update_primary_plane(struct intel_crtc *crtc)
 131 {
 132         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 133         int reg = DSPCNTR(crtc->plane);
 134
 135         if (crtc->primary_enabled)
 136                 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
 137         else
 138                 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
 139 }
 140
 141 static void
 142 vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 143                  struct drm_framebuffer *fb,
 144                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 145                  unsigned int crtc_w, unsigned int crtc_h,
 146                  uint32_t x, uint32_t y,
 147                  uint32_t src_w, uint32_t src_h)
 148 {
 149         struct drm_device *dev = dplane->dev;
 150         struct drm_i915_private *dev_priv = dev->dev_private;
 151         struct intel_plane *intel_plane = to_intel_plane(dplane);
 152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 153         int pipe = intel_plane->pipe;
 154         int plane = intel_plane->plane;
 155         u32 sprctl;
 156         unsigned long sprsurf_offset, linear_offset;
 157         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 158         u32 start_vbl_count;
 159         bool atomic_update;
 160
 161         sprctl = I915_READ(SPCNTR(pipe, plane));
 162
 163         /* Mask out pixel format bits in case we change it */
 164         sprctl &= ~SP_PIXFORMAT_MASK;
 165         sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
 166         sprctl &= ~SP_TILED;
 167
 168         switch (fb->pixel_format) {
 169         case DRM_FORMAT_YUYV:
 170                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 171                 break;
 172         case DRM_FORMAT_YVYU:
 173                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 174                 break;
 175         case DRM_FORMAT_UYVY:
 176                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 177                 break;
 178         case DRM_FORMAT_VYUY:
 179                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 180                 break;
 181         case DRM_FORMAT_RGB565:
 182                 sprctl |= SP_FORMAT_BGR565;
 183                 break;
 184         case DRM_FORMAT_XRGB8888:
 185                 sprctl |= SP_FORMAT_BGRX8888;
 186                 break;
 187         case DRM_FORMAT_ARGB8888:
 188                 sprctl |= SP_FORMAT_BGRA8888;
 189                 break;
 190         case DRM_FORMAT_XBGR2101010:
 191                 sprctl |= SP_FORMAT_RGBX1010102;
 192                 break;
 193         case DRM_FORMAT_ABGR2101010:
 194                 sprctl |= SP_FORMAT_RGBA1010102;
 195                 break;
 196         case DRM_FORMAT_XBGR8888:
 197                 sprctl |= SP_FORMAT_RGBX8888;
 198                 break;
 199         case DRM_FORMAT_ABGR8888:
 200                 sprctl |= SP_FORMAT_RGBA8888;
 201                 break;
 202         default:
 203                 /*
 204                  * If we get here one of the upper layers failed to filter
 205                  * out the unsupported plane formats
 206                  */
 207                 BUG();
 208                 break;
 209         }
 210
 211         /*
 212          * Enable gamma to match primary/cursor plane behaviour.
 213          * FIXME should be user controllable via propertiesa.
 214          */
 215         sprctl |= SP_GAMMA_ENABLE;
 216
 217         if (obj->tiling_mode != I915_TILING_NONE)
 218                 sprctl |= SP_TILED;
 219
 220         sprctl |= SP_ENABLE;
 221
 222         intel_update_sprite_watermarks(dplane, crtc, src_w, src_h,
 223                                        pixel_size, true,
 224                                        src_w != crtc_w || src_h != crtc_h);
 225
 226         /* Sizes are 0 based */
 227         src_w--;
 228         src_h--;
 229         crtc_w--;
 230         crtc_h--;
 231
 232         linear_offset = y * fb->pitches[0] + x * pixel_size;
 233         sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
 234                                                         obj->tiling_mode,
 235                                                         pixel_size,
 236                                                         fb->pitches[0]);
 237         linear_offset -= sprsurf_offset;
 238
 239         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
 240
 241         intel_update_primary_plane(intel_crtc);
 242
 243         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 244         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 245
 246         if (obj->tiling_mode != I915_TILING_NONE)
 247                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 248         else
 249                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 250
 251         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 252         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 253         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
 254                    sprsurf_offset);
 255
 256         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 257
 258         if (atomic_update)
 259                 intel_pipe_update_end(intel_crtc, start_vbl_count);
 260 }
 261
 262 static void
 263 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 264 {
 265         struct drm_device *dev = dplane->dev;
 266         struct drm_i915_private *dev_priv = dev->dev_private;
 267         struct intel_plane *intel_plane = to_intel_plane(dplane);
 268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 269         int pipe = intel_plane->pipe;
 270         int plane = intel_plane->plane;
 271         u32 start_vbl_count;
 272         bool atomic_update;
 273
 274         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
 275
 276         intel_update_primary_plane(intel_crtc);
 277
 278         I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
 279                    ~SP_ENABLE);
 280         /* Activate double buffered register update */
 281         I915_WRITE(SPSURF(pipe, plane), 0);
 282
 283         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 284
 285         if (atomic_update)
 286                 intel_pipe_update_end(intel_crtc, start_vbl_count);
 287
 288         intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
 289 }
 290
 291 static int
 292 vlv_update_colorkey(struct drm_plane *dplane,
 293                     struct drm_intel_sprite_colorkey *key)
 294 {
 295         struct drm_device *dev = dplane->dev;
 296         struct drm_i915_private *dev_priv = dev->dev_private;
 297         struct intel_plane *intel_plane = to_intel_plane(dplane);
 298         int pipe = intel_plane->pipe;
 299         int plane = intel_plane->plane;
 300         u32 sprctl;
 301
 302         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 303                 return -EINVAL;
 304
 305         I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 306         I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 307         I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 308
 309         sprctl = I915_READ(SPCNTR(pipe, plane));
 310         sprctl &= ~SP_SOURCE_KEY;
 311         if (key->flags & I915_SET_COLORKEY_SOURCE)
 312                 sprctl |= SP_SOURCE_KEY;
 313         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 314
 315         POSTING_READ(SPKEYMSK(pipe, plane));
 316
 317         return 0;
 318 }
 319
 320 static void
 321 vlv_get_colorkey(struct drm_plane *dplane,
 322                  struct drm_intel_sprite_colorkey *key)
 323 {
 324         struct drm_device *dev = dplane->dev;
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326         struct intel_plane *intel_plane = to_intel_plane(dplane);
 327         int pipe = intel_plane->pipe;
 328         int plane = intel_plane->plane;
 329         u32 sprctl;
 330
 331         key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
 332         key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
 333         key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
 334
 335         sprctl = I915_READ(SPCNTR(pipe, plane));
 336         if (sprctl & SP_SOURCE_KEY)
 337                 key->flags = I915_SET_COLORKEY_SOURCE;
 338         else
 339                 key->flags = I915_SET_COLORKEY_NONE;
 340 }
 341
 342 static void
 343 ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 344                  struct drm_framebuffer *fb,
 345                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 346                  unsigned int crtc_w, unsigned int crtc_h,
 347                  uint32_t x, uint32_t y,
 348                  uint32_t src_w, uint32_t src_h)
 349 {
 350         struct drm_device *dev = plane->dev;
 351         struct drm_i915_private *dev_priv = dev->dev_private;
 352         struct intel_plane *intel_plane = to_intel_plane(plane);
 353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 354         int pipe = intel_plane->pipe;
 355         u32 sprctl, sprscale = 0;
 356         unsigned long sprsurf_offset, linear_offset;
 357         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 358         u32 start_vbl_count;
 359         bool atomic_update;
 360
 361         sprctl = I915_READ(SPRCTL(pipe));
 362
 363         /* Mask out pixel format bits in case we change it */
 364         sprctl &= ~SPRITE_PIXFORMAT_MASK;
 365         sprctl &= ~SPRITE_RGB_ORDER_RGBX;
 366         sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
 367         sprctl &= ~SPRITE_TILED;
 368
 369         switch (fb->pixel_format) {
 370         case DRM_FORMAT_XBGR8888:
 371                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 372                 break;
 373         case DRM_FORMAT_XRGB8888:
 374                 sprctl |= SPRITE_FORMAT_RGBX888;
 375                 break;
 376         case DRM_FORMAT_YUYV:
 377                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 378                 break;
 379         case DRM_FORMAT_YVYU:
 380                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 381                 break;
 382         case DRM_FORMAT_UYVY:
 383                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 384                 break;
 385         case DRM_FORMAT_VYUY:
 386                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 387                 break;
 388         default:
 389                 BUG();
 390         }
 391
 392         /*
 393          * Enable gamma to match primary/cursor plane behaviour.
 394          * FIXME should be user controllable via propertiesa.
 395          */
 396         sprctl |= SPRITE_GAMMA_ENABLE;
 397
 398         if (obj->tiling_mode != I915_TILING_NONE)
 399                 sprctl |= SPRITE_TILED;
 400
 401         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 402                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 403         else
 404                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 405
 406         sprctl |= SPRITE_ENABLE;
 407
 408         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 409                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 410
 411         intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
 412                                        true,
 413                                        src_w != crtc_w || src_h != crtc_h);
 414
 415         /* Sizes are 0 based */
 416         src_w--;
 417         src_h--;
 418         crtc_w--;
 419         crtc_h--;
 420
 421         if (crtc_w != src_w || crtc_h != src_h)
 422                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 423
 424         linear_offset = y * fb->pitches[0] + x * pixel_size;
 425         sprsurf_offset =
 426                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
 427                                                pixel_size, fb->pitches[0]);
 428         linear_offset -= sprsurf_offset;
 429
 430         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
 431
 432         intel_update_primary_plane(intel_crtc);
 433
 434         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 435         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 436
 437         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 438          * register */
 439         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 440                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 441         else if (obj->tiling_mode != I915_TILING_NONE)
 442                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 443         else
 444                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 445
 446         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 447         if (intel_plane->can_scale)
 448                 I915_WRITE(SPRSCALE(pipe), sprscale);
 449         I915_WRITE(SPRCTL(pipe), sprctl);
 450         I915_WRITE(SPRSURF(pipe),
 451                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
 452
 453         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 454
 455         if (atomic_update)
 456                 intel_pipe_update_end(intel_crtc, start_vbl_count);
 457 }
 458
 459 static void
 460 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 461 {
 462         struct drm_device *dev = plane->dev;
 463         struct drm_i915_private *dev_priv = dev->dev_private;
 464         struct intel_plane *intel_plane = to_intel_plane(plane);
 465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 466         int pipe = intel_plane->pipe;
 467         u32 start_vbl_count;
 468         bool atomic_update;
 469
 470         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
 471
 472         intel_update_primary_plane(intel_crtc);
 473
 474         I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
 475         /* Can't leave the scaler enabled... */
 476         if (intel_plane->can_scale)
 477                 I915_WRITE(SPRSCALE(pipe), 0);
 478         /* Activate double buffered register update */
 479         I915_WRITE(SPRSURF(pipe), 0);
 480
 481         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 482
 483         if (atomic_update)
 484                 intel_pipe_update_end(intel_crtc, start_vbl_count);
 485
 486         /*
 487          * Avoid underruns when disabling the sprite.
 488          * FIXME remove once watermark updates are done properly.
 489          */
 490         intel_wait_for_vblank(dev, pipe);
 491
 492         intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false);
 493 }
 494
 495 static int
 496 ivb_update_colorkey(struct drm_plane *plane,
 497                     struct drm_intel_sprite_colorkey *key)
 498 {
 499         struct drm_device *dev = plane->dev;
 500         struct drm_i915_private *dev_priv = dev->dev_private;
 501         struct intel_plane *intel_plane;
 502         u32 sprctl;
 503         int ret = 0;
 504
 505         intel_plane = to_intel_plane(plane);
 506
 507         I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
 508         I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
 509         I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
 510
 511         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 512         sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
 513         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 514                 sprctl |= SPRITE_DEST_KEY;
 515         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 516                 sprctl |= SPRITE_SOURCE_KEY;
 517         I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
 518
 519         POSTING_READ(SPRKEYMSK(intel_plane->pipe));
 520
 521         return ret;
 522 }
 523
 524 static void
 525 ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 526 {
 527         struct drm_device *dev = plane->dev;
 528         struct drm_i915_private *dev_priv = dev->dev_private;
 529         struct intel_plane *intel_plane;
 530         u32 sprctl;
 531
 532         intel_plane = to_intel_plane(plane);
 533
 534         key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
 535         key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
 536         key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
 537         key->flags = 0;
 538
 539         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 540
 541         if (sprctl & SPRITE_DEST_KEY)
 542                 key->flags = I915_SET_COLORKEY_DESTINATION;
 543         else if (sprctl & SPRITE_SOURCE_KEY)
 544                 key->flags = I915_SET_COLORKEY_SOURCE;
 545         else
 546                 key->flags = I915_SET_COLORKEY_NONE;
 547 }
 548
 549 static void
 550 ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 551                  struct drm_framebuffer *fb,
 552                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 553                  unsigned int crtc_w, unsigned int crtc_h,
 554                  uint32_t x, uint32_t y,
 555                  uint32_t src_w, uint32_t src_h)
 556 {
 557         struct drm_device *dev = plane->dev;
 558         struct drm_i915_private *dev_priv = dev->dev_private;
 559         struct intel_plane *intel_plane = to_intel_plane(plane);
 560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 561         int pipe = intel_plane->pipe;
 562         unsigned long dvssurf_offset, linear_offset;
 563         u32 dvscntr, dvsscale;
 564         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 565         u32 start_vbl_count;
 566         bool atomic_update;
 567
 568         dvscntr = I915_READ(DVSCNTR(pipe));
 569
 570         /* Mask out pixel format bits in case we change it */
 571         dvscntr &= ~DVS_PIXFORMAT_MASK;
 572         dvscntr &= ~DVS_RGB_ORDER_XBGR;
 573         dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
 574         dvscntr &= ~DVS_TILED;
 575
 576         switch (fb->pixel_format) {
 577         case DRM_FORMAT_XBGR8888:
 578                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 579                 break;
 580         case DRM_FORMAT_XRGB8888:
 581                 dvscntr |= DVS_FORMAT_RGBX888;
 582                 break;
 583         case DRM_FORMAT_YUYV:
 584                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 585                 break;
 586         case DRM_FORMAT_YVYU:
 587                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 588                 break;
 589         case DRM_FORMAT_UYVY:
 590                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 591                 break;
 592         case DRM_FORMAT_VYUY:
 593                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 594                 break;
 595         default:
 596                 BUG();
 597         }
 598
 599         /*
 600          * Enable gamma to match primary/cursor plane behaviour.
 601          * FIXME should be user controllable via propertiesa.
 602          */
 603         dvscntr |= DVS_GAMMA_ENABLE;
 604
 605         if (obj->tiling_mode != I915_TILING_NONE)
 606                 dvscntr |= DVS_TILED;
 607
 608         if (IS_GEN6(dev))
 609                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 610         dvscntr |= DVS_ENABLE;
 611
 612         intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
 613                                        pixel_size, true,
 614                                        src_w != crtc_w || src_h != crtc_h);
 615
 616         /* Sizes are 0 based */
 617         src_w--;
 618         src_h--;
 619         crtc_w--;
 620         crtc_h--;
 621
 622         dvsscale = 0;
 623         if (crtc_w != src_w || crtc_h != src_h)
 624                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 625
 626         linear_offset = y * fb->pitches[0] + x * pixel_size;
 627         dvssurf_offset =
 628                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
 629                                                pixel_size, fb->pitches[0]);
 630         linear_offset -= dvssurf_offset;
 631
 632         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
 633
 634         intel_update_primary_plane(intel_crtc);
 635
 636         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 637         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 638
 639         if (obj->tiling_mode != I915_TILING_NONE)
 640                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 641         else
 642                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 643
 644         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 645         I915_WRITE(DVSSCALE(pipe), dvsscale);
 646         I915_WRITE(DVSCNTR(pipe), dvscntr);
 647         I915_WRITE(DVSSURF(pipe),
 648                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
 649
 650         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 651
 652         if (atomic_update)
 653                 intel_pipe_update_end(intel_crtc, start_vbl_count);
 654 }
 655
 656 static void
 657 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 658 {
 659         struct drm_device *dev = plane->dev;
 660         struct drm_i915_private *dev_priv = dev->dev_private;
 661         struct intel_plane *intel_plane = to_intel_plane(plane);
 662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 663         int pipe = intel_plane->pipe;
 664         u32 start_vbl_count;
 665         bool atomic_update;
 666
 667         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
 668
 669         intel_update_primary_plane(intel_crtc);
 670
 671         I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
 672         /* Disable the scaler */
 673         I915_WRITE(DVSSCALE(pipe), 0);
 674         /* Flush double buffered register updates */
 675         I915_WRITE(DVSSURF(pipe), 0);
 676
 677         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 678
 679         if (atomic_update)
 680                 intel_pipe_update_end(intel_crtc, start_vbl_count);
 681
 682         /*
 683          * Avoid underruns when disabling the sprite.
 684          * FIXME remove once watermark updates are done properly.
 685          */
 686         intel_wait_for_vblank(dev, pipe);
 687
 688         intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false);
 689 }
 690
 691 static void
 692 intel_post_enable_primary(struct drm_crtc *crtc)
 693 {
 694         struct drm_device *dev = crtc->dev;
 695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 696
 697         /*
 698          * BDW signals flip done immediately if the plane
 699          * is disabled, even if the plane enable is already
 700          * armed to occur at the next vblank :(
 701          */
 702         if (IS_BROADWELL(dev))
 703                 intel_wait_for_vblank(dev, intel_crtc->pipe);
 704
 705         /*
 706          * FIXME IPS should be fine as long as one plane is
 707          * enabled, but in practice it seems to have problems
 708          * when going from primary only to sprite only and vice
 709          * versa.
 710          */
 711         hsw_enable_ips(intel_crtc);
 712
 713         mutex_lock(&dev->struct_mutex);
 714         intel_update_fbc(dev);
 715         mutex_unlock(&dev->struct_mutex);
 716 }
 717
 718 static void
 719 intel_pre_disable_primary(struct drm_crtc *crtc)
 720 {
 721         struct drm_device *dev = crtc->dev;
 722         struct drm_i915_private *dev_priv = dev->dev_private;
 723         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 724
 725         mutex_lock(&dev->struct_mutex);
 726         if (dev_priv->fbc.plane == intel_crtc->plane)
 727                 intel_disable_fbc(dev);
 728         mutex_unlock(&dev->struct_mutex);
 729
 730         /*
 731          * FIXME IPS should be fine as long as one plane is
 732          * enabled, but in practice it seems to have problems
 733          * when going from primary only to sprite only and vice
 734          * versa.
 735          */
 736         hsw_disable_ips(intel_crtc);
 737 }
 738
 739 static int
 740 ilk_update_colorkey(struct drm_plane *plane,
 741                     struct drm_intel_sprite_colorkey *key)
 742 {
 743         struct drm_device *dev = plane->dev;
 744         struct drm_i915_private *dev_priv = dev->dev_private;
 745         struct intel_plane *intel_plane;
 746         u32 dvscntr;
 747         int ret = 0;
 748
 749         intel_plane = to_intel_plane(plane);
 750
 751         I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
 752         I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
 753         I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
 754
 755         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 756         dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
 757         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 758                 dvscntr |= DVS_DEST_KEY;
 759         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 760                 dvscntr |= DVS_SOURCE_KEY;
 761         I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
 762
 763         POSTING_READ(DVSKEYMSK(intel_plane->pipe));
 764
 765         return ret;
 766 }
 767
 768 static void
 769 ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 770 {
 771         struct drm_device *dev = plane->dev;
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773         struct intel_plane *intel_plane;
 774         u32 dvscntr;
 775
 776         intel_plane = to_intel_plane(plane);
 777
 778         key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
 779         key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
 780         key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
 781         key->flags = 0;
 782
 783         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 784
 785         if (dvscntr & DVS_DEST_KEY)
 786                 key->flags = I915_SET_COLORKEY_DESTINATION;
 787         else if (dvscntr & DVS_SOURCE_KEY)
 788                 key->flags = I915_SET_COLORKEY_SOURCE;
 789         else
 790                 key->flags = I915_SET_COLORKEY_NONE;
 791 }
 792
 793 static bool
 794 format_is_yuv(uint32_t format)
 795 {
 796         switch (format) {
 797         case DRM_FORMAT_YUYV:
 798         case DRM_FORMAT_UYVY:
 799         case DRM_FORMAT_VYUY:
 800         case DRM_FORMAT_YVYU:
 801                 return true;
 802         default:
 803                 return false;
 804         }
 805 }
 806
 807 static bool colorkey_enabled(struct intel_plane *intel_plane)
 808 {
 809         struct drm_intel_sprite_colorkey key;
 810
 811         intel_plane->get_colorkey(&intel_plane->base, &key);
 812
 813         return key.flags != I915_SET_COLORKEY_NONE;
 814 }
 815
 816 static int
 817 intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 818                    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
 819                    unsigned int crtc_w, unsigned int crtc_h,
 820                    uint32_t src_x, uint32_t src_y,
 821                    uint32_t src_w, uint32_t src_h)
 822 {
 823         struct drm_device *dev = plane->dev;
 824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 825         struct intel_plane *intel_plane = to_intel_plane(plane);
 826         enum pipe pipe = intel_crtc->pipe;
 827         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 828         struct drm_i915_gem_object *obj = intel_fb->obj;
 829         struct drm_i915_gem_object *old_obj = intel_plane->obj;
 830         int ret;
 831         bool primary_enabled;
 832         bool visible;
 833         int hscale, vscale;
 834         int max_scale, min_scale;
 835         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 836         struct drm_rect src = {
 837                 /* sample coordinates in 16.16 fixed point */
 838                 .x1 = src_x,
 839                 .x2 = src_x + src_w,
 840                 .y1 = src_y,
 841                 .y2 = src_y + src_h,
 842         };
 843         struct drm_rect dst = {
 844                 /* integer pixels */
 845                 .x1 = crtc_x,
 846                 .x2 = crtc_x + crtc_w,
 847                 .y1 = crtc_y,
 848                 .y2 = crtc_y + crtc_h,
 849         };
 850         const struct drm_rect clip = {
 851                 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
 852                 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
 853         };
 854         const struct {
 855                 int crtc_x, crtc_y;
 856                 unsigned int crtc_w, crtc_h;
 857                 uint32_t src_x, src_y, src_w, src_h;
 858         } orig = {
 859                 .crtc_x = crtc_x,
 860                 .crtc_y = crtc_y,
 861                 .crtc_w = crtc_w,
 862                 .crtc_h = crtc_h,
 863                 .src_x = src_x,
 864                 .src_y = src_y,
 865                 .src_w = src_w,
 866                 .src_h = src_h,
 867         };
 868
 869         /* Don't modify another pipe's plane */
 870         if (intel_plane->pipe != intel_crtc->pipe) {
 871                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 872                 return -EINVAL;
 873         }
 874
 875         /* FIXME check all gen limits */
 876         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 877                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 878                 return -EINVAL;
 879         }
 880
 881         /* Sprite planes can be linear or x-tiled surfaces */
 882         switch (obj->tiling_mode) {
 883                 case I915_TILING_NONE:
 884                 case I915_TILING_X:
 885                         break;
 886                 default:
 887                         DRM_DEBUG_KMS("Unsupported tiling mode\n");
 888                         return -EINVAL;
 889         }
 890
 891         /*
 892          * FIXME the following code does a bunch of fuzzy adjustments to the
 893          * coordinates and sizes. We probably need some way to decide whether
 894          * more strict checking should be done instead.
 895          */
 896         max_scale = intel_plane->max_downscale << 16;
 897         min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 898
 899         hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale);
 900         BUG_ON(hscale < 0);
 901
 902         vscale = drm_rect_calc_vscale_relaxed(&src, &dst, min_scale, max_scale);
 903         BUG_ON(vscale < 0);
 904
 905         visible = drm_rect_clip_scaled(&src, &dst, &clip, hscale, vscale);
 906
 907         crtc_x = dst.x1;
 908         crtc_y = dst.y1;
 909         crtc_w = drm_rect_width(&dst);
 910         crtc_h = drm_rect_height(&dst);
 911
 912         if (visible) {
 913                 /* check again in case clipping clamped the results */
 914                 hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale);
 915                 if (hscale < 0) {
 916                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 917                         drm_rect_debug_print(&src, true);
 918                         drm_rect_debug_print(&dst, false);
 919
 920                         return hscale;
 921                 }
 922
 923                 vscale = drm_rect_calc_vscale(&src, &dst, min_scale, max_scale);
 924                 if (vscale < 0) {
 925                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 926                         drm_rect_debug_print(&src, true);
 927                         drm_rect_debug_print(&dst, false);
 928
 929                         return vscale;
 930                 }
 931
 932                 /* Make the source viewport size an exact multiple of the scaling factors. */
 933                 drm_rect_adjust_size(&src,
 934                                      drm_rect_width(&dst) * hscale - drm_rect_width(&src),
 935                                      drm_rect_height(&dst) * vscale - drm_rect_height(&src));
 936
 937                 /* sanity check to make sure the src viewport wasn't enlarged */
 938                 WARN_ON(src.x1 < (int) src_x ||
 939                         src.y1 < (int) src_y ||
 940                         src.x2 > (int) (src_x + src_w) ||
 941                         src.y2 > (int) (src_y + src_h));
 942
 943                 /*
 944                  * Hardware doesn't handle subpixel coordinates.
 945                  * Adjust to (macro)pixel boundary, but be careful not to
 946                  * increase the source viewport size, because that could
 947                  * push the downscaling factor out of bounds.
 948                  */
 949                 src_x = src.x1 >> 16;
 950                 src_w = drm_rect_width(&src) >> 16;
 951                 src_y = src.y1 >> 16;
 952                 src_h = drm_rect_height(&src) >> 16;
 953
 954                 if (format_is_yuv(fb->pixel_format)) {
 955                         src_x &= ~1;
 956                         src_w &= ~1;
 957
 958                         /*
 959                          * Must keep src and dst the
 960                          * same if we can't scale.
 961                          */
 962                         if (!intel_plane->can_scale)
 963                                 crtc_w &= ~1;
 964
 965                         if (crtc_w == 0)
 966                                 visible = false;
 967                 }
 968         }
 969
 970         /* Check size restrictions when scaling */
 971         if (visible && (src_w != crtc_w || src_h != crtc_h)) {
 972                 unsigned int width_bytes;
 973
 974                 WARN_ON(!intel_plane->can_scale);
 975
 976                 /* FIXME interlacing min height is 6 */
 977
 978                 if (crtc_w < 3 || crtc_h < 3)
 979                         visible = false;
 980
 981                 if (src_w < 3 || src_h < 3)
 982                         visible = false;
 983
 984                 width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size;
 985
 986                 if (src_w > 2048 || src_h > 2048 ||
 987                     width_bytes > 4096 || fb->pitches[0] > 4096) {
 988                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 989                         return -EINVAL;
 990                 }
 991         }
 992
 993         dst.x1 = crtc_x;
 994         dst.x2 = crtc_x + crtc_w;
 995         dst.y1 = crtc_y;
 996         dst.y2 = crtc_y + crtc_h;
 997
 998         /*
 999          * If the sprite is completely covering the primary plane,
1000          * we can disable the primary and save power.
1001          */
1002         primary_enabled = !drm_rect_equals(&dst, &clip) || colorkey_enabled(intel_plane);
1003         WARN_ON(!primary_enabled && !visible && intel_crtc->active);
1004
1005         mutex_lock(&dev->struct_mutex);
1006
1007         /* Note that this will apply the VT-d workaround for scanouts,
1008          * which is more restrictive than required for sprites. (The
1009          * primary plane requires 256KiB alignment with 64 PTE padding,
1010          * the sprite planes only require 128KiB alignment and 32 PTE padding.
1011          */
1012         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
1013
1014         i915_gem_track_fb(old_obj, obj,
1015                           INTEL_FRONTBUFFER_SPRITE(pipe));
1016         mutex_unlock(&dev->struct_mutex);
1017
1018         if (ret)
1019                 return ret;
1020
1021         intel_plane->crtc_x = orig.crtc_x;
1022         intel_plane->crtc_y = orig.crtc_y;
1023         intel_plane->crtc_w = orig.crtc_w;
1024         intel_plane->crtc_h = orig.crtc_h;
1025         intel_plane->src_x = orig.src_x;
1026         intel_plane->src_y = orig.src_y;
1027         intel_plane->src_w = orig.src_w;
1028         intel_plane->src_h = orig.src_h;
1029         intel_plane->obj = obj;
1030
1031         if (intel_crtc->active) {
1032                 bool primary_was_enabled = intel_crtc->primary_enabled;
1033
1034                 intel_crtc->primary_enabled = primary_enabled;
1035
1036                 if (primary_was_enabled != primary_enabled)
1037                         intel_crtc_wait_for_pending_flips(crtc);
1038
1039                 if (primary_was_enabled && !primary_enabled)
1040                         intel_pre_disable_primary(crtc);
1041
1042                 if (visible)
1043                         intel_plane->update_plane(plane, crtc, fb, obj,
1044                                                   crtc_x, crtc_y, crtc_w, crtc_h,
1045                                                   src_x, src_y, src_w, src_h);
1046                 else
1047                         intel_plane->disable_plane(plane, crtc);
1048
1049                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_SPRITE(pipe));
1050
1051                 if (!primary_was_enabled && primary_enabled)
1052                         intel_post_enable_primary(crtc);
1053         }
1054
1055         /* Unpin old obj after new one is active to avoid ugliness */
1056         if (old_obj) {
1057                 /*
1058                  * It's fairly common to simply update the position of
1059                  * an existing object.  In that case, we don't need to
1060                  * wait for vblank to avoid ugliness, we only need to
1061                  * do the pin & ref bookkeeping.
1062                  */
1063                 if (old_obj != obj && intel_crtc->active)
1064                         intel_wait_for_vblank(dev, intel_crtc->pipe);
1065
1066                 mutex_lock(&dev->struct_mutex);
1067                 intel_unpin_fb_obj(old_obj);
1068                 mutex_unlock(&dev->struct_mutex);
1069         }
1070
1071         return 0;
1072 }
1073
1074 static int
1075 intel_disable_plane(struct drm_plane *plane)
1076 {
1077         struct drm_device *dev = plane->dev;
1078         struct intel_plane *intel_plane = to_intel_plane(plane);
1079         struct intel_crtc *intel_crtc;
1080         enum pipe pipe;
1081
1082         if (!plane->fb)
1083                 return 0;
1084
1085         if (WARN_ON(!plane->crtc))
1086                 return -EINVAL;
1087
1088         intel_crtc = to_intel_crtc(plane->crtc);
1089         pipe = intel_crtc->pipe;
1090
1091         if (intel_crtc->active) {
1092                 bool primary_was_enabled = intel_crtc->primary_enabled;
1093
1094                 intel_crtc->primary_enabled = true;
1095
1096                 intel_plane->disable_plane(plane, plane->crtc);
1097
1098                 if (!primary_was_enabled && intel_crtc->primary_enabled)
1099                         intel_post_enable_primary(plane->crtc);
1100         }
1101
1102         if (intel_plane->obj) {
1103                 if (intel_crtc->active)
1104                         intel_wait_for_vblank(dev, intel_plane->pipe);
1105
1106                 mutex_lock(&dev->struct_mutex);
1107                 intel_unpin_fb_obj(intel_plane->obj);
1108                 i915_gem_track_fb(intel_plane->obj, NULL,
1109                                   INTEL_FRONTBUFFER_SPRITE(pipe));
1110                 mutex_unlock(&dev->struct_mutex);
1111
1112                 intel_plane->obj = NULL;
1113         }
1114
1115         return 0;
1116 }
1117
1118 static void intel_destroy_plane(struct drm_plane *plane)
1119 {
1120         struct intel_plane *intel_plane = to_intel_plane(plane);
1121         intel_disable_plane(plane);
1122         drm_plane_cleanup(plane);
1123         kfree(intel_plane);
1124 }
1125
1126 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1127                               struct drm_file *file_priv)
1128 {
1129         struct drm_intel_sprite_colorkey *set = data;
1130         struct drm_plane *plane;
1131         struct intel_plane *intel_plane;
1132         int ret = 0;
1133
1134         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1135                 return -ENODEV;
1136
1137         /* Make sure we don't try to enable both src & dest simultaneously */
1138         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1139                 return -EINVAL;
1140
1141         drm_modeset_lock_all(dev);
1142
1143         plane = drm_plane_find(dev, set->plane_id);
1144         if (!plane) {
1145                 ret = -ENOENT;
1146                 goto out_unlock;
1147         }
1148
1149         intel_plane = to_intel_plane(plane);
1150         ret = intel_plane->update_colorkey(plane, set);
1151
1152 out_unlock:
1153         drm_modeset_unlock_all(dev);
1154         return ret;
1155 }
1156
1157 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1158                               struct drm_file *file_priv)
1159 {
1160         struct drm_intel_sprite_colorkey *get = data;
1161         struct drm_plane *plane;
1162         struct intel_plane *intel_plane;
1163         int ret = 0;
1164
1165         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1166                 return -ENODEV;
1167
1168         drm_modeset_lock_all(dev);
1169
1170         plane = drm_plane_find(dev, get->plane_id);
1171         if (!plane) {
1172                 ret = -ENOENT;
1173                 goto out_unlock;
1174         }
1175
1176         intel_plane = to_intel_plane(plane);
1177         intel_plane->get_colorkey(plane, get);
1178
1179 out_unlock:
1180         drm_modeset_unlock_all(dev);
1181         return ret;
1182 }
1183
1184 void intel_plane_restore(struct drm_plane *plane)
1185 {
1186         struct intel_plane *intel_plane = to_intel_plane(plane);
1187
1188         if (!plane->crtc || !plane->fb)
1189                 return;
1190
1191         intel_update_plane(plane, plane->crtc, plane->fb,
1192                            intel_plane->crtc_x, intel_plane->crtc_y,
1193                            intel_plane->crtc_w, intel_plane->crtc_h,
1194                            intel_plane->src_x, intel_plane->src_y,
1195                            intel_plane->src_w, intel_plane->src_h);
1196 }
1197
1198 void intel_plane_disable(struct drm_plane *plane)
1199 {
1200         if (!plane->crtc || !plane->fb)
1201                 return;
1202
1203         intel_disable_plane(plane);
1204 }
1205
1206 static const struct drm_plane_funcs intel_plane_funcs = {
1207         .update_plane = intel_update_plane,
1208         .disable_plane = intel_disable_plane,
1209         .destroy = intel_destroy_plane,
1210 };
1211
1212 static uint32_t ilk_plane_formats[] = {
1213         DRM_FORMAT_XRGB8888,
1214         DRM_FORMAT_YUYV,
1215         DRM_FORMAT_YVYU,
1216         DRM_FORMAT_UYVY,
1217         DRM_FORMAT_VYUY,
1218 };
1219
1220 static uint32_t snb_plane_formats[] = {
1221         DRM_FORMAT_XBGR8888,
1222         DRM_FORMAT_XRGB8888,
1223         DRM_FORMAT_YUYV,
1224         DRM_FORMAT_YVYU,
1225         DRM_FORMAT_UYVY,
1226         DRM_FORMAT_VYUY,
1227 };
1228
1229 static uint32_t vlv_plane_formats[] = {
1230         DRM_FORMAT_RGB565,
1231         DRM_FORMAT_ABGR8888,
1232         DRM_FORMAT_ARGB8888,
1233         DRM_FORMAT_XBGR8888,
1234         DRM_FORMAT_XRGB8888,
1235         DRM_FORMAT_XBGR2101010,
1236         DRM_FORMAT_ABGR2101010,
1237         DRM_FORMAT_YUYV,
1238         DRM_FORMAT_YVYU,
1239         DRM_FORMAT_UYVY,
1240         DRM_FORMAT_VYUY,
1241 };
1242
1243 int
1244 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1245 {
1246         struct intel_plane *intel_plane;
1247         unsigned long possible_crtcs;
1248         const uint32_t *plane_formats;
1249         int num_plane_formats;
1250         int ret;
1251
1252         if (INTEL_INFO(dev)->gen < 5)
1253                 return -ENODEV;
1254
1255         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1256         if (!intel_plane)
1257                 return -ENOMEM;
1258
1259         switch (INTEL_INFO(dev)->gen) {
1260         case 5:
1261         case 6:
1262                 intel_plane->can_scale = true;
1263                 intel_plane->max_downscale = 16;
1264                 intel_plane->update_plane = ilk_update_plane;
1265                 intel_plane->disable_plane = ilk_disable_plane;
1266                 intel_plane->update_colorkey = ilk_update_colorkey;
1267                 intel_plane->get_colorkey = ilk_get_colorkey;
1268
1269                 if (IS_GEN6(dev)) {
1270                         plane_formats = snb_plane_formats;
1271                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1272                 } else {
1273                         plane_formats = ilk_plane_formats;
1274                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1275                 }
1276                 break;
1277
1278         case 7:
1279         case 8:
1280                 if (IS_IVYBRIDGE(dev)) {
1281                         intel_plane->can_scale = true;
1282                         intel_plane->max_downscale = 2;
1283                 } else {
1284                         intel_plane->can_scale = false;
1285                         intel_plane->max_downscale = 1;
1286                 }
1287
1288                 if (IS_VALLEYVIEW(dev)) {
1289                         intel_plane->update_plane = vlv_update_plane;
1290                         intel_plane->disable_plane = vlv_disable_plane;
1291                         intel_plane->update_colorkey = vlv_update_colorkey;
1292                         intel_plane->get_colorkey = vlv_get_colorkey;
1293
1294                         plane_formats = vlv_plane_formats;
1295                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1296                 } else {
1297                         intel_plane->update_plane = ivb_update_plane;
1298                         intel_plane->disable_plane = ivb_disable_plane;
1299                         intel_plane->update_colorkey = ivb_update_colorkey;
1300                         intel_plane->get_colorkey = ivb_get_colorkey;
1301
1302                         plane_formats = snb_plane_formats;
1303                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1304                 }
1305                 break;
1306
1307         default:
1308                 kfree(intel_plane);
1309                 return -ENODEV;
1310         }
1311
1312         intel_plane->pipe = pipe;
1313         intel_plane->plane = plane;
1314         possible_crtcs = (1 << pipe);
1315         ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
1316                              &intel_plane_funcs,
1317                              plane_formats, num_plane_formats,
1318                              false);
1319         if (ret)
1320                 kfree(intel_plane);
1321
1322         return ret;
1323 }