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drm/i915: clean up plane commit functions
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sprite.c
1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
32 #include <drm/drmP.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_plane_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include "i915_drv.h"
41
42 static bool
43 format_is_yuv(uint32_t format)
44 {
45 switch (format) {
46 case DRM_FORMAT_YUYV:
47 case DRM_FORMAT_UYVY:
48 case DRM_FORMAT_VYUY:
49 case DRM_FORMAT_YVYU:
50 return true;
51 default:
52 return false;
53 }
54 }
55
56 static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
57 {
58 /* paranoia */
59 if (!mode->crtc_htotal)
60 return 1;
61
62 return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
63 }
64
65 /**
66 * intel_pipe_update_start() - start update of a set of display registers
67 * @crtc: the crtc of which the registers are going to be updated
68 * @start_vbl_count: vblank counter return pointer used for error checking
69 *
70 * Mark the start of an update to pipe registers that should be updated
71 * atomically regarding vblank. If the next vblank will happens within
72 * the next 100 us, this function waits until the vblank passes.
73 *
74 * After a successful call to this function, interrupts will be disabled
75 * until a subsequent call to intel_pipe_update_end(). That is done to
76 * avoid random delays. The value written to @start_vbl_count should be
77 * supplied to intel_pipe_update_end() for error checking.
78 *
79 * Return: true if the call was successful
80 */
81 bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
82 {
83 struct drm_device *dev = crtc->base.dev;
84 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
85 enum pipe pipe = crtc->pipe;
86 long timeout = msecs_to_jiffies_timeout(1);
87 int scanline, min, max, vblank_start;
88 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
89 DEFINE_WAIT(wait);
90
91 vblank_start = mode->crtc_vblank_start;
92 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
93 vblank_start = DIV_ROUND_UP(vblank_start, 2);
94
95 /* FIXME needs to be calibrated sensibly */
96 min = vblank_start - usecs_to_scanlines(mode, 100);
97 max = vblank_start - 1;
98
99 if (min <= 0 || max <= 0)
100 return false;
101
102 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
103 return false;
104
105 local_irq_disable();
106
107 trace_i915_pipe_update_start(crtc, min, max);
108
109 for (;;) {
110 /*
111 * prepare_to_wait() has a memory barrier, which guarantees
112 * other CPUs can see the task state update by the time we
113 * read the scanline.
114 */
115 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
116
117 scanline = intel_get_crtc_scanline(crtc);
118 if (scanline < min || scanline > max)
119 break;
120
121 if (timeout <= 0) {
122 DRM_ERROR("Potential atomic update failure on pipe %c\n",
123 pipe_name(crtc->pipe));
124 break;
125 }
126
127 local_irq_enable();
128
129 timeout = schedule_timeout(timeout);
130
131 local_irq_disable();
132 }
133
134 finish_wait(wq, &wait);
135
136 drm_crtc_vblank_put(&crtc->base);
137
138 *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
139
140 trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count);
141
142 return true;
143 }
144
145 /**
146 * intel_pipe_update_end() - end update of a set of display registers
147 * @crtc: the crtc of which the registers were updated
148 * @start_vbl_count: start vblank counter (used for error checking)
149 *
150 * Mark the end of an update started with intel_pipe_update_start(). This
151 * re-enables interrupts and verifies the update was actually completed
152 * before a vblank using the value of @start_vbl_count.
153 */
154 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
155 {
156 struct drm_device *dev = crtc->base.dev;
157 enum pipe pipe = crtc->pipe;
158 u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
159
160 trace_i915_pipe_update_end(crtc, end_vbl_count);
161
162 local_irq_enable();
163
164 if (start_vbl_count != end_vbl_count)
165 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
166 pipe_name(pipe), start_vbl_count, end_vbl_count);
167 }
168
169 static void
170 skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
171 struct drm_framebuffer *fb,
172 int crtc_x, int crtc_y,
173 unsigned int crtc_w, unsigned int crtc_h,
174 uint32_t x, uint32_t y,
175 uint32_t src_w, uint32_t src_h)
176 {
177 struct drm_device *dev = drm_plane->dev;
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
180 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
181 const int pipe = intel_plane->pipe;
182 const int plane = intel_plane->plane + 1;
183 u32 plane_ctl, stride_div, stride;
184 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
185 const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey;
186 unsigned long surf_addr;
187 u32 tile_height, plane_offset, plane_size;
188 unsigned int rotation;
189 int x_offset, y_offset;
190 struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
191 int scaler_id;
192
193 plane_ctl = PLANE_CTL_ENABLE |
194 PLANE_CTL_PIPE_CSC_ENABLE;
195
196 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
197 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
198
199 rotation = drm_plane->state->rotation;
200 plane_ctl |= skl_plane_ctl_rotation(rotation);
201
202 intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
203 pixel_size, true,
204 src_w != crtc_w || src_h != crtc_h);
205
206 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
207 fb->pixel_format);
208
209 scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id;
210
211 /* Sizes are 0 based */
212 src_w--;
213 src_h--;
214 crtc_w--;
215 crtc_h--;
216
217 if (key->flags) {
218 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
219 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
220 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
221 }
222
223 if (key->flags & I915_SET_COLORKEY_DESTINATION)
224 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
225 else if (key->flags & I915_SET_COLORKEY_SOURCE)
226 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
227
228 surf_addr = intel_plane_obj_offset(intel_plane, obj);
229
230 if (intel_rotation_90_or_270(rotation)) {
231 /* stride: Surface height in tiles */
232 tile_height = intel_tile_height(dev, fb->pixel_format,
233 fb->modifier[0]);
234 stride = DIV_ROUND_UP(fb->height, tile_height);
235 plane_size = (src_w << 16) | src_h;
236 x_offset = stride * tile_height - y - (src_h + 1);
237 y_offset = x;
238 } else {
239 stride = fb->pitches[0] / stride_div;
240 plane_size = (src_h << 16) | src_w;
241 x_offset = x;
242 y_offset = y;
243 }
244 plane_offset = y_offset << 16 | x_offset;
245
246 I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
247 I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
248 I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
249
250 /* program plane scaler */
251 if (scaler_id >= 0) {
252 uint32_t ps_ctrl = 0;
253
254 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
255 PS_PLANE_SEL(plane));
256 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
257 crtc_state->scaler_state.scalers[scaler_id].mode;
258 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
259 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
260 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
261 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
262 ((crtc_w + 1) << 16)|(crtc_h + 1));
263
264 I915_WRITE(PLANE_POS(pipe, plane), 0);
265 } else {
266 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
267 }
268
269 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
270 I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
271 POSTING_READ(PLANE_SURF(pipe, plane));
272 }
273
274 static void
275 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force)
276 {
277 struct drm_device *dev = dplane->dev;
278 struct drm_i915_private *dev_priv = dev->dev_private;
279 struct intel_plane *intel_plane = to_intel_plane(dplane);
280 const int pipe = intel_plane->pipe;
281 const int plane = intel_plane->plane + 1;
282
283 I915_WRITE(PLANE_CTL(pipe, plane), 0);
284
285 I915_WRITE(PLANE_SURF(pipe, plane), 0);
286 POSTING_READ(PLANE_SURF(pipe, plane));
287
288 intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
289 }
290
291 static void
292 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
293 {
294 struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
295 int plane = intel_plane->plane;
296
297 /* Seems RGB data bypasses the CSC always */
298 if (!format_is_yuv(format))
299 return;
300
301 /*
302 * BT.601 limited range YCbCr -> full range RGB
303 *
304 * |r| | 6537 4769 0| |cr |
305 * |g| = |-3330 4769 -1605| x |y-64|
306 * |b| | 0 4769 8263| |cb |
307 *
308 * Cb and Cr apparently come in as signed already, so no
309 * need for any offset. For Y we need to remove the offset.
310 */
311 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
312 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
313 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
314
315 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
316 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
317 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
318 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
319 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
320
321 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
322 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
323 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
324
325 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
326 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
327 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
328 }
329
330 static void
331 vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
332 struct drm_framebuffer *fb,
333 int crtc_x, int crtc_y,
334 unsigned int crtc_w, unsigned int crtc_h,
335 uint32_t x, uint32_t y,
336 uint32_t src_w, uint32_t src_h)
337 {
338 struct drm_device *dev = dplane->dev;
339 struct drm_i915_private *dev_priv = dev->dev_private;
340 struct intel_plane *intel_plane = to_intel_plane(dplane);
341 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
342 int pipe = intel_plane->pipe;
343 int plane = intel_plane->plane;
344 u32 sprctl;
345 unsigned long sprsurf_offset, linear_offset;
346 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
347 const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey;
348
349 sprctl = SP_ENABLE;
350
351 switch (fb->pixel_format) {
352 case DRM_FORMAT_YUYV:
353 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
354 break;
355 case DRM_FORMAT_YVYU:
356 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
357 break;
358 case DRM_FORMAT_UYVY:
359 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
360 break;
361 case DRM_FORMAT_VYUY:
362 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
363 break;
364 case DRM_FORMAT_RGB565:
365 sprctl |= SP_FORMAT_BGR565;
366 break;
367 case DRM_FORMAT_XRGB8888:
368 sprctl |= SP_FORMAT_BGRX8888;
369 break;
370 case DRM_FORMAT_ARGB8888:
371 sprctl |= SP_FORMAT_BGRA8888;
372 break;
373 case DRM_FORMAT_XBGR2101010:
374 sprctl |= SP_FORMAT_RGBX1010102;
375 break;
376 case DRM_FORMAT_ABGR2101010:
377 sprctl |= SP_FORMAT_RGBA1010102;
378 break;
379 case DRM_FORMAT_XBGR8888:
380 sprctl |= SP_FORMAT_RGBX8888;
381 break;
382 case DRM_FORMAT_ABGR8888:
383 sprctl |= SP_FORMAT_RGBA8888;
384 break;
385 default:
386 /*
387 * If we get here one of the upper layers failed to filter
388 * out the unsupported plane formats
389 */
390 BUG();
391 break;
392 }
393
394 /*
395 * Enable gamma to match primary/cursor plane behaviour.
396 * FIXME should be user controllable via propertiesa.
397 */
398 sprctl |= SP_GAMMA_ENABLE;
399
400 if (obj->tiling_mode != I915_TILING_NONE)
401 sprctl |= SP_TILED;
402
403 intel_update_sprite_watermarks(dplane, crtc, src_w, src_h,
404 pixel_size, true,
405 src_w != crtc_w || src_h != crtc_h);
406
407 /* Sizes are 0 based */
408 src_w--;
409 src_h--;
410 crtc_w--;
411 crtc_h--;
412
413 linear_offset = y * fb->pitches[0] + x * pixel_size;
414 sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
415 &x, &y,
416 obj->tiling_mode,
417 pixel_size,
418 fb->pitches[0]);
419 linear_offset -= sprsurf_offset;
420
421 if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
422 sprctl |= SP_ROTATE_180;
423
424 x += src_w;
425 y += src_h;
426 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
427 }
428
429 if (key->flags) {
430 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
431 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
432 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
433 }
434
435 if (key->flags & I915_SET_COLORKEY_SOURCE)
436 sprctl |= SP_SOURCE_KEY;
437
438 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
439 chv_update_csc(intel_plane, fb->pixel_format);
440
441 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
442 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
443
444 if (obj->tiling_mode != I915_TILING_NONE)
445 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
446 else
447 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
448
449 I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
450
451 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
452 I915_WRITE(SPCNTR(pipe, plane), sprctl);
453 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
454 sprsurf_offset);
455 POSTING_READ(SPSURF(pipe, plane));
456 }
457
458 static void
459 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force)
460 {
461 struct drm_device *dev = dplane->dev;
462 struct drm_i915_private *dev_priv = dev->dev_private;
463 struct intel_plane *intel_plane = to_intel_plane(dplane);
464 int pipe = intel_plane->pipe;
465 int plane = intel_plane->plane;
466
467 I915_WRITE(SPCNTR(pipe, plane), 0);
468
469 I915_WRITE(SPSURF(pipe, plane), 0);
470 POSTING_READ(SPSURF(pipe, plane));
471
472 intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
473 }
474
475 static void
476 ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
477 struct drm_framebuffer *fb,
478 int crtc_x, int crtc_y,
479 unsigned int crtc_w, unsigned int crtc_h,
480 uint32_t x, uint32_t y,
481 uint32_t src_w, uint32_t src_h)
482 {
483 struct drm_device *dev = plane->dev;
484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct intel_plane *intel_plane = to_intel_plane(plane);
486 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
487 enum pipe pipe = intel_plane->pipe;
488 u32 sprctl, sprscale = 0;
489 unsigned long sprsurf_offset, linear_offset;
490 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
491 const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey;
492
493 sprctl = SPRITE_ENABLE;
494
495 switch (fb->pixel_format) {
496 case DRM_FORMAT_XBGR8888:
497 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
498 break;
499 case DRM_FORMAT_XRGB8888:
500 sprctl |= SPRITE_FORMAT_RGBX888;
501 break;
502 case DRM_FORMAT_YUYV:
503 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
504 break;
505 case DRM_FORMAT_YVYU:
506 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
507 break;
508 case DRM_FORMAT_UYVY:
509 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
510 break;
511 case DRM_FORMAT_VYUY:
512 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
513 break;
514 default:
515 BUG();
516 }
517
518 /*
519 * Enable gamma to match primary/cursor plane behaviour.
520 * FIXME should be user controllable via propertiesa.
521 */
522 sprctl |= SPRITE_GAMMA_ENABLE;
523
524 if (obj->tiling_mode != I915_TILING_NONE)
525 sprctl |= SPRITE_TILED;
526
527 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
528 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
529 else
530 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
531
532 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
533 sprctl |= SPRITE_PIPE_CSC_ENABLE;
534
535 intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
536 true,
537 src_w != crtc_w || src_h != crtc_h);
538
539 /* Sizes are 0 based */
540 src_w--;
541 src_h--;
542 crtc_w--;
543 crtc_h--;
544
545 if (crtc_w != src_w || crtc_h != src_h)
546 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
547
548 linear_offset = y * fb->pitches[0] + x * pixel_size;
549 sprsurf_offset =
550 intel_gen4_compute_page_offset(dev_priv,
551 &x, &y, obj->tiling_mode,
552 pixel_size, fb->pitches[0]);
553 linear_offset -= sprsurf_offset;
554
555 if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
556 sprctl |= SPRITE_ROTATE_180;
557
558 /* HSW and BDW does this automagically in hardware */
559 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
560 x += src_w;
561 y += src_h;
562 linear_offset += src_h * fb->pitches[0] +
563 src_w * pixel_size;
564 }
565 }
566
567 if (key->flags) {
568 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
569 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
570 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
571 }
572
573 if (key->flags & I915_SET_COLORKEY_DESTINATION)
574 sprctl |= SPRITE_DEST_KEY;
575 else if (key->flags & I915_SET_COLORKEY_SOURCE)
576 sprctl |= SPRITE_SOURCE_KEY;
577
578 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
579 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
580
581 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
582 * register */
583 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
584 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
585 else if (obj->tiling_mode != I915_TILING_NONE)
586 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
587 else
588 I915_WRITE(SPRLINOFF(pipe), linear_offset);
589
590 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
591 if (intel_plane->can_scale)
592 I915_WRITE(SPRSCALE(pipe), sprscale);
593 I915_WRITE(SPRCTL(pipe), sprctl);
594 I915_WRITE(SPRSURF(pipe),
595 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
596 POSTING_READ(SPRSURF(pipe));
597 }
598
599 static void
600 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force)
601 {
602 struct drm_device *dev = plane->dev;
603 struct drm_i915_private *dev_priv = dev->dev_private;
604 struct intel_plane *intel_plane = to_intel_plane(plane);
605 int pipe = intel_plane->pipe;
606
607 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
608 /* Can't leave the scaler enabled... */
609 if (intel_plane->can_scale)
610 I915_WRITE(SPRSCALE(pipe), 0);
611
612 I915_WRITE(SPRSURF(pipe), 0);
613 POSTING_READ(SPRSURF(pipe));
614 }
615
616 static void
617 ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
618 struct drm_framebuffer *fb,
619 int crtc_x, int crtc_y,
620 unsigned int crtc_w, unsigned int crtc_h,
621 uint32_t x, uint32_t y,
622 uint32_t src_w, uint32_t src_h)
623 {
624 struct drm_device *dev = plane->dev;
625 struct drm_i915_private *dev_priv = dev->dev_private;
626 struct intel_plane *intel_plane = to_intel_plane(plane);
627 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
628 int pipe = intel_plane->pipe;
629 unsigned long dvssurf_offset, linear_offset;
630 u32 dvscntr, dvsscale;
631 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
632 const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey;
633
634 dvscntr = DVS_ENABLE;
635
636 switch (fb->pixel_format) {
637 case DRM_FORMAT_XBGR8888:
638 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
639 break;
640 case DRM_FORMAT_XRGB8888:
641 dvscntr |= DVS_FORMAT_RGBX888;
642 break;
643 case DRM_FORMAT_YUYV:
644 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
645 break;
646 case DRM_FORMAT_YVYU:
647 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
648 break;
649 case DRM_FORMAT_UYVY:
650 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
651 break;
652 case DRM_FORMAT_VYUY:
653 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
654 break;
655 default:
656 BUG();
657 }
658
659 /*
660 * Enable gamma to match primary/cursor plane behaviour.
661 * FIXME should be user controllable via propertiesa.
662 */
663 dvscntr |= DVS_GAMMA_ENABLE;
664
665 if (obj->tiling_mode != I915_TILING_NONE)
666 dvscntr |= DVS_TILED;
667
668 if (IS_GEN6(dev))
669 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
670
671 intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
672 pixel_size, true,
673 src_w != crtc_w || src_h != crtc_h);
674
675 /* Sizes are 0 based */
676 src_w--;
677 src_h--;
678 crtc_w--;
679 crtc_h--;
680
681 dvsscale = 0;
682 if (crtc_w != src_w || crtc_h != src_h)
683 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
684
685 linear_offset = y * fb->pitches[0] + x * pixel_size;
686 dvssurf_offset =
687 intel_gen4_compute_page_offset(dev_priv,
688 &x, &y, obj->tiling_mode,
689 pixel_size, fb->pitches[0]);
690 linear_offset -= dvssurf_offset;
691
692 if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
693 dvscntr |= DVS_ROTATE_180;
694
695 x += src_w;
696 y += src_h;
697 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
698 }
699
700 if (key->flags) {
701 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
702 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
703 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
704 }
705
706 if (key->flags & I915_SET_COLORKEY_DESTINATION)
707 dvscntr |= DVS_DEST_KEY;
708 else if (key->flags & I915_SET_COLORKEY_SOURCE)
709 dvscntr |= DVS_SOURCE_KEY;
710
711 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
712 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
713
714 if (obj->tiling_mode != I915_TILING_NONE)
715 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
716 else
717 I915_WRITE(DVSLINOFF(pipe), linear_offset);
718
719 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
720 I915_WRITE(DVSSCALE(pipe), dvsscale);
721 I915_WRITE(DVSCNTR(pipe), dvscntr);
722 I915_WRITE(DVSSURF(pipe),
723 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
724 POSTING_READ(DVSSURF(pipe));
725 }
726
727 static void
728 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force)
729 {
730 struct drm_device *dev = plane->dev;
731 struct drm_i915_private *dev_priv = dev->dev_private;
732 struct intel_plane *intel_plane = to_intel_plane(plane);
733 int pipe = intel_plane->pipe;
734
735 I915_WRITE(DVSCNTR(pipe), 0);
736 /* Disable the scaler */
737 I915_WRITE(DVSSCALE(pipe), 0);
738
739 I915_WRITE(DVSSURF(pipe), 0);
740 POSTING_READ(DVSSURF(pipe));
741 }
742
743 static int
744 intel_check_sprite_plane(struct drm_plane *plane,
745 struct intel_plane_state *state)
746 {
747 struct drm_device *dev = plane->dev;
748 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
749 struct intel_crtc_state *crtc_state;
750 struct intel_plane *intel_plane = to_intel_plane(plane);
751 struct drm_framebuffer *fb = state->base.fb;
752 int crtc_x, crtc_y;
753 unsigned int crtc_w, crtc_h;
754 uint32_t src_x, src_y, src_w, src_h;
755 struct drm_rect *src = &state->src;
756 struct drm_rect *dst = &state->dst;
757 const struct drm_rect *clip = &state->clip;
758 int hscale, vscale;
759 int max_scale, min_scale;
760 bool can_scale;
761 int pixel_size;
762
763 intel_crtc = intel_crtc ? intel_crtc : to_intel_crtc(plane->crtc);
764 crtc_state = state->base.state ?
765 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
766
767 if (!fb) {
768 state->visible = false;
769 return 0;
770 }
771
772 /* Don't modify another pipe's plane */
773 if (intel_plane->pipe != intel_crtc->pipe) {
774 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
775 return -EINVAL;
776 }
777
778 /* FIXME check all gen limits */
779 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
780 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
781 return -EINVAL;
782 }
783
784 /* setup can_scale, min_scale, max_scale */
785 if (INTEL_INFO(dev)->gen >= 9) {
786 /* use scaler when colorkey is not required */
787 if (intel_plane->ckey.flags == I915_SET_COLORKEY_NONE) {
788 can_scale = 1;
789 min_scale = 1;
790 max_scale = skl_max_scale(intel_crtc, crtc_state);
791 } else {
792 can_scale = 0;
793 min_scale = DRM_PLANE_HELPER_NO_SCALING;
794 max_scale = DRM_PLANE_HELPER_NO_SCALING;
795 }
796 } else {
797 can_scale = intel_plane->can_scale;
798 max_scale = intel_plane->max_downscale << 16;
799 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
800 }
801
802 /*
803 * FIXME the following code does a bunch of fuzzy adjustments to the
804 * coordinates and sizes. We probably need some way to decide whether
805 * more strict checking should be done instead.
806 */
807
808 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
809 state->base.rotation);
810
811 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
812 BUG_ON(hscale < 0);
813
814 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
815 BUG_ON(vscale < 0);
816
817 state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
818
819 crtc_x = dst->x1;
820 crtc_y = dst->y1;
821 crtc_w = drm_rect_width(dst);
822 crtc_h = drm_rect_height(dst);
823
824 if (state->visible) {
825 /* check again in case clipping clamped the results */
826 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
827 if (hscale < 0) {
828 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
829 drm_rect_debug_print(src, true);
830 drm_rect_debug_print(dst, false);
831
832 return hscale;
833 }
834
835 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
836 if (vscale < 0) {
837 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
838 drm_rect_debug_print(src, true);
839 drm_rect_debug_print(dst, false);
840
841 return vscale;
842 }
843
844 /* Make the source viewport size an exact multiple of the scaling factors. */
845 drm_rect_adjust_size(src,
846 drm_rect_width(dst) * hscale - drm_rect_width(src),
847 drm_rect_height(dst) * vscale - drm_rect_height(src));
848
849 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
850 state->base.rotation);
851
852 /* sanity check to make sure the src viewport wasn't enlarged */
853 WARN_ON(src->x1 < (int) state->base.src_x ||
854 src->y1 < (int) state->base.src_y ||
855 src->x2 > (int) state->base.src_x + state->base.src_w ||
856 src->y2 > (int) state->base.src_y + state->base.src_h);
857
858 /*
859 * Hardware doesn't handle subpixel coordinates.
860 * Adjust to (macro)pixel boundary, but be careful not to
861 * increase the source viewport size, because that could
862 * push the downscaling factor out of bounds.
863 */
864 src_x = src->x1 >> 16;
865 src_w = drm_rect_width(src) >> 16;
866 src_y = src->y1 >> 16;
867 src_h = drm_rect_height(src) >> 16;
868
869 if (format_is_yuv(fb->pixel_format)) {
870 src_x &= ~1;
871 src_w &= ~1;
872
873 /*
874 * Must keep src and dst the
875 * same if we can't scale.
876 */
877 if (!can_scale)
878 crtc_w &= ~1;
879
880 if (crtc_w == 0)
881 state->visible = false;
882 }
883 }
884
885 /* Check size restrictions when scaling */
886 if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
887 unsigned int width_bytes;
888
889 WARN_ON(!can_scale);
890
891 /* FIXME interlacing min height is 6 */
892
893 if (crtc_w < 3 || crtc_h < 3)
894 state->visible = false;
895
896 if (src_w < 3 || src_h < 3)
897 state->visible = false;
898
899 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
900 width_bytes = ((src_x * pixel_size) & 63) +
901 src_w * pixel_size;
902
903 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
904 width_bytes > 4096 || fb->pitches[0] > 4096)) {
905 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
906 return -EINVAL;
907 }
908 }
909
910 if (state->visible) {
911 src->x1 = src_x << 16;
912 src->x2 = (src_x + src_w) << 16;
913 src->y1 = src_y << 16;
914 src->y2 = (src_y + src_h) << 16;
915 }
916
917 dst->x1 = crtc_x;
918 dst->x2 = crtc_x + crtc_w;
919 dst->y1 = crtc_y;
920 dst->y2 = crtc_y + crtc_h;
921
922 return 0;
923 }
924
925 static void
926 intel_commit_sprite_plane(struct drm_plane *plane,
927 struct intel_plane_state *state)
928 {
929 struct drm_crtc *crtc = state->base.crtc;
930 struct intel_crtc *intel_crtc;
931 struct intel_plane *intel_plane = to_intel_plane(plane);
932 struct drm_framebuffer *fb = state->base.fb;
933
934 crtc = crtc ? crtc : plane->crtc;
935 intel_crtc = to_intel_crtc(crtc);
936
937 plane->fb = fb;
938
939 if (!intel_crtc->active)
940 return;
941
942 if (state->visible) {
943 intel_plane->update_plane(plane, crtc, fb,
944 state->dst.x1, state->dst.y1,
945 drm_rect_width(&state->dst),
946 drm_rect_height(&state->dst),
947 state->src.x1 >> 16,
948 state->src.y1 >> 16,
949 drm_rect_width(&state->src) >> 16,
950 drm_rect_height(&state->src) >> 16);
951 } else {
952 intel_plane->disable_plane(plane, crtc, false);
953 }
954 }
955
956 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
957 struct drm_file *file_priv)
958 {
959 struct drm_intel_sprite_colorkey *set = data;
960 struct drm_plane *plane;
961 struct intel_plane *intel_plane;
962 int ret = 0;
963
964 /* Make sure we don't try to enable both src & dest simultaneously */
965 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
966 return -EINVAL;
967
968 if (IS_VALLEYVIEW(dev) &&
969 set->flags & I915_SET_COLORKEY_DESTINATION)
970 return -EINVAL;
971
972 drm_modeset_lock_all(dev);
973
974 plane = drm_plane_find(dev, set->plane_id);
975 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) {
976 ret = -ENOENT;
977 goto out_unlock;
978 }
979
980 intel_plane = to_intel_plane(plane);
981
982 if (INTEL_INFO(dev)->gen >= 9) {
983 /* plane scaling and colorkey are mutually exclusive */
984 if (to_intel_plane_state(plane->state)->scaler_id >= 0) {
985 DRM_ERROR("colorkey not allowed with scaler\n");
986 ret = -EINVAL;
987 goto out_unlock;
988 }
989 }
990
991 intel_plane->ckey = *set;
992
993 /*
994 * The only way this could fail would be due to
995 * the current plane state being unsupportable already,
996 * and we dont't consider that an error for the
997 * colorkey ioctl. So just ignore any error.
998 */
999 intel_plane_restore(plane);
1000
1001 out_unlock:
1002 drm_modeset_unlock_all(dev);
1003 return ret;
1004 }
1005
1006 int intel_plane_restore(struct drm_plane *plane)
1007 {
1008 if (!plane->crtc || !plane->state->fb)
1009 return 0;
1010
1011 return drm_plane_helper_update(plane, plane->crtc, plane->state->fb,
1012 plane->state->crtc_x, plane->state->crtc_y,
1013 plane->state->crtc_w, plane->state->crtc_h,
1014 plane->state->src_x, plane->state->src_y,
1015 plane->state->src_w, plane->state->src_h);
1016 }
1017
1018 static const uint32_t ilk_plane_formats[] = {
1019 DRM_FORMAT_XRGB8888,
1020 DRM_FORMAT_YUYV,
1021 DRM_FORMAT_YVYU,
1022 DRM_FORMAT_UYVY,
1023 DRM_FORMAT_VYUY,
1024 };
1025
1026 static const uint32_t snb_plane_formats[] = {
1027 DRM_FORMAT_XBGR8888,
1028 DRM_FORMAT_XRGB8888,
1029 DRM_FORMAT_YUYV,
1030 DRM_FORMAT_YVYU,
1031 DRM_FORMAT_UYVY,
1032 DRM_FORMAT_VYUY,
1033 };
1034
1035 static const uint32_t vlv_plane_formats[] = {
1036 DRM_FORMAT_RGB565,
1037 DRM_FORMAT_ABGR8888,
1038 DRM_FORMAT_ARGB8888,
1039 DRM_FORMAT_XBGR8888,
1040 DRM_FORMAT_XRGB8888,
1041 DRM_FORMAT_XBGR2101010,
1042 DRM_FORMAT_ABGR2101010,
1043 DRM_FORMAT_YUYV,
1044 DRM_FORMAT_YVYU,
1045 DRM_FORMAT_UYVY,
1046 DRM_FORMAT_VYUY,
1047 };
1048
1049 static uint32_t skl_plane_formats[] = {
1050 DRM_FORMAT_RGB565,
1051 DRM_FORMAT_ABGR8888,
1052 DRM_FORMAT_ARGB8888,
1053 DRM_FORMAT_XBGR8888,
1054 DRM_FORMAT_XRGB8888,
1055 DRM_FORMAT_YUYV,
1056 DRM_FORMAT_YVYU,
1057 DRM_FORMAT_UYVY,
1058 DRM_FORMAT_VYUY,
1059 };
1060
1061 int
1062 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1063 {
1064 struct intel_plane *intel_plane;
1065 struct intel_plane_state *state;
1066 unsigned long possible_crtcs;
1067 const uint32_t *plane_formats;
1068 int num_plane_formats;
1069 int ret;
1070
1071 if (INTEL_INFO(dev)->gen < 5)
1072 return -ENODEV;
1073
1074 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1075 if (!intel_plane)
1076 return -ENOMEM;
1077
1078 state = intel_create_plane_state(&intel_plane->base);
1079 if (!state) {
1080 kfree(intel_plane);
1081 return -ENOMEM;
1082 }
1083 intel_plane->base.state = &state->base;
1084
1085 switch (INTEL_INFO(dev)->gen) {
1086 case 5:
1087 case 6:
1088 intel_plane->can_scale = true;
1089 intel_plane->max_downscale = 16;
1090 intel_plane->update_plane = ilk_update_plane;
1091 intel_plane->disable_plane = ilk_disable_plane;
1092
1093 if (IS_GEN6(dev)) {
1094 plane_formats = snb_plane_formats;
1095 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1096 } else {
1097 plane_formats = ilk_plane_formats;
1098 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1099 }
1100 break;
1101
1102 case 7:
1103 case 8:
1104 if (IS_IVYBRIDGE(dev)) {
1105 intel_plane->can_scale = true;
1106 intel_plane->max_downscale = 2;
1107 } else {
1108 intel_plane->can_scale = false;
1109 intel_plane->max_downscale = 1;
1110 }
1111
1112 if (IS_VALLEYVIEW(dev)) {
1113 intel_plane->update_plane = vlv_update_plane;
1114 intel_plane->disable_plane = vlv_disable_plane;
1115
1116 plane_formats = vlv_plane_formats;
1117 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1118 } else {
1119 intel_plane->update_plane = ivb_update_plane;
1120 intel_plane->disable_plane = ivb_disable_plane;
1121
1122 plane_formats = snb_plane_formats;
1123 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1124 }
1125 break;
1126 case 9:
1127 intel_plane->can_scale = true;
1128 intel_plane->update_plane = skl_update_plane;
1129 intel_plane->disable_plane = skl_disable_plane;
1130 state->scaler_id = -1;
1131
1132 plane_formats = skl_plane_formats;
1133 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1134 break;
1135 default:
1136 kfree(intel_plane);
1137 return -ENODEV;
1138 }
1139
1140 intel_plane->pipe = pipe;
1141 intel_plane->plane = plane;
1142 intel_plane->check_plane = intel_check_sprite_plane;
1143 intel_plane->commit_plane = intel_commit_sprite_plane;
1144 intel_plane->ckey.flags = I915_SET_COLORKEY_NONE;
1145 possible_crtcs = (1 << pipe);
1146 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1147 &intel_plane_funcs,
1148 plane_formats, num_plane_formats,
1149 DRM_PLANE_TYPE_OVERLAY);
1150 if (ret) {
1151 kfree(intel_plane);
1152 goto out;
1153 }
1154
1155 intel_create_rotation_property(dev, intel_plane);
1156
1157 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1158
1159 out:
1160 return ret;
1161 }
Linux kernel - Deliverables
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