2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
41 vlv_update_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
,
42 struct drm_framebuffer
*fb
,
43 struct drm_i915_gem_object
*obj
, int crtc_x
, int crtc_y
,
44 unsigned int crtc_w
, unsigned int crtc_h
,
45 uint32_t x
, uint32_t y
,
46 uint32_t src_w
, uint32_t src_h
)
48 struct drm_device
*dev
= dplane
->dev
;
49 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
50 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
51 int pipe
= intel_plane
->pipe
;
52 int plane
= intel_plane
->plane
;
54 unsigned long sprsurf_offset
, linear_offset
;
55 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
57 sprctl
= I915_READ(SPCNTR(pipe
, plane
));
59 /* Mask out pixel format bits in case we change it */
60 sprctl
&= ~SP_PIXFORMAT_MASK
;
61 sprctl
&= ~SP_YUV_BYTE_ORDER_MASK
;
64 switch (fb
->pixel_format
) {
66 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YUYV
;
69 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YVYU
;
72 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_UYVY
;
75 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_VYUY
;
77 case DRM_FORMAT_RGB565
:
78 sprctl
|= SP_FORMAT_BGR565
;
80 case DRM_FORMAT_XRGB8888
:
81 sprctl
|= SP_FORMAT_BGRX8888
;
83 case DRM_FORMAT_ARGB8888
:
84 sprctl
|= SP_FORMAT_BGRA8888
;
86 case DRM_FORMAT_XBGR2101010
:
87 sprctl
|= SP_FORMAT_RGBX1010102
;
89 case DRM_FORMAT_ABGR2101010
:
90 sprctl
|= SP_FORMAT_RGBA1010102
;
92 case DRM_FORMAT_XBGR8888
:
93 sprctl
|= SP_FORMAT_RGBX8888
;
95 case DRM_FORMAT_ABGR8888
:
96 sprctl
|= SP_FORMAT_RGBA8888
;
100 * If we get here one of the upper layers failed to filter
101 * out the unsupported plane formats
107 if (obj
->tiling_mode
!= I915_TILING_NONE
)
112 intel_update_sprite_watermarks(dplane
, crtc
, src_w
, pixel_size
, true,
113 src_w
!= crtc_w
|| src_h
!= crtc_h
);
115 /* Sizes are 0 based */
121 I915_WRITE(SPSTRIDE(pipe
, plane
), fb
->pitches
[0]);
122 I915_WRITE(SPPOS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
124 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
125 sprsurf_offset
= intel_gen4_compute_page_offset(&x
, &y
,
129 linear_offset
-= sprsurf_offset
;
131 if (obj
->tiling_mode
!= I915_TILING_NONE
)
132 I915_WRITE(SPTILEOFF(pipe
, plane
), (y
<< 16) | x
);
134 I915_WRITE(SPLINOFF(pipe
, plane
), linear_offset
);
136 I915_WRITE(SPSIZE(pipe
, plane
), (crtc_h
<< 16) | crtc_w
);
137 I915_WRITE(SPCNTR(pipe
, plane
), sprctl
);
138 I915_MODIFY_DISPBASE(SPSURF(pipe
, plane
), i915_gem_obj_ggtt_offset(obj
) +
140 POSTING_READ(SPSURF(pipe
, plane
));
144 vlv_disable_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
)
146 struct drm_device
*dev
= dplane
->dev
;
147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
148 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
149 int pipe
= intel_plane
->pipe
;
150 int plane
= intel_plane
->plane
;
152 I915_WRITE(SPCNTR(pipe
, plane
), I915_READ(SPCNTR(pipe
, plane
)) &
154 /* Activate double buffered register update */
155 I915_MODIFY_DISPBASE(SPSURF(pipe
, plane
), 0);
156 POSTING_READ(SPSURF(pipe
, plane
));
158 intel_update_sprite_watermarks(dplane
, crtc
, 0, 0, false, false);
162 vlv_update_colorkey(struct drm_plane
*dplane
,
163 struct drm_intel_sprite_colorkey
*key
)
165 struct drm_device
*dev
= dplane
->dev
;
166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
167 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
168 int pipe
= intel_plane
->pipe
;
169 int plane
= intel_plane
->plane
;
172 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
175 I915_WRITE(SPKEYMINVAL(pipe
, plane
), key
->min_value
);
176 I915_WRITE(SPKEYMAXVAL(pipe
, plane
), key
->max_value
);
177 I915_WRITE(SPKEYMSK(pipe
, plane
), key
->channel_mask
);
179 sprctl
= I915_READ(SPCNTR(pipe
, plane
));
180 sprctl
&= ~SP_SOURCE_KEY
;
181 if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
182 sprctl
|= SP_SOURCE_KEY
;
183 I915_WRITE(SPCNTR(pipe
, plane
), sprctl
);
185 POSTING_READ(SPKEYMSK(pipe
, plane
));
191 vlv_get_colorkey(struct drm_plane
*dplane
,
192 struct drm_intel_sprite_colorkey
*key
)
194 struct drm_device
*dev
= dplane
->dev
;
195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
196 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
197 int pipe
= intel_plane
->pipe
;
198 int plane
= intel_plane
->plane
;
201 key
->min_value
= I915_READ(SPKEYMINVAL(pipe
, plane
));
202 key
->max_value
= I915_READ(SPKEYMAXVAL(pipe
, plane
));
203 key
->channel_mask
= I915_READ(SPKEYMSK(pipe
, plane
));
205 sprctl
= I915_READ(SPCNTR(pipe
, plane
));
206 if (sprctl
& SP_SOURCE_KEY
)
207 key
->flags
= I915_SET_COLORKEY_SOURCE
;
209 key
->flags
= I915_SET_COLORKEY_NONE
;
213 ivb_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
214 struct drm_framebuffer
*fb
,
215 struct drm_i915_gem_object
*obj
, int crtc_x
, int crtc_y
,
216 unsigned int crtc_w
, unsigned int crtc_h
,
217 uint32_t x
, uint32_t y
,
218 uint32_t src_w
, uint32_t src_h
)
220 struct drm_device
*dev
= plane
->dev
;
221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
222 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
223 int pipe
= intel_plane
->pipe
;
224 u32 sprctl
, sprscale
= 0;
225 unsigned long sprsurf_offset
, linear_offset
;
226 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
227 bool scaling_was_enabled
= dev_priv
->sprite_scaling_enabled
;
229 sprctl
= I915_READ(SPRCTL(pipe
));
231 /* Mask out pixel format bits in case we change it */
232 sprctl
&= ~SPRITE_PIXFORMAT_MASK
;
233 sprctl
&= ~SPRITE_RGB_ORDER_RGBX
;
234 sprctl
&= ~SPRITE_YUV_BYTE_ORDER_MASK
;
235 sprctl
&= ~SPRITE_TILED
;
237 switch (fb
->pixel_format
) {
238 case DRM_FORMAT_XBGR8888
:
239 sprctl
|= SPRITE_FORMAT_RGBX888
| SPRITE_RGB_ORDER_RGBX
;
241 case DRM_FORMAT_XRGB8888
:
242 sprctl
|= SPRITE_FORMAT_RGBX888
;
244 case DRM_FORMAT_YUYV
:
245 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YUYV
;
247 case DRM_FORMAT_YVYU
:
248 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YVYU
;
250 case DRM_FORMAT_UYVY
:
251 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_UYVY
;
253 case DRM_FORMAT_VYUY
:
254 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_VYUY
;
260 if (obj
->tiling_mode
!= I915_TILING_NONE
)
261 sprctl
|= SPRITE_TILED
;
264 sprctl
|= SPRITE_TRICKLE_FEED_DISABLE
;
265 sprctl
|= SPRITE_ENABLE
;
268 sprctl
|= SPRITE_PIPE_CSC_ENABLE
;
270 intel_update_sprite_watermarks(plane
, crtc
, src_w
, pixel_size
, true,
271 src_w
!= crtc_w
|| src_h
!= crtc_h
);
273 /* Sizes are 0 based */
280 * IVB workaround: must disable low power watermarks for at least
281 * one frame before enabling scaling. LP watermarks can be re-enabled
282 * when scaling is disabled.
284 if (crtc_w
!= src_w
|| crtc_h
!= src_h
) {
285 dev_priv
->sprite_scaling_enabled
|= 1 << pipe
;
287 if (!scaling_was_enabled
) {
288 intel_update_watermarks(dev
);
289 intel_wait_for_vblank(dev
, pipe
);
291 sprscale
= SPRITE_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
293 dev_priv
->sprite_scaling_enabled
&= ~(1 << pipe
);
295 I915_WRITE(SPRSTRIDE(pipe
), fb
->pitches
[0]);
296 I915_WRITE(SPRPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
298 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
300 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
301 pixel_size
, fb
->pitches
[0]);
302 linear_offset
-= sprsurf_offset
;
304 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
307 I915_WRITE(SPROFFSET(pipe
), (y
<< 16) | x
);
308 else if (obj
->tiling_mode
!= I915_TILING_NONE
)
309 I915_WRITE(SPRTILEOFF(pipe
), (y
<< 16) | x
);
311 I915_WRITE(SPRLINOFF(pipe
), linear_offset
);
313 I915_WRITE(SPRSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
314 if (intel_plane
->can_scale
)
315 I915_WRITE(SPRSCALE(pipe
), sprscale
);
316 I915_WRITE(SPRCTL(pipe
), sprctl
);
317 I915_MODIFY_DISPBASE(SPRSURF(pipe
),
318 i915_gem_obj_ggtt_offset(obj
) + sprsurf_offset
);
319 POSTING_READ(SPRSURF(pipe
));
321 /* potentially re-enable LP watermarks */
322 if (scaling_was_enabled
&& !dev_priv
->sprite_scaling_enabled
)
323 intel_update_watermarks(dev
);
327 ivb_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
)
329 struct drm_device
*dev
= plane
->dev
;
330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
331 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
332 int pipe
= intel_plane
->pipe
;
333 bool scaling_was_enabled
= dev_priv
->sprite_scaling_enabled
;
335 I915_WRITE(SPRCTL(pipe
), I915_READ(SPRCTL(pipe
)) & ~SPRITE_ENABLE
);
336 /* Can't leave the scaler enabled... */
337 if (intel_plane
->can_scale
)
338 I915_WRITE(SPRSCALE(pipe
), 0);
339 /* Activate double buffered register update */
340 I915_MODIFY_DISPBASE(SPRSURF(pipe
), 0);
341 POSTING_READ(SPRSURF(pipe
));
343 dev_priv
->sprite_scaling_enabled
&= ~(1 << pipe
);
345 intel_update_sprite_watermarks(plane
, crtc
, 0, 0, false, false);
347 /* potentially re-enable LP watermarks */
348 if (scaling_was_enabled
&& !dev_priv
->sprite_scaling_enabled
)
349 intel_update_watermarks(dev
);
353 ivb_update_colorkey(struct drm_plane
*plane
,
354 struct drm_intel_sprite_colorkey
*key
)
356 struct drm_device
*dev
= plane
->dev
;
357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
358 struct intel_plane
*intel_plane
;
362 intel_plane
= to_intel_plane(plane
);
364 I915_WRITE(SPRKEYVAL(intel_plane
->pipe
), key
->min_value
);
365 I915_WRITE(SPRKEYMAX(intel_plane
->pipe
), key
->max_value
);
366 I915_WRITE(SPRKEYMSK(intel_plane
->pipe
), key
->channel_mask
);
368 sprctl
= I915_READ(SPRCTL(intel_plane
->pipe
));
369 sprctl
&= ~(SPRITE_SOURCE_KEY
| SPRITE_DEST_KEY
);
370 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
371 sprctl
|= SPRITE_DEST_KEY
;
372 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
373 sprctl
|= SPRITE_SOURCE_KEY
;
374 I915_WRITE(SPRCTL(intel_plane
->pipe
), sprctl
);
376 POSTING_READ(SPRKEYMSK(intel_plane
->pipe
));
382 ivb_get_colorkey(struct drm_plane
*plane
, struct drm_intel_sprite_colorkey
*key
)
384 struct drm_device
*dev
= plane
->dev
;
385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
386 struct intel_plane
*intel_plane
;
389 intel_plane
= to_intel_plane(plane
);
391 key
->min_value
= I915_READ(SPRKEYVAL(intel_plane
->pipe
));
392 key
->max_value
= I915_READ(SPRKEYMAX(intel_plane
->pipe
));
393 key
->channel_mask
= I915_READ(SPRKEYMSK(intel_plane
->pipe
));
396 sprctl
= I915_READ(SPRCTL(intel_plane
->pipe
));
398 if (sprctl
& SPRITE_DEST_KEY
)
399 key
->flags
= I915_SET_COLORKEY_DESTINATION
;
400 else if (sprctl
& SPRITE_SOURCE_KEY
)
401 key
->flags
= I915_SET_COLORKEY_SOURCE
;
403 key
->flags
= I915_SET_COLORKEY_NONE
;
407 ilk_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
408 struct drm_framebuffer
*fb
,
409 struct drm_i915_gem_object
*obj
, int crtc_x
, int crtc_y
,
410 unsigned int crtc_w
, unsigned int crtc_h
,
411 uint32_t x
, uint32_t y
,
412 uint32_t src_w
, uint32_t src_h
)
414 struct drm_device
*dev
= plane
->dev
;
415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
416 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
417 int pipe
= intel_plane
->pipe
;
418 unsigned long dvssurf_offset
, linear_offset
;
419 u32 dvscntr
, dvsscale
;
420 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
422 dvscntr
= I915_READ(DVSCNTR(pipe
));
424 /* Mask out pixel format bits in case we change it */
425 dvscntr
&= ~DVS_PIXFORMAT_MASK
;
426 dvscntr
&= ~DVS_RGB_ORDER_XBGR
;
427 dvscntr
&= ~DVS_YUV_BYTE_ORDER_MASK
;
428 dvscntr
&= ~DVS_TILED
;
430 switch (fb
->pixel_format
) {
431 case DRM_FORMAT_XBGR8888
:
432 dvscntr
|= DVS_FORMAT_RGBX888
| DVS_RGB_ORDER_XBGR
;
434 case DRM_FORMAT_XRGB8888
:
435 dvscntr
|= DVS_FORMAT_RGBX888
;
437 case DRM_FORMAT_YUYV
:
438 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YUYV
;
440 case DRM_FORMAT_YVYU
:
441 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YVYU
;
443 case DRM_FORMAT_UYVY
:
444 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_UYVY
;
446 case DRM_FORMAT_VYUY
:
447 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_VYUY
;
453 if (obj
->tiling_mode
!= I915_TILING_NONE
)
454 dvscntr
|= DVS_TILED
;
457 dvscntr
|= DVS_TRICKLE_FEED_DISABLE
; /* must disable */
458 dvscntr
|= DVS_ENABLE
;
460 intel_update_sprite_watermarks(plane
, crtc
, src_w
, pixel_size
, true,
461 src_w
!= crtc_w
|| src_h
!= crtc_h
);
463 /* Sizes are 0 based */
470 if (IS_GEN5(dev
) || crtc_w
!= src_w
|| crtc_h
!= src_h
)
471 dvsscale
= DVS_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
473 I915_WRITE(DVSSTRIDE(pipe
), fb
->pitches
[0]);
474 I915_WRITE(DVSPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
476 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
478 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
479 pixel_size
, fb
->pitches
[0]);
480 linear_offset
-= dvssurf_offset
;
482 if (obj
->tiling_mode
!= I915_TILING_NONE
)
483 I915_WRITE(DVSTILEOFF(pipe
), (y
<< 16) | x
);
485 I915_WRITE(DVSLINOFF(pipe
), linear_offset
);
487 I915_WRITE(DVSSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
488 I915_WRITE(DVSSCALE(pipe
), dvsscale
);
489 I915_WRITE(DVSCNTR(pipe
), dvscntr
);
490 I915_MODIFY_DISPBASE(DVSSURF(pipe
),
491 i915_gem_obj_ggtt_offset(obj
) + dvssurf_offset
);
492 POSTING_READ(DVSSURF(pipe
));
496 ilk_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
)
498 struct drm_device
*dev
= plane
->dev
;
499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
500 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
501 int pipe
= intel_plane
->pipe
;
503 I915_WRITE(DVSCNTR(pipe
), I915_READ(DVSCNTR(pipe
)) & ~DVS_ENABLE
);
504 /* Disable the scaler */
505 I915_WRITE(DVSSCALE(pipe
), 0);
506 /* Flush double buffered register updates */
507 I915_MODIFY_DISPBASE(DVSSURF(pipe
), 0);
508 POSTING_READ(DVSSURF(pipe
));
510 intel_update_sprite_watermarks(plane
, crtc
, 0, 0, false, false);
514 intel_enable_primary(struct drm_crtc
*crtc
)
516 struct drm_device
*dev
= crtc
->dev
;
517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
518 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
519 int reg
= DSPCNTR(intel_crtc
->plane
);
521 if (!intel_crtc
->primary_disabled
)
524 intel_crtc
->primary_disabled
= false;
525 intel_update_fbc(dev
);
527 I915_WRITE(reg
, I915_READ(reg
) | DISPLAY_PLANE_ENABLE
);
531 intel_disable_primary(struct drm_crtc
*crtc
)
533 struct drm_device
*dev
= crtc
->dev
;
534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
535 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
536 int reg
= DSPCNTR(intel_crtc
->plane
);
538 if (intel_crtc
->primary_disabled
)
541 I915_WRITE(reg
, I915_READ(reg
) & ~DISPLAY_PLANE_ENABLE
);
543 intel_crtc
->primary_disabled
= true;
544 intel_update_fbc(dev
);
548 ilk_update_colorkey(struct drm_plane
*plane
,
549 struct drm_intel_sprite_colorkey
*key
)
551 struct drm_device
*dev
= plane
->dev
;
552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
553 struct intel_plane
*intel_plane
;
557 intel_plane
= to_intel_plane(plane
);
559 I915_WRITE(DVSKEYVAL(intel_plane
->pipe
), key
->min_value
);
560 I915_WRITE(DVSKEYMAX(intel_plane
->pipe
), key
->max_value
);
561 I915_WRITE(DVSKEYMSK(intel_plane
->pipe
), key
->channel_mask
);
563 dvscntr
= I915_READ(DVSCNTR(intel_plane
->pipe
));
564 dvscntr
&= ~(DVS_SOURCE_KEY
| DVS_DEST_KEY
);
565 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
566 dvscntr
|= DVS_DEST_KEY
;
567 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
568 dvscntr
|= DVS_SOURCE_KEY
;
569 I915_WRITE(DVSCNTR(intel_plane
->pipe
), dvscntr
);
571 POSTING_READ(DVSKEYMSK(intel_plane
->pipe
));
577 ilk_get_colorkey(struct drm_plane
*plane
, struct drm_intel_sprite_colorkey
*key
)
579 struct drm_device
*dev
= plane
->dev
;
580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
581 struct intel_plane
*intel_plane
;
584 intel_plane
= to_intel_plane(plane
);
586 key
->min_value
= I915_READ(DVSKEYVAL(intel_plane
->pipe
));
587 key
->max_value
= I915_READ(DVSKEYMAX(intel_plane
->pipe
));
588 key
->channel_mask
= I915_READ(DVSKEYMSK(intel_plane
->pipe
));
591 dvscntr
= I915_READ(DVSCNTR(intel_plane
->pipe
));
593 if (dvscntr
& DVS_DEST_KEY
)
594 key
->flags
= I915_SET_COLORKEY_DESTINATION
;
595 else if (dvscntr
& DVS_SOURCE_KEY
)
596 key
->flags
= I915_SET_COLORKEY_SOURCE
;
598 key
->flags
= I915_SET_COLORKEY_NONE
;
602 format_is_yuv(uint32_t format
)
605 case DRM_FORMAT_YUYV
:
606 case DRM_FORMAT_UYVY
:
607 case DRM_FORMAT_VYUY
:
608 case DRM_FORMAT_YVYU
:
616 intel_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
617 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
618 unsigned int crtc_w
, unsigned int crtc_h
,
619 uint32_t src_x
, uint32_t src_y
,
620 uint32_t src_w
, uint32_t src_h
)
622 struct drm_device
*dev
= plane
->dev
;
623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
624 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
625 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
626 struct intel_framebuffer
*intel_fb
;
627 struct drm_i915_gem_object
*obj
, *old_obj
;
628 int pipe
= intel_plane
->pipe
;
629 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
632 bool disable_primary
= false;
635 int max_scale
, min_scale
;
636 int pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
637 struct drm_rect src
= {
638 /* sample coordinates in 16.16 fixed point */
644 struct drm_rect dst
= {
647 .x2
= crtc_x
+ crtc_w
,
649 .y2
= crtc_y
+ crtc_h
,
651 const struct drm_rect clip
= {
652 .x2
= crtc
->mode
.hdisplay
,
653 .y2
= crtc
->mode
.vdisplay
,
656 intel_fb
= to_intel_framebuffer(fb
);
659 old_obj
= intel_plane
->obj
;
661 intel_plane
->crtc_x
= crtc_x
;
662 intel_plane
->crtc_y
= crtc_y
;
663 intel_plane
->crtc_w
= crtc_w
;
664 intel_plane
->crtc_h
= crtc_h
;
665 intel_plane
->src_x
= src_x
;
666 intel_plane
->src_y
= src_y
;
667 intel_plane
->src_w
= src_w
;
668 intel_plane
->src_h
= src_h
;
670 /* Pipe must be running... */
671 if (!(I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_ENABLE
)) {
672 DRM_DEBUG_KMS("Pipe disabled\n");
676 /* Don't modify another pipe's plane */
677 if (intel_plane
->pipe
!= intel_crtc
->pipe
) {
678 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
682 /* FIXME check all gen limits */
683 if (fb
->width
< 3 || fb
->height
< 3 || fb
->pitches
[0] > 16384) {
684 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
688 /* Sprite planes can be linear or x-tiled surfaces */
689 switch (obj
->tiling_mode
) {
690 case I915_TILING_NONE
:
694 DRM_DEBUG_KMS("Unsupported tiling mode\n");
699 * FIXME the following code does a bunch of fuzzy adjustments to the
700 * coordinates and sizes. We probably need some way to decide whether
701 * more strict checking should be done instead.
703 max_scale
= intel_plane
->max_downscale
<< 16;
704 min_scale
= intel_plane
->can_scale
? 1 : (1 << 16);
706 hscale
= drm_rect_calc_hscale_relaxed(&src
, &dst
, min_scale
, max_scale
);
709 vscale
= drm_rect_calc_vscale_relaxed(&src
, &dst
, min_scale
, max_scale
);
712 visible
= drm_rect_clip_scaled(&src
, &dst
, &clip
, hscale
, vscale
);
716 crtc_w
= drm_rect_width(&dst
);
717 crtc_h
= drm_rect_height(&dst
);
720 /* check again in case clipping clamped the results */
721 hscale
= drm_rect_calc_hscale(&src
, &dst
, min_scale
, max_scale
);
723 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
724 drm_rect_debug_print(&src
, true);
725 drm_rect_debug_print(&dst
, false);
730 vscale
= drm_rect_calc_vscale(&src
, &dst
, min_scale
, max_scale
);
732 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
733 drm_rect_debug_print(&src
, true);
734 drm_rect_debug_print(&dst
, false);
739 /* Make the source viewport size an exact multiple of the scaling factors. */
740 drm_rect_adjust_size(&src
,
741 drm_rect_width(&dst
) * hscale
- drm_rect_width(&src
),
742 drm_rect_height(&dst
) * vscale
- drm_rect_height(&src
));
744 /* sanity check to make sure the src viewport wasn't enlarged */
745 WARN_ON(src
.x1
< (int) src_x
||
746 src
.y1
< (int) src_y
||
747 src
.x2
> (int) (src_x
+ src_w
) ||
748 src
.y2
> (int) (src_y
+ src_h
));
751 * Hardware doesn't handle subpixel coordinates.
752 * Adjust to (macro)pixel boundary, but be careful not to
753 * increase the source viewport size, because that could
754 * push the downscaling factor out of bounds.
756 src_x
= src
.x1
>> 16;
757 src_w
= drm_rect_width(&src
) >> 16;
758 src_y
= src
.y1
>> 16;
759 src_h
= drm_rect_height(&src
) >> 16;
761 if (format_is_yuv(fb
->pixel_format
)) {
766 * Must keep src and dst the
767 * same if we can't scale.
769 if (!intel_plane
->can_scale
)
777 /* Check size restrictions when scaling */
778 if (visible
&& (src_w
!= crtc_w
|| src_h
!= crtc_h
)) {
779 unsigned int width_bytes
;
781 WARN_ON(!intel_plane
->can_scale
);
783 /* FIXME interlacing min height is 6 */
785 if (crtc_w
< 3 || crtc_h
< 3)
788 if (src_w
< 3 || src_h
< 3)
791 width_bytes
= ((src_x
* pixel_size
) & 63) + src_w
* pixel_size
;
793 if (src_w
> 2048 || src_h
> 2048 ||
794 width_bytes
> 4096 || fb
->pitches
[0] > 4096) {
795 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
801 dst
.x2
= crtc_x
+ crtc_w
;
803 dst
.y2
= crtc_y
+ crtc_h
;
806 * If the sprite is completely covering the primary plane,
807 * we can disable the primary and save power.
809 disable_primary
= drm_rect_equals(&dst
, &clip
);
810 WARN_ON(disable_primary
&& !visible
);
812 mutex_lock(&dev
->struct_mutex
);
814 /* Note that this will apply the VT-d workaround for scanouts,
815 * which is more restrictive than required for sprites. (The
816 * primary plane requires 256KiB alignment with 64 PTE padding,
817 * the sprite planes only require 128KiB alignment and 32 PTE padding.
819 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
823 intel_plane
->obj
= obj
;
826 * Be sure to re-enable the primary before the sprite is no longer
829 if (!disable_primary
)
830 intel_enable_primary(crtc
);
833 intel_plane
->update_plane(plane
, crtc
, fb
, obj
,
834 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
835 src_x
, src_y
, src_w
, src_h
);
837 intel_plane
->disable_plane(plane
, crtc
);
840 intel_disable_primary(crtc
);
842 /* Unpin old obj after new one is active to avoid ugliness */
845 * It's fairly common to simply update the position of
846 * an existing object. In that case, we don't need to
847 * wait for vblank to avoid ugliness, we only need to
848 * do the pin & ref bookkeeping.
850 if (old_obj
!= obj
) {
851 mutex_unlock(&dev
->struct_mutex
);
852 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
853 mutex_lock(&dev
->struct_mutex
);
855 intel_unpin_fb_obj(old_obj
);
859 mutex_unlock(&dev
->struct_mutex
);
864 intel_disable_plane(struct drm_plane
*plane
)
866 struct drm_device
*dev
= plane
->dev
;
867 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
873 if (WARN_ON(!plane
->crtc
))
876 intel_enable_primary(plane
->crtc
);
877 intel_plane
->disable_plane(plane
, plane
->crtc
);
879 if (!intel_plane
->obj
)
882 intel_wait_for_vblank(dev
, intel_plane
->pipe
);
884 mutex_lock(&dev
->struct_mutex
);
885 intel_unpin_fb_obj(intel_plane
->obj
);
886 intel_plane
->obj
= NULL
;
887 mutex_unlock(&dev
->struct_mutex
);
893 static void intel_destroy_plane(struct drm_plane
*plane
)
895 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
896 intel_disable_plane(plane
);
897 drm_plane_cleanup(plane
);
901 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
902 struct drm_file
*file_priv
)
904 struct drm_intel_sprite_colorkey
*set
= data
;
905 struct drm_mode_object
*obj
;
906 struct drm_plane
*plane
;
907 struct intel_plane
*intel_plane
;
910 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
913 /* Make sure we don't try to enable both src & dest simultaneously */
914 if ((set
->flags
& (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
)) == (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
))
917 drm_modeset_lock_all(dev
);
919 obj
= drm_mode_object_find(dev
, set
->plane_id
, DRM_MODE_OBJECT_PLANE
);
925 plane
= obj_to_plane(obj
);
926 intel_plane
= to_intel_plane(plane
);
927 ret
= intel_plane
->update_colorkey(plane
, set
);
930 drm_modeset_unlock_all(dev
);
934 int intel_sprite_get_colorkey(struct drm_device
*dev
, void *data
,
935 struct drm_file
*file_priv
)
937 struct drm_intel_sprite_colorkey
*get
= data
;
938 struct drm_mode_object
*obj
;
939 struct drm_plane
*plane
;
940 struct intel_plane
*intel_plane
;
943 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
946 drm_modeset_lock_all(dev
);
948 obj
= drm_mode_object_find(dev
, get
->plane_id
, DRM_MODE_OBJECT_PLANE
);
954 plane
= obj_to_plane(obj
);
955 intel_plane
= to_intel_plane(plane
);
956 intel_plane
->get_colorkey(plane
, get
);
959 drm_modeset_unlock_all(dev
);
963 void intel_plane_restore(struct drm_plane
*plane
)
965 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
967 if (!plane
->crtc
|| !plane
->fb
)
970 intel_update_plane(plane
, plane
->crtc
, plane
->fb
,
971 intel_plane
->crtc_x
, intel_plane
->crtc_y
,
972 intel_plane
->crtc_w
, intel_plane
->crtc_h
,
973 intel_plane
->src_x
, intel_plane
->src_y
,
974 intel_plane
->src_w
, intel_plane
->src_h
);
977 void intel_plane_disable(struct drm_plane
*plane
)
979 if (!plane
->crtc
|| !plane
->fb
)
982 intel_disable_plane(plane
);
985 static const struct drm_plane_funcs intel_plane_funcs
= {
986 .update_plane
= intel_update_plane
,
987 .disable_plane
= intel_disable_plane
,
988 .destroy
= intel_destroy_plane
,
991 static uint32_t ilk_plane_formats
[] = {
999 static uint32_t snb_plane_formats
[] = {
1000 DRM_FORMAT_XBGR8888
,
1001 DRM_FORMAT_XRGB8888
,
1008 static uint32_t vlv_plane_formats
[] = {
1010 DRM_FORMAT_ABGR8888
,
1011 DRM_FORMAT_ARGB8888
,
1012 DRM_FORMAT_XBGR8888
,
1013 DRM_FORMAT_XRGB8888
,
1014 DRM_FORMAT_XBGR2101010
,
1015 DRM_FORMAT_ABGR2101010
,
1023 intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
)
1025 struct intel_plane
*intel_plane
;
1026 unsigned long possible_crtcs
;
1027 const uint32_t *plane_formats
;
1028 int num_plane_formats
;
1031 if (INTEL_INFO(dev
)->gen
< 5)
1034 intel_plane
= kzalloc(sizeof(struct intel_plane
), GFP_KERNEL
);
1038 switch (INTEL_INFO(dev
)->gen
) {
1041 intel_plane
->can_scale
= true;
1042 intel_plane
->max_downscale
= 16;
1043 intel_plane
->update_plane
= ilk_update_plane
;
1044 intel_plane
->disable_plane
= ilk_disable_plane
;
1045 intel_plane
->update_colorkey
= ilk_update_colorkey
;
1046 intel_plane
->get_colorkey
= ilk_get_colorkey
;
1049 plane_formats
= snb_plane_formats
;
1050 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1052 plane_formats
= ilk_plane_formats
;
1053 num_plane_formats
= ARRAY_SIZE(ilk_plane_formats
);
1058 if (IS_IVYBRIDGE(dev
)) {
1059 intel_plane
->can_scale
= true;
1060 intel_plane
->max_downscale
= 2;
1062 intel_plane
->can_scale
= false;
1063 intel_plane
->max_downscale
= 1;
1066 if (IS_VALLEYVIEW(dev
)) {
1067 intel_plane
->update_plane
= vlv_update_plane
;
1068 intel_plane
->disable_plane
= vlv_disable_plane
;
1069 intel_plane
->update_colorkey
= vlv_update_colorkey
;
1070 intel_plane
->get_colorkey
= vlv_get_colorkey
;
1072 plane_formats
= vlv_plane_formats
;
1073 num_plane_formats
= ARRAY_SIZE(vlv_plane_formats
);
1075 intel_plane
->update_plane
= ivb_update_plane
;
1076 intel_plane
->disable_plane
= ivb_disable_plane
;
1077 intel_plane
->update_colorkey
= ivb_update_colorkey
;
1078 intel_plane
->get_colorkey
= ivb_get_colorkey
;
1080 plane_formats
= snb_plane_formats
;
1081 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1090 intel_plane
->pipe
= pipe
;
1091 intel_plane
->plane
= plane
;
1092 possible_crtcs
= (1 << pipe
);
1093 ret
= drm_plane_init(dev
, &intel_plane
->base
, possible_crtcs
,
1095 plane_formats
, num_plane_formats
,