2 * Copyright © 2006-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
30 * Integrated TV-out support for the 915GM and 945GM.
37 #include "intel_drv.h"
42 TV_MARGIN_LEFT
, TV_MARGIN_TOP
,
43 TV_MARGIN_RIGHT
, TV_MARGIN_BOTTOM
46 /** Private structure for the integrated TV support */
48 struct intel_encoder base
;
51 const char *tv_format
;
63 u32 save_TV_SC_CTL_1
, save_TV_SC_CTL_2
, save_TV_SC_CTL_3
;
71 u32 save_TV_CLR_KNOBS
;
72 u32 save_TV_CLR_LEVEL
;
75 u32 save_TV_FILTER_CTL_1
;
76 u32 save_TV_FILTER_CTL_2
;
77 u32 save_TV_FILTER_CTL_3
;
79 u32 save_TV_H_LUMA
[60];
80 u32 save_TV_H_CHROMA
[60];
81 u32 save_TV_V_LUMA
[43];
82 u32 save_TV_V_CHROMA
[43];
89 int blank
, black
, burst
;
92 struct color_conversion
{
98 static const u32 filter_table
[] = {
99 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
100 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
101 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
102 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
103 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
104 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
105 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
106 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
107 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
108 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
109 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
110 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
111 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
112 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
113 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
114 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
115 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
116 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
117 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
118 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
119 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
120 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
121 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
122 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
123 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
124 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
125 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
126 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
127 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
128 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
129 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
130 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
131 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
132 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
133 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
134 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
135 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
136 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
137 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
138 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
139 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
140 0x2D002CC0, 0x30003640, 0x2D0036C0,
141 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
142 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
143 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
144 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
145 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
146 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
147 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
148 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
149 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
150 0x28003100, 0x28002F00, 0x00003100,
154 * Color conversion values have 3 separate fixed point formats:
156 * 10 bit fields (ay, au)
157 * 1.9 fixed point (b.bbbbbbbbb)
158 * 11 bit fields (ry, by, ru, gu, gv)
159 * exp.mantissa (ee.mmmmmmmmm)
160 * ee = 00 = 10^-1 (0.mmmmmmmmm)
161 * ee = 01 = 10^-2 (0.0mmmmmmmmm)
162 * ee = 10 = 10^-3 (0.00mmmmmmmmm)
163 * ee = 11 = 10^-4 (0.000mmmmmmmmm)
164 * 12 bit fields (gy, rv, bu)
165 * exp.mantissa (eee.mmmmmmmmm)
166 * eee = 000 = 10^-1 (0.mmmmmmmmm)
167 * eee = 001 = 10^-2 (0.0mmmmmmmmm)
168 * eee = 010 = 10^-3 (0.00mmmmmmmmm)
169 * eee = 011 = 10^-4 (0.000mmmmmmmmm)
170 * eee = 100 = reserved
171 * eee = 101 = reserved
172 * eee = 110 = reserved
173 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
175 * Saturation and contrast are 8 bits, with their own representation:
176 * 8 bit field (saturation, contrast)
177 * exp.mantissa (ee.mmmmmm)
178 * ee = 00 = 10^-1 (0.mmmmmm)
179 * ee = 01 = 10^0 (m.mmmmm)
180 * ee = 10 = 10^1 (mm.mmmm)
181 * ee = 11 = 10^2 (mmm.mmm)
183 * Simple conversion function:
186 * float_to_csc_11(float f)
199 * for (exp = 0; exp < 3 && f < 0.5; exp++)
201 * mant = (f * (1 << 9) + 0.5);
202 * if (mant >= (1 << 9))
203 * mant = (1 << 9) - 1;
205 * ret = (exp << 9) | mant;
211 * Behold, magic numbers! If we plant them they might grow a big
212 * s-video cable to the sky... or something.
214 * Pre-converted to appropriate hex value.
218 * PAL & NTSC values for composite & s-video connections
220 static const struct color_conversion ntsc_m_csc_composite
= {
221 .ry
= 0x0332, .gy
= 0x012d, .by
= 0x07d3, .ay
= 0x0104,
222 .ru
= 0x0733, .gu
= 0x052d, .bu
= 0x05c7, .au
= 0x0200,
223 .rv
= 0x0340, .gv
= 0x030c, .bv
= 0x06d0, .av
= 0x0200,
226 static const struct video_levels ntsc_m_levels_composite
= {
227 .blank
= 225, .black
= 267, .burst
= 113,
230 static const struct color_conversion ntsc_m_csc_svideo
= {
231 .ry
= 0x0332, .gy
= 0x012d, .by
= 0x07d3, .ay
= 0x0133,
232 .ru
= 0x076a, .gu
= 0x0564, .bu
= 0x030d, .au
= 0x0200,
233 .rv
= 0x037a, .gv
= 0x033d, .bv
= 0x06f6, .av
= 0x0200,
236 static const struct video_levels ntsc_m_levels_svideo
= {
237 .blank
= 266, .black
= 316, .burst
= 133,
240 static const struct color_conversion ntsc_j_csc_composite
= {
241 .ry
= 0x0332, .gy
= 0x012d, .by
= 0x07d3, .ay
= 0x0119,
242 .ru
= 0x074c, .gu
= 0x0546, .bu
= 0x05ec, .au
= 0x0200,
243 .rv
= 0x035a, .gv
= 0x0322, .bv
= 0x06e1, .av
= 0x0200,
246 static const struct video_levels ntsc_j_levels_composite
= {
247 .blank
= 225, .black
= 225, .burst
= 113,
250 static const struct color_conversion ntsc_j_csc_svideo
= {
251 .ry
= 0x0332, .gy
= 0x012d, .by
= 0x07d3, .ay
= 0x014c,
252 .ru
= 0x0788, .gu
= 0x0581, .bu
= 0x0322, .au
= 0x0200,
253 .rv
= 0x0399, .gv
= 0x0356, .bv
= 0x070a, .av
= 0x0200,
256 static const struct video_levels ntsc_j_levels_svideo
= {
257 .blank
= 266, .black
= 266, .burst
= 133,
260 static const struct color_conversion pal_csc_composite
= {
261 .ry
= 0x0332, .gy
= 0x012d, .by
= 0x07d3, .ay
= 0x0113,
262 .ru
= 0x0745, .gu
= 0x053f, .bu
= 0x05e1, .au
= 0x0200,
263 .rv
= 0x0353, .gv
= 0x031c, .bv
= 0x06dc, .av
= 0x0200,
266 static const struct video_levels pal_levels_composite
= {
267 .blank
= 237, .black
= 237, .burst
= 118,
270 static const struct color_conversion pal_csc_svideo
= {
271 .ry
= 0x0332, .gy
= 0x012d, .by
= 0x07d3, .ay
= 0x0145,
272 .ru
= 0x0780, .gu
= 0x0579, .bu
= 0x031c, .au
= 0x0200,
273 .rv
= 0x0390, .gv
= 0x034f, .bv
= 0x0705, .av
= 0x0200,
276 static const struct video_levels pal_levels_svideo
= {
277 .blank
= 280, .black
= 280, .burst
= 139,
280 static const struct color_conversion pal_m_csc_composite
= {
281 .ry
= 0x0332, .gy
= 0x012d, .by
= 0x07d3, .ay
= 0x0104,
282 .ru
= 0x0733, .gu
= 0x052d, .bu
= 0x05c7, .au
= 0x0200,
283 .rv
= 0x0340, .gv
= 0x030c, .bv
= 0x06d0, .av
= 0x0200,
286 static const struct video_levels pal_m_levels_composite
= {
287 .blank
= 225, .black
= 267, .burst
= 113,
290 static const struct color_conversion pal_m_csc_svideo
= {
291 .ry
= 0x0332, .gy
= 0x012d, .by
= 0x07d3, .ay
= 0x0133,
292 .ru
= 0x076a, .gu
= 0x0564, .bu
= 0x030d, .au
= 0x0200,
293 .rv
= 0x037a, .gv
= 0x033d, .bv
= 0x06f6, .av
= 0x0200,
296 static const struct video_levels pal_m_levels_svideo
= {
297 .blank
= 266, .black
= 316, .burst
= 133,
300 static const struct color_conversion pal_n_csc_composite
= {
301 .ry
= 0x0332, .gy
= 0x012d, .by
= 0x07d3, .ay
= 0x0104,
302 .ru
= 0x0733, .gu
= 0x052d, .bu
= 0x05c7, .au
= 0x0200,
303 .rv
= 0x0340, .gv
= 0x030c, .bv
= 0x06d0, .av
= 0x0200,
306 static const struct video_levels pal_n_levels_composite
= {
307 .blank
= 225, .black
= 267, .burst
= 118,
310 static const struct color_conversion pal_n_csc_svideo
= {
311 .ry
= 0x0332, .gy
= 0x012d, .by
= 0x07d3, .ay
= 0x0133,
312 .ru
= 0x076a, .gu
= 0x0564, .bu
= 0x030d, .au
= 0x0200,
313 .rv
= 0x037a, .gv
= 0x033d, .bv
= 0x06f6, .av
= 0x0200,
316 static const struct video_levels pal_n_levels_svideo
= {
317 .blank
= 266, .black
= 316, .burst
= 139,
321 * Component connections
323 static const struct color_conversion sdtv_csc_yprpb
= {
324 .ry
= 0x0332, .gy
= 0x012d, .by
= 0x07d3, .ay
= 0x0145,
325 .ru
= 0x0559, .gu
= 0x0353, .bu
= 0x0100, .au
= 0x0200,
326 .rv
= 0x0100, .gv
= 0x03ad, .bv
= 0x074d, .av
= 0x0200,
329 static const struct color_conversion sdtv_csc_rgb
= {
330 .ry
= 0x0000, .gy
= 0x0f00, .by
= 0x0000, .ay
= 0x0166,
331 .ru
= 0x0000, .gu
= 0x0000, .bu
= 0x0f00, .au
= 0x0166,
332 .rv
= 0x0f00, .gv
= 0x0000, .bv
= 0x0000, .av
= 0x0166,
335 static const struct color_conversion hdtv_csc_yprpb
= {
336 .ry
= 0x05b3, .gy
= 0x016e, .by
= 0x0728, .ay
= 0x0145,
337 .ru
= 0x07d5, .gu
= 0x038b, .bu
= 0x0100, .au
= 0x0200,
338 .rv
= 0x0100, .gv
= 0x03d1, .bv
= 0x06bc, .av
= 0x0200,
341 static const struct color_conversion hdtv_csc_rgb
= {
342 .ry
= 0x0000, .gy
= 0x0f00, .by
= 0x0000, .ay
= 0x0166,
343 .ru
= 0x0000, .gu
= 0x0000, .bu
= 0x0f00, .au
= 0x0166,
344 .rv
= 0x0f00, .gv
= 0x0000, .bv
= 0x0000, .av
= 0x0166,
347 static const struct video_levels component_levels
= {
348 .blank
= 279, .black
= 279, .burst
= 0,
355 int refresh
; /* in millihertz (for precision) */
357 int hsync_end
, hblank_start
, hblank_end
, htotal
;
358 bool progressive
, trilevel_sync
, component_only
;
359 int vsync_start_f1
, vsync_start_f2
, vsync_len
;
361 int veq_start_f1
, veq_start_f2
, veq_len
;
362 int vi_end_f1
, vi_end_f2
, nbr_end
;
364 int hburst_start
, hburst_len
;
365 int vburst_start_f1
, vburst_end_f1
;
366 int vburst_start_f2
, vburst_end_f2
;
367 int vburst_start_f3
, vburst_end_f3
;
368 int vburst_start_f4
, vburst_end_f4
;
370 * subcarrier programming
372 int dda2_size
, dda3_size
, dda1_inc
, dda2_inc
, dda3_inc
;
378 const struct video_levels
*composite_levels
, *svideo_levels
;
379 const struct color_conversion
*composite_color
, *svideo_color
;
380 const u32
*filter_table
;
388 * I think this works as follows:
390 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
392 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
395 * dda1_ideal = subcarrier/pixel * 4096
396 * dda1_inc = floor (dda1_ideal)
397 * dda2 = dda1_ideal - dda1_inc
399 * then pick a ratio for dda2 that gives the closest approximation. If
400 * you can't get close enough, you can play with dda3 as well. This
401 * seems likely to happen when dda2 is small as the jumps would be larger
405 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
407 * The constants below were all computed using a 107.520MHz clock
411 * Register programming values for TV modes.
413 * These values account for -1s required.
416 static const struct tv_mode tv_modes
[] = {
421 .oversample
= TV_OVERSAMPLE_8X
,
423 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
425 .hsync_end
= 64, .hblank_end
= 124,
426 .hblank_start
= 836, .htotal
= 857,
428 .progressive
= false, .trilevel_sync
= false,
430 .vsync_start_f1
= 6, .vsync_start_f2
= 7,
433 .veq_ena
= true, .veq_start_f1
= 0,
434 .veq_start_f2
= 1, .veq_len
= 18,
436 .vi_end_f1
= 20, .vi_end_f2
= 21,
440 .hburst_start
= 72, .hburst_len
= 34,
441 .vburst_start_f1
= 9, .vburst_end_f1
= 240,
442 .vburst_start_f2
= 10, .vburst_end_f2
= 240,
443 .vburst_start_f3
= 9, .vburst_end_f3
= 240,
444 .vburst_start_f4
= 10, .vburst_end_f4
= 240,
446 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
448 .dda2_inc
= 20800, .dda2_size
= 27456,
449 .dda3_inc
= 0, .dda3_size
= 0,
450 .sc_reset
= TV_SC_RESET_EVERY_4
,
453 .composite_levels
= &ntsc_m_levels_composite
,
454 .composite_color
= &ntsc_m_csc_composite
,
455 .svideo_levels
= &ntsc_m_levels_svideo
,
456 .svideo_color
= &ntsc_m_csc_svideo
,
458 .filter_table
= filter_table
,
464 .oversample
= TV_OVERSAMPLE_8X
,
466 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
467 .hsync_end
= 64, .hblank_end
= 124,
468 .hblank_start
= 836, .htotal
= 857,
470 .progressive
= false, .trilevel_sync
= false,
472 .vsync_start_f1
= 6, .vsync_start_f2
= 7,
475 .veq_ena
= true, .veq_start_f1
= 0,
476 .veq_start_f2
= 1, .veq_len
= 18,
478 .vi_end_f1
= 20, .vi_end_f2
= 21,
482 .hburst_start
= 72, .hburst_len
= 34,
483 .vburst_start_f1
= 9, .vburst_end_f1
= 240,
484 .vburst_start_f2
= 10, .vburst_end_f2
= 240,
485 .vburst_start_f3
= 9, .vburst_end_f3
= 240,
486 .vburst_start_f4
= 10, .vburst_end_f4
= 240,
488 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
490 .dda2_inc
= 4093, .dda2_size
= 27456,
491 .dda3_inc
= 310, .dda3_size
= 525,
492 .sc_reset
= TV_SC_RESET_NEVER
,
495 .composite_levels
= &ntsc_m_levels_composite
,
496 .composite_color
= &ntsc_m_csc_composite
,
497 .svideo_levels
= &ntsc_m_levels_svideo
,
498 .svideo_color
= &ntsc_m_csc_svideo
,
500 .filter_table
= filter_table
,
506 .oversample
= TV_OVERSAMPLE_8X
,
509 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
510 .hsync_end
= 64, .hblank_end
= 124,
511 .hblank_start
= 836, .htotal
= 857,
513 .progressive
= false, .trilevel_sync
= false,
515 .vsync_start_f1
= 6, .vsync_start_f2
= 7,
518 .veq_ena
= true, .veq_start_f1
= 0,
519 .veq_start_f2
= 1, .veq_len
= 18,
521 .vi_end_f1
= 20, .vi_end_f2
= 21,
525 .hburst_start
= 72, .hburst_len
= 34,
526 .vburst_start_f1
= 9, .vburst_end_f1
= 240,
527 .vburst_start_f2
= 10, .vburst_end_f2
= 240,
528 .vburst_start_f3
= 9, .vburst_end_f3
= 240,
529 .vburst_start_f4
= 10, .vburst_end_f4
= 240,
531 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
533 .dda2_inc
= 20800, .dda2_size
= 27456,
534 .dda3_inc
= 0, .dda3_size
= 0,
535 .sc_reset
= TV_SC_RESET_EVERY_4
,
538 .composite_levels
= &ntsc_j_levels_composite
,
539 .composite_color
= &ntsc_j_csc_composite
,
540 .svideo_levels
= &ntsc_j_levels_svideo
,
541 .svideo_color
= &ntsc_j_csc_svideo
,
543 .filter_table
= filter_table
,
549 .oversample
= TV_OVERSAMPLE_8X
,
552 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
553 .hsync_end
= 64, .hblank_end
= 124,
554 .hblank_start
= 836, .htotal
= 857,
556 .progressive
= false, .trilevel_sync
= false,
558 .vsync_start_f1
= 6, .vsync_start_f2
= 7,
561 .veq_ena
= true, .veq_start_f1
= 0,
562 .veq_start_f2
= 1, .veq_len
= 18,
564 .vi_end_f1
= 20, .vi_end_f2
= 21,
568 .hburst_start
= 72, .hburst_len
= 34,
569 .vburst_start_f1
= 9, .vburst_end_f1
= 240,
570 .vburst_start_f2
= 10, .vburst_end_f2
= 240,
571 .vburst_start_f3
= 9, .vburst_end_f3
= 240,
572 .vburst_start_f4
= 10, .vburst_end_f4
= 240,
574 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
576 .dda2_inc
= 16704, .dda2_size
= 27456,
577 .dda3_inc
= 0, .dda3_size
= 0,
578 .sc_reset
= TV_SC_RESET_EVERY_8
,
581 .composite_levels
= &pal_m_levels_composite
,
582 .composite_color
= &pal_m_csc_composite
,
583 .svideo_levels
= &pal_m_levels_svideo
,
584 .svideo_color
= &pal_m_csc_svideo
,
586 .filter_table
= filter_table
,
589 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
593 .oversample
= TV_OVERSAMPLE_8X
,
596 .hsync_end
= 64, .hblank_end
= 128,
597 .hblank_start
= 844, .htotal
= 863,
599 .progressive
= false, .trilevel_sync
= false,
602 .vsync_start_f1
= 6, .vsync_start_f2
= 7,
605 .veq_ena
= true, .veq_start_f1
= 0,
606 .veq_start_f2
= 1, .veq_len
= 18,
608 .vi_end_f1
= 24, .vi_end_f2
= 25,
612 .hburst_start
= 73, .hburst_len
= 34,
613 .vburst_start_f1
= 8, .vburst_end_f1
= 285,
614 .vburst_start_f2
= 8, .vburst_end_f2
= 286,
615 .vburst_start_f3
= 9, .vburst_end_f3
= 286,
616 .vburst_start_f4
= 9, .vburst_end_f4
= 285,
619 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
621 .dda2_inc
= 23578, .dda2_size
= 27648,
622 .dda3_inc
= 134, .dda3_size
= 625,
623 .sc_reset
= TV_SC_RESET_EVERY_8
,
626 .composite_levels
= &pal_n_levels_composite
,
627 .composite_color
= &pal_n_csc_composite
,
628 .svideo_levels
= &pal_n_levels_svideo
,
629 .svideo_color
= &pal_n_csc_svideo
,
631 .filter_table
= filter_table
,
634 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
638 .oversample
= TV_OVERSAMPLE_8X
,
641 .hsync_end
= 64, .hblank_end
= 142,
642 .hblank_start
= 844, .htotal
= 863,
644 .progressive
= false, .trilevel_sync
= false,
646 .vsync_start_f1
= 5, .vsync_start_f2
= 6,
649 .veq_ena
= true, .veq_start_f1
= 0,
650 .veq_start_f2
= 1, .veq_len
= 15,
652 .vi_end_f1
= 24, .vi_end_f2
= 25,
656 .hburst_start
= 73, .hburst_len
= 32,
657 .vburst_start_f1
= 8, .vburst_end_f1
= 285,
658 .vburst_start_f2
= 8, .vburst_end_f2
= 286,
659 .vburst_start_f3
= 9, .vburst_end_f3
= 286,
660 .vburst_start_f4
= 9, .vburst_end_f4
= 285,
662 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
664 .dda2_inc
= 4122, .dda2_size
= 27648,
665 .dda3_inc
= 67, .dda3_size
= 625,
666 .sc_reset
= TV_SC_RESET_EVERY_8
,
669 .composite_levels
= &pal_levels_composite
,
670 .composite_color
= &pal_csc_composite
,
671 .svideo_levels
= &pal_levels_svideo
,
672 .svideo_color
= &pal_csc_svideo
,
674 .filter_table
= filter_table
,
677 .name
= "480p@59.94Hz",
680 .oversample
= TV_OVERSAMPLE_4X
,
683 .hsync_end
= 64, .hblank_end
= 122,
684 .hblank_start
= 842, .htotal
= 857,
686 .progressive
= true,.trilevel_sync
= false,
688 .vsync_start_f1
= 12, .vsync_start_f2
= 12,
693 .vi_end_f1
= 44, .vi_end_f2
= 44,
698 .filter_table
= filter_table
,
704 .oversample
= TV_OVERSAMPLE_4X
,
707 .hsync_end
= 64, .hblank_end
= 122,
708 .hblank_start
= 842, .htotal
= 856,
710 .progressive
= true,.trilevel_sync
= false,
712 .vsync_start_f1
= 12, .vsync_start_f2
= 12,
717 .vi_end_f1
= 44, .vi_end_f2
= 44,
722 .filter_table
= filter_table
,
728 .oversample
= TV_OVERSAMPLE_4X
,
731 .hsync_end
= 64, .hblank_end
= 139,
732 .hblank_start
= 859, .htotal
= 863,
734 .progressive
= true, .trilevel_sync
= false,
736 .vsync_start_f1
= 10, .vsync_start_f2
= 10,
741 .vi_end_f1
= 48, .vi_end_f2
= 48,
746 .filter_table
= filter_table
,
752 .oversample
= TV_OVERSAMPLE_2X
,
755 .hsync_end
= 80, .hblank_end
= 300,
756 .hblank_start
= 1580, .htotal
= 1649,
758 .progressive
= true, .trilevel_sync
= true,
760 .vsync_start_f1
= 10, .vsync_start_f2
= 10,
765 .vi_end_f1
= 29, .vi_end_f2
= 29,
770 .filter_table
= filter_table
,
773 .name
= "720p@59.94Hz",
776 .oversample
= TV_OVERSAMPLE_2X
,
779 .hsync_end
= 80, .hblank_end
= 300,
780 .hblank_start
= 1580, .htotal
= 1651,
782 .progressive
= true, .trilevel_sync
= true,
784 .vsync_start_f1
= 10, .vsync_start_f2
= 10,
789 .vi_end_f1
= 29, .vi_end_f2
= 29,
794 .filter_table
= filter_table
,
800 .oversample
= TV_OVERSAMPLE_2X
,
803 .hsync_end
= 80, .hblank_end
= 300,
804 .hblank_start
= 1580, .htotal
= 1979,
806 .progressive
= true, .trilevel_sync
= true,
808 .vsync_start_f1
= 10, .vsync_start_f2
= 10,
813 .vi_end_f1
= 29, .vi_end_f2
= 29,
818 .filter_table
= filter_table
,
822 .name
= "1080i@50Hz",
825 .oversample
= TV_OVERSAMPLE_2X
,
828 .hsync_end
= 88, .hblank_end
= 235,
829 .hblank_start
= 2155, .htotal
= 2639,
831 .progressive
= false, .trilevel_sync
= true,
833 .vsync_start_f1
= 4, .vsync_start_f2
= 5,
836 .veq_ena
= true, .veq_start_f1
= 4,
837 .veq_start_f2
= 4, .veq_len
= 10,
840 .vi_end_f1
= 21, .vi_end_f2
= 22,
845 .filter_table
= filter_table
,
848 .name
= "1080i@60Hz",
851 .oversample
= TV_OVERSAMPLE_2X
,
854 .hsync_end
= 88, .hblank_end
= 235,
855 .hblank_start
= 2155, .htotal
= 2199,
857 .progressive
= false, .trilevel_sync
= true,
859 .vsync_start_f1
= 4, .vsync_start_f2
= 5,
862 .veq_ena
= true, .veq_start_f1
= 4,
863 .veq_start_f2
= 4, .veq_len
= 10,
866 .vi_end_f1
= 21, .vi_end_f2
= 22,
871 .filter_table
= filter_table
,
874 .name
= "1080i@59.94Hz",
877 .oversample
= TV_OVERSAMPLE_2X
,
880 .hsync_end
= 88, .hblank_end
= 235,
881 .hblank_start
= 2155, .htotal
= 2201,
883 .progressive
= false, .trilevel_sync
= true,
885 .vsync_start_f1
= 4, .vsync_start_f2
= 5,
888 .veq_ena
= true, .veq_start_f1
= 4,
889 .veq_start_f2
= 4, .veq_len
= 10,
892 .vi_end_f1
= 21, .vi_end_f2
= 22,
897 .filter_table
= filter_table
,
901 static struct intel_tv
*enc_to_intel_tv(struct drm_encoder
*encoder
)
903 return container_of(encoder
, struct intel_tv
, base
.base
);
906 static struct intel_tv
*intel_attached_tv(struct drm_connector
*connector
)
908 return container_of(intel_attached_encoder(connector
),
914 intel_tv_dpms(struct drm_encoder
*encoder
, int mode
)
916 struct drm_device
*dev
= encoder
->dev
;
917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
920 case DRM_MODE_DPMS_ON
:
921 I915_WRITE(TV_CTL
, I915_READ(TV_CTL
) | TV_ENC_ENABLE
);
923 case DRM_MODE_DPMS_STANDBY
:
924 case DRM_MODE_DPMS_SUSPEND
:
925 case DRM_MODE_DPMS_OFF
:
926 I915_WRITE(TV_CTL
, I915_READ(TV_CTL
) & ~TV_ENC_ENABLE
);
931 static const struct tv_mode
*
932 intel_tv_mode_lookup(const char *tv_format
)
936 for (i
= 0; i
< sizeof(tv_modes
) / sizeof (tv_modes
[0]); i
++) {
937 const struct tv_mode
*tv_mode
= &tv_modes
[i
];
939 if (!strcmp(tv_format
, tv_mode
->name
))
945 static const struct tv_mode
*
946 intel_tv_mode_find(struct intel_tv
*intel_tv
)
948 return intel_tv_mode_lookup(intel_tv
->tv_format
);
951 static enum drm_mode_status
952 intel_tv_mode_valid(struct drm_connector
*connector
,
953 struct drm_display_mode
*mode
)
955 struct intel_tv
*intel_tv
= intel_attached_tv(connector
);
956 const struct tv_mode
*tv_mode
= intel_tv_mode_find(intel_tv
);
958 /* Ensure TV refresh is close to desired refresh */
959 if (tv_mode
&& abs(tv_mode
->refresh
- drm_mode_vrefresh(mode
) * 1000)
963 return MODE_CLOCK_RANGE
;
968 intel_tv_mode_fixup(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
969 struct drm_display_mode
*adjusted_mode
)
971 struct drm_device
*dev
= encoder
->dev
;
972 struct drm_mode_config
*drm_config
= &dev
->mode_config
;
973 struct intel_tv
*intel_tv
= enc_to_intel_tv(encoder
);
974 const struct tv_mode
*tv_mode
= intel_tv_mode_find(intel_tv
);
975 struct drm_encoder
*other_encoder
;
980 /* FIXME: lock encoder list */
981 list_for_each_entry(other_encoder
, &drm_config
->encoder_list
, head
) {
982 if (other_encoder
!= encoder
&&
983 other_encoder
->crtc
== encoder
->crtc
)
987 adjusted_mode
->clock
= tv_mode
->clock
;
992 intel_tv_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
993 struct drm_display_mode
*adjusted_mode
)
995 struct drm_device
*dev
= encoder
->dev
;
996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
997 struct drm_crtc
*crtc
= encoder
->crtc
;
998 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
999 struct intel_tv
*intel_tv
= enc_to_intel_tv(encoder
);
1000 const struct tv_mode
*tv_mode
= intel_tv_mode_find(intel_tv
);
1002 u32 hctl1
, hctl2
, hctl3
;
1003 u32 vctl1
, vctl2
, vctl3
, vctl4
, vctl5
, vctl6
, vctl7
;
1004 u32 scctl1
, scctl2
, scctl3
;
1006 const struct video_levels
*video_levels
;
1007 const struct color_conversion
*color_conversion
;
1011 return; /* can't happen (mode_prepare prevents this) */
1013 tv_ctl
= I915_READ(TV_CTL
);
1014 tv_ctl
&= TV_CTL_SAVE
;
1016 switch (intel_tv
->type
) {
1018 case DRM_MODE_CONNECTOR_Unknown
:
1019 case DRM_MODE_CONNECTOR_Composite
:
1020 tv_ctl
|= TV_ENC_OUTPUT_COMPOSITE
;
1021 video_levels
= tv_mode
->composite_levels
;
1022 color_conversion
= tv_mode
->composite_color
;
1023 burst_ena
= tv_mode
->burst_ena
;
1025 case DRM_MODE_CONNECTOR_Component
:
1026 tv_ctl
|= TV_ENC_OUTPUT_COMPONENT
;
1027 video_levels
= &component_levels
;
1028 if (tv_mode
->burst_ena
)
1029 color_conversion
= &sdtv_csc_yprpb
;
1031 color_conversion
= &hdtv_csc_yprpb
;
1034 case DRM_MODE_CONNECTOR_SVIDEO
:
1035 tv_ctl
|= TV_ENC_OUTPUT_SVIDEO
;
1036 video_levels
= tv_mode
->svideo_levels
;
1037 color_conversion
= tv_mode
->svideo_color
;
1038 burst_ena
= tv_mode
->burst_ena
;
1041 hctl1
= (tv_mode
->hsync_end
<< TV_HSYNC_END_SHIFT
) |
1042 (tv_mode
->htotal
<< TV_HTOTAL_SHIFT
);
1044 hctl2
= (tv_mode
->hburst_start
<< 16) |
1045 (tv_mode
->hburst_len
<< TV_HBURST_LEN_SHIFT
);
1048 hctl2
|= TV_BURST_ENA
;
1050 hctl3
= (tv_mode
->hblank_start
<< TV_HBLANK_START_SHIFT
) |
1051 (tv_mode
->hblank_end
<< TV_HBLANK_END_SHIFT
);
1053 vctl1
= (tv_mode
->nbr_end
<< TV_NBR_END_SHIFT
) |
1054 (tv_mode
->vi_end_f1
<< TV_VI_END_F1_SHIFT
) |
1055 (tv_mode
->vi_end_f2
<< TV_VI_END_F2_SHIFT
);
1057 vctl2
= (tv_mode
->vsync_len
<< TV_VSYNC_LEN_SHIFT
) |
1058 (tv_mode
->vsync_start_f1
<< TV_VSYNC_START_F1_SHIFT
) |
1059 (tv_mode
->vsync_start_f2
<< TV_VSYNC_START_F2_SHIFT
);
1061 vctl3
= (tv_mode
->veq_len
<< TV_VEQ_LEN_SHIFT
) |
1062 (tv_mode
->veq_start_f1
<< TV_VEQ_START_F1_SHIFT
) |
1063 (tv_mode
->veq_start_f2
<< TV_VEQ_START_F2_SHIFT
);
1065 if (tv_mode
->veq_ena
)
1066 vctl3
|= TV_EQUAL_ENA
;
1068 vctl4
= (tv_mode
->vburst_start_f1
<< TV_VBURST_START_F1_SHIFT
) |
1069 (tv_mode
->vburst_end_f1
<< TV_VBURST_END_F1_SHIFT
);
1071 vctl5
= (tv_mode
->vburst_start_f2
<< TV_VBURST_START_F2_SHIFT
) |
1072 (tv_mode
->vburst_end_f2
<< TV_VBURST_END_F2_SHIFT
);
1074 vctl6
= (tv_mode
->vburst_start_f3
<< TV_VBURST_START_F3_SHIFT
) |
1075 (tv_mode
->vburst_end_f3
<< TV_VBURST_END_F3_SHIFT
);
1077 vctl7
= (tv_mode
->vburst_start_f4
<< TV_VBURST_START_F4_SHIFT
) |
1078 (tv_mode
->vburst_end_f4
<< TV_VBURST_END_F4_SHIFT
);
1080 if (intel_crtc
->pipe
== 1)
1081 tv_ctl
|= TV_ENC_PIPEB_SELECT
;
1082 tv_ctl
|= tv_mode
->oversample
;
1084 if (tv_mode
->progressive
)
1085 tv_ctl
|= TV_PROGRESSIVE
;
1086 if (tv_mode
->trilevel_sync
)
1087 tv_ctl
|= TV_TRILEVEL_SYNC
;
1088 if (tv_mode
->pal_burst
)
1089 tv_ctl
|= TV_PAL_BURST
;
1092 if (tv_mode
->dda1_inc
)
1093 scctl1
|= TV_SC_DDA1_EN
;
1094 if (tv_mode
->dda2_inc
)
1095 scctl1
|= TV_SC_DDA2_EN
;
1096 if (tv_mode
->dda3_inc
)
1097 scctl1
|= TV_SC_DDA3_EN
;
1098 scctl1
|= tv_mode
->sc_reset
;
1100 scctl1
|= video_levels
->burst
<< TV_BURST_LEVEL_SHIFT
;
1101 scctl1
|= tv_mode
->dda1_inc
<< TV_SCDDA1_INC_SHIFT
;
1103 scctl2
= tv_mode
->dda2_size
<< TV_SCDDA2_SIZE_SHIFT
|
1104 tv_mode
->dda2_inc
<< TV_SCDDA2_INC_SHIFT
;
1106 scctl3
= tv_mode
->dda3_size
<< TV_SCDDA3_SIZE_SHIFT
|
1107 tv_mode
->dda3_inc
<< TV_SCDDA3_INC_SHIFT
;
1109 /* Enable two fixes for the chips that need them. */
1110 if (dev
->pci_device
< 0x2772)
1111 tv_ctl
|= TV_ENC_C0_FIX
| TV_ENC_SDP_FIX
;
1113 I915_WRITE(TV_H_CTL_1
, hctl1
);
1114 I915_WRITE(TV_H_CTL_2
, hctl2
);
1115 I915_WRITE(TV_H_CTL_3
, hctl3
);
1116 I915_WRITE(TV_V_CTL_1
, vctl1
);
1117 I915_WRITE(TV_V_CTL_2
, vctl2
);
1118 I915_WRITE(TV_V_CTL_3
, vctl3
);
1119 I915_WRITE(TV_V_CTL_4
, vctl4
);
1120 I915_WRITE(TV_V_CTL_5
, vctl5
);
1121 I915_WRITE(TV_V_CTL_6
, vctl6
);
1122 I915_WRITE(TV_V_CTL_7
, vctl7
);
1123 I915_WRITE(TV_SC_CTL_1
, scctl1
);
1124 I915_WRITE(TV_SC_CTL_2
, scctl2
);
1125 I915_WRITE(TV_SC_CTL_3
, scctl3
);
1127 if (color_conversion
) {
1128 I915_WRITE(TV_CSC_Y
, (color_conversion
->ry
<< 16) |
1129 color_conversion
->gy
);
1130 I915_WRITE(TV_CSC_Y2
,(color_conversion
->by
<< 16) |
1131 color_conversion
->ay
);
1132 I915_WRITE(TV_CSC_U
, (color_conversion
->ru
<< 16) |
1133 color_conversion
->gu
);
1134 I915_WRITE(TV_CSC_U2
, (color_conversion
->bu
<< 16) |
1135 color_conversion
->au
);
1136 I915_WRITE(TV_CSC_V
, (color_conversion
->rv
<< 16) |
1137 color_conversion
->gv
);
1138 I915_WRITE(TV_CSC_V2
, (color_conversion
->bv
<< 16) |
1139 color_conversion
->av
);
1142 if (INTEL_INFO(dev
)->gen
>= 4)
1143 I915_WRITE(TV_CLR_KNOBS
, 0x00404000);
1145 I915_WRITE(TV_CLR_KNOBS
, 0x00606000);
1148 I915_WRITE(TV_CLR_LEVEL
,
1149 ((video_levels
->black
<< TV_BLACK_LEVEL_SHIFT
) |
1150 (video_levels
->blank
<< TV_BLANK_LEVEL_SHIFT
)));
1152 int pipeconf_reg
= (intel_crtc
->pipe
== 0) ?
1153 PIPEACONF
: PIPEBCONF
;
1154 int dspcntr_reg
= (intel_crtc
->plane
== 0) ?
1155 DSPACNTR
: DSPBCNTR
;
1156 int pipeconf
= I915_READ(pipeconf_reg
);
1157 int dspcntr
= I915_READ(dspcntr_reg
);
1158 int dspbase_reg
= (intel_crtc
->plane
== 0) ?
1159 DSPAADDR
: DSPBADDR
;
1160 int xpos
= 0x0, ypos
= 0x0;
1161 unsigned int xsize
, ysize
;
1162 /* Pipe must be off here */
1163 I915_WRITE(dspcntr_reg
, dspcntr
& ~DISPLAY_PLANE_ENABLE
);
1164 /* Flush the plane changes */
1165 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1167 /* Wait for vblank for the disable to take effect */
1169 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1171 I915_WRITE(pipeconf_reg
, pipeconf
& ~PIPECONF_ENABLE
);
1172 /* Wait for vblank for the disable to take effect. */
1173 intel_wait_for_pipe_off(dev
, intel_crtc
->pipe
);
1175 /* Filter ctl must be set before TV_WIN_SIZE */
1176 I915_WRITE(TV_FILTER_CTL_1
, TV_AUTO_SCALE
);
1177 xsize
= tv_mode
->hblank_start
- tv_mode
->hblank_end
;
1178 if (tv_mode
->progressive
)
1179 ysize
= tv_mode
->nbr_end
+ 1;
1181 ysize
= 2*tv_mode
->nbr_end
+ 1;
1183 xpos
+= intel_tv
->margin
[TV_MARGIN_LEFT
];
1184 ypos
+= intel_tv
->margin
[TV_MARGIN_TOP
];
1185 xsize
-= (intel_tv
->margin
[TV_MARGIN_LEFT
] +
1186 intel_tv
->margin
[TV_MARGIN_RIGHT
]);
1187 ysize
-= (intel_tv
->margin
[TV_MARGIN_TOP
] +
1188 intel_tv
->margin
[TV_MARGIN_BOTTOM
]);
1189 I915_WRITE(TV_WIN_POS
, (xpos
<<16)|ypos
);
1190 I915_WRITE(TV_WIN_SIZE
, (xsize
<<16)|ysize
);
1192 I915_WRITE(pipeconf_reg
, pipeconf
);
1193 I915_WRITE(dspcntr_reg
, dspcntr
);
1194 /* Flush the plane changes */
1195 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1199 for (i
= 0; i
< 60; i
++)
1200 I915_WRITE(TV_H_LUMA_0
+ (i
<<2), tv_mode
->filter_table
[j
++]);
1201 for (i
= 0; i
< 60; i
++)
1202 I915_WRITE(TV_H_CHROMA_0
+ (i
<<2), tv_mode
->filter_table
[j
++]);
1203 for (i
= 0; i
< 43; i
++)
1204 I915_WRITE(TV_V_LUMA_0
+ (i
<<2), tv_mode
->filter_table
[j
++]);
1205 for (i
= 0; i
< 43; i
++)
1206 I915_WRITE(TV_V_CHROMA_0
+ (i
<<2), tv_mode
->filter_table
[j
++]);
1207 I915_WRITE(TV_DAC
, I915_READ(TV_DAC
) & TV_DAC_SAVE
);
1208 I915_WRITE(TV_CTL
, tv_ctl
);
1211 static const struct drm_display_mode reported_modes
[] = {
1213 .name
= "NTSC 480i",
1216 .hsync_start
= 1368,
1221 .vsync_start
= 1027,
1224 .type
= DRM_MODE_TYPE_DRIVER
,
1229 * Detects TV presence by checking for load.
1231 * Requires that the current pipe's DPLL is active.
1233 * \return true if TV is connected.
1234 * \return false if TV is disconnected.
1237 intel_tv_detect_type (struct intel_tv
*intel_tv
)
1239 struct drm_encoder
*encoder
= &intel_tv
->base
.base
;
1240 struct drm_device
*dev
= encoder
->dev
;
1241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1242 unsigned long irqflags
;
1243 u32 tv_ctl
, save_tv_ctl
;
1244 u32 tv_dac
, save_tv_dac
;
1247 /* Disable TV interrupts around load detect or we'll recurse */
1248 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1249 i915_disable_pipestat(dev_priv
, 0,
1250 PIPE_HOTPLUG_INTERRUPT_ENABLE
|
1251 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE
);
1252 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1254 save_tv_dac
= tv_dac
= I915_READ(TV_DAC
);
1255 save_tv_ctl
= tv_ctl
= I915_READ(TV_CTL
);
1257 /* Poll for TV detection */
1258 tv_ctl
&= ~(TV_ENC_ENABLE
| TV_TEST_MODE_MASK
);
1259 tv_ctl
|= TV_TEST_MODE_MONITOR_DETECT
;
1261 tv_dac
&= ~(TVDAC_SENSE_MASK
| DAC_A_MASK
| DAC_B_MASK
| DAC_C_MASK
);
1262 tv_dac
|= (TVDAC_STATE_CHG_EN
|
1271 I915_WRITE(TV_CTL
, tv_ctl
);
1272 I915_WRITE(TV_DAC
, tv_dac
);
1273 POSTING_READ(TV_DAC
);
1275 intel_wait_for_vblank(intel_tv
->base
.base
.dev
,
1276 to_intel_crtc(intel_tv
->base
.base
.crtc
)->pipe
);
1279 if (wait_for((tv_dac
= I915_READ(TV_DAC
)) & TVDAC_STATE_CHG
, 20) == 0) {
1280 DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl
, tv_dac
);
1287 if ((tv_dac
& TVDAC_SENSE_MASK
) == (TVDAC_B_SENSE
| TVDAC_C_SENSE
)) {
1288 DRM_DEBUG_KMS("Detected Composite TV connection\n");
1289 type
= DRM_MODE_CONNECTOR_Composite
;
1290 } else if ((tv_dac
& (TVDAC_A_SENSE
|TVDAC_B_SENSE
)) == TVDAC_A_SENSE
) {
1291 DRM_DEBUG_KMS("Detected S-Video TV connection\n");
1292 type
= DRM_MODE_CONNECTOR_SVIDEO
;
1293 } else if ((tv_dac
& TVDAC_SENSE_MASK
) == 0) {
1294 DRM_DEBUG_KMS("Detected Component TV connection\n");
1295 type
= DRM_MODE_CONNECTOR_Component
;
1297 DRM_DEBUG_KMS("Unrecognised TV connection\n");
1301 I915_WRITE(TV_DAC
, save_tv_dac
& ~TVDAC_STATE_CHG_EN
);
1302 I915_WRITE(TV_CTL
, save_tv_ctl
);
1304 /* Restore interrupt config */
1305 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1306 i915_enable_pipestat(dev_priv
, 0,
1307 PIPE_HOTPLUG_INTERRUPT_ENABLE
|
1308 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE
);
1309 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1315 * Here we set accurate tv format according to connector type
1316 * i.e Component TV should not be assigned by NTSC or PAL
1318 static void intel_tv_find_better_format(struct drm_connector
*connector
)
1320 struct intel_tv
*intel_tv
= intel_attached_tv(connector
);
1321 const struct tv_mode
*tv_mode
= intel_tv_mode_find(intel_tv
);
1324 if ((intel_tv
->type
== DRM_MODE_CONNECTOR_Component
) ==
1325 tv_mode
->component_only
)
1329 for (i
= 0; i
< sizeof(tv_modes
) / sizeof(*tv_modes
); i
++) {
1330 tv_mode
= tv_modes
+ i
;
1332 if ((intel_tv
->type
== DRM_MODE_CONNECTOR_Component
) ==
1333 tv_mode
->component_only
)
1337 intel_tv
->tv_format
= tv_mode
->name
;
1338 drm_connector_property_set_value(connector
,
1339 connector
->dev
->mode_config
.tv_mode_property
, i
);
1343 * Detect the TV connection.
1345 * Currently this always returns CONNECTOR_STATUS_UNKNOWN, as we need to be sure
1346 * we have a pipe programmed in order to probe the TV.
1348 static enum drm_connector_status
1349 intel_tv_detect(struct drm_connector
*connector
, bool force
)
1351 struct drm_display_mode mode
;
1352 struct intel_tv
*intel_tv
= intel_attached_tv(connector
);
1355 mode
= reported_modes
[0];
1356 drm_mode_set_crtcinfo(&mode
, CRTC_INTERLACE_HALVE_V
);
1358 if (intel_tv
->base
.base
.crtc
&& intel_tv
->base
.base
.crtc
->enabled
) {
1359 type
= intel_tv_detect_type(intel_tv
);
1361 struct drm_crtc
*crtc
;
1364 crtc
= intel_get_load_detect_pipe(&intel_tv
->base
, connector
,
1367 type
= intel_tv_detect_type(intel_tv
);
1368 intel_release_load_detect_pipe(&intel_tv
->base
, connector
,
1371 return connector_status_unknown
;
1373 return connector
->status
;
1376 return connector_status_disconnected
;
1378 intel_tv_find_better_format(connector
);
1379 return connector_status_connected
;
1382 static const struct input_res
{
1385 } input_res_table
[] = {
1386 {"640x480", 640, 480},
1387 {"800x600", 800, 600},
1388 {"1024x768", 1024, 768},
1389 {"1280x1024", 1280, 1024},
1390 {"848x480", 848, 480},
1391 {"1280x720", 1280, 720},
1392 {"1920x1080", 1920, 1080},
1396 * Chose preferred mode according to line number of TV format
1399 intel_tv_chose_preferred_modes(struct drm_connector
*connector
,
1400 struct drm_display_mode
*mode_ptr
)
1402 struct intel_tv
*intel_tv
= intel_attached_tv(connector
);
1403 const struct tv_mode
*tv_mode
= intel_tv_mode_find(intel_tv
);
1405 if (tv_mode
->nbr_end
< 480 && mode_ptr
->vdisplay
== 480)
1406 mode_ptr
->type
|= DRM_MODE_TYPE_PREFERRED
;
1407 else if (tv_mode
->nbr_end
> 480) {
1408 if (tv_mode
->progressive
== true && tv_mode
->nbr_end
< 720) {
1409 if (mode_ptr
->vdisplay
== 720)
1410 mode_ptr
->type
|= DRM_MODE_TYPE_PREFERRED
;
1411 } else if (mode_ptr
->vdisplay
== 1080)
1412 mode_ptr
->type
|= DRM_MODE_TYPE_PREFERRED
;
1417 * Stub get_modes function.
1419 * This should probably return a set of fixed modes, unless we can figure out
1420 * how to probe modes off of TV connections.
1424 intel_tv_get_modes(struct drm_connector
*connector
)
1426 struct drm_display_mode
*mode_ptr
;
1427 struct intel_tv
*intel_tv
= intel_attached_tv(connector
);
1428 const struct tv_mode
*tv_mode
= intel_tv_mode_find(intel_tv
);
1432 for (j
= 0; j
< ARRAY_SIZE(input_res_table
);
1434 const struct input_res
*input
= &input_res_table
[j
];
1435 unsigned int hactive_s
= input
->w
;
1436 unsigned int vactive_s
= input
->h
;
1438 if (tv_mode
->max_srcw
&& input
->w
> tv_mode
->max_srcw
)
1441 if (input
->w
> 1024 && (!tv_mode
->progressive
1442 && !tv_mode
->component_only
))
1445 mode_ptr
= drm_mode_create(connector
->dev
);
1448 strncpy(mode_ptr
->name
, input
->name
, DRM_DISPLAY_MODE_LEN
);
1450 mode_ptr
->hdisplay
= hactive_s
;
1451 mode_ptr
->hsync_start
= hactive_s
+ 1;
1452 mode_ptr
->hsync_end
= hactive_s
+ 64;
1453 if (mode_ptr
->hsync_end
<= mode_ptr
->hsync_start
)
1454 mode_ptr
->hsync_end
= mode_ptr
->hsync_start
+ 1;
1455 mode_ptr
->htotal
= hactive_s
+ 96;
1457 mode_ptr
->vdisplay
= vactive_s
;
1458 mode_ptr
->vsync_start
= vactive_s
+ 1;
1459 mode_ptr
->vsync_end
= vactive_s
+ 32;
1460 if (mode_ptr
->vsync_end
<= mode_ptr
->vsync_start
)
1461 mode_ptr
->vsync_end
= mode_ptr
->vsync_start
+ 1;
1462 mode_ptr
->vtotal
= vactive_s
+ 33;
1464 tmp
= (u64
) tv_mode
->refresh
* mode_ptr
->vtotal
;
1465 tmp
*= mode_ptr
->htotal
;
1466 tmp
= div_u64(tmp
, 1000000);
1467 mode_ptr
->clock
= (int) tmp
;
1469 mode_ptr
->type
= DRM_MODE_TYPE_DRIVER
;
1470 intel_tv_chose_preferred_modes(connector
, mode_ptr
);
1471 drm_mode_probed_add(connector
, mode_ptr
);
1479 intel_tv_destroy (struct drm_connector
*connector
)
1481 drm_sysfs_connector_remove(connector
);
1482 drm_connector_cleanup(connector
);
1488 intel_tv_set_property(struct drm_connector
*connector
, struct drm_property
*property
,
1491 struct drm_device
*dev
= connector
->dev
;
1492 struct intel_tv
*intel_tv
= intel_attached_tv(connector
);
1493 struct drm_crtc
*crtc
= intel_tv
->base
.base
.crtc
;
1495 bool changed
= false;
1497 ret
= drm_connector_property_set_value(connector
, property
, val
);
1501 if (property
== dev
->mode_config
.tv_left_margin_property
&&
1502 intel_tv
->margin
[TV_MARGIN_LEFT
] != val
) {
1503 intel_tv
->margin
[TV_MARGIN_LEFT
] = val
;
1505 } else if (property
== dev
->mode_config
.tv_right_margin_property
&&
1506 intel_tv
->margin
[TV_MARGIN_RIGHT
] != val
) {
1507 intel_tv
->margin
[TV_MARGIN_RIGHT
] = val
;
1509 } else if (property
== dev
->mode_config
.tv_top_margin_property
&&
1510 intel_tv
->margin
[TV_MARGIN_TOP
] != val
) {
1511 intel_tv
->margin
[TV_MARGIN_TOP
] = val
;
1513 } else if (property
== dev
->mode_config
.tv_bottom_margin_property
&&
1514 intel_tv
->margin
[TV_MARGIN_BOTTOM
] != val
) {
1515 intel_tv
->margin
[TV_MARGIN_BOTTOM
] = val
;
1517 } else if (property
== dev
->mode_config
.tv_mode_property
) {
1518 if (val
>= ARRAY_SIZE(tv_modes
)) {
1522 if (!strcmp(intel_tv
->tv_format
, tv_modes
[val
].name
))
1525 intel_tv
->tv_format
= tv_modes
[val
].name
;
1532 if (changed
&& crtc
)
1533 drm_crtc_helper_set_mode(crtc
, &crtc
->mode
, crtc
->x
,
1539 static const struct drm_encoder_helper_funcs intel_tv_helper_funcs
= {
1540 .dpms
= intel_tv_dpms
,
1541 .mode_fixup
= intel_tv_mode_fixup
,
1542 .prepare
= intel_encoder_prepare
,
1543 .mode_set
= intel_tv_mode_set
,
1544 .commit
= intel_encoder_commit
,
1547 static const struct drm_connector_funcs intel_tv_connector_funcs
= {
1548 .dpms
= drm_helper_connector_dpms
,
1549 .detect
= intel_tv_detect
,
1550 .destroy
= intel_tv_destroy
,
1551 .set_property
= intel_tv_set_property
,
1552 .fill_modes
= drm_helper_probe_single_connector_modes
,
1555 static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs
= {
1556 .mode_valid
= intel_tv_mode_valid
,
1557 .get_modes
= intel_tv_get_modes
,
1558 .best_encoder
= intel_best_encoder
,
1561 static const struct drm_encoder_funcs intel_tv_enc_funcs
= {
1562 .destroy
= intel_encoder_destroy
,
1566 * Enumerate the child dev array parsed from VBT to check whether
1567 * the integrated TV is present.
1568 * If it is present, return 1.
1569 * If it is not present, return false.
1570 * If no child dev is parsed from VBT, it assumes that the TV is present.
1572 static int tv_is_present_in_vbt(struct drm_device
*dev
)
1574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1575 struct child_device_config
*p_child
;
1578 if (!dev_priv
->child_dev_num
)
1582 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
1583 p_child
= dev_priv
->child_dev
+ i
;
1585 * If the device type is not TV, continue.
1587 if (p_child
->device_type
!= DEVICE_TYPE_INT_TV
&&
1588 p_child
->device_type
!= DEVICE_TYPE_TV
)
1590 /* Only when the addin_offset is non-zero, it is regarded
1593 if (p_child
->addin_offset
) {
1602 intel_tv_init(struct drm_device
*dev
)
1604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1605 struct drm_connector
*connector
;
1606 struct intel_tv
*intel_tv
;
1607 struct intel_encoder
*intel_encoder
;
1608 struct intel_connector
*intel_connector
;
1609 u32 tv_dac_on
, tv_dac_off
, save_tv_dac
;
1610 char *tv_format_names
[ARRAY_SIZE(tv_modes
)];
1611 int i
, initial_mode
= 0;
1613 if ((I915_READ(TV_CTL
) & TV_FUSE_STATE_MASK
) == TV_FUSE_STATE_DISABLED
)
1616 if (!tv_is_present_in_vbt(dev
)) {
1617 DRM_DEBUG_KMS("Integrated TV is not present.\n");
1620 /* Even if we have an encoder we may not have a connector */
1621 if (!dev_priv
->int_tv_support
)
1625 * Sanity check the TV output by checking to see if the
1626 * DAC register holds a value
1628 save_tv_dac
= I915_READ(TV_DAC
);
1630 I915_WRITE(TV_DAC
, save_tv_dac
| TVDAC_STATE_CHG_EN
);
1631 tv_dac_on
= I915_READ(TV_DAC
);
1633 I915_WRITE(TV_DAC
, save_tv_dac
& ~TVDAC_STATE_CHG_EN
);
1634 tv_dac_off
= I915_READ(TV_DAC
);
1636 I915_WRITE(TV_DAC
, save_tv_dac
);
1639 * If the register does not hold the state change enable
1640 * bit, (either as a 0 or a 1), assume it doesn't really
1643 if ((tv_dac_on
& TVDAC_STATE_CHG_EN
) == 0 ||
1644 (tv_dac_off
& TVDAC_STATE_CHG_EN
) != 0)
1647 intel_tv
= kzalloc(sizeof(struct intel_tv
), GFP_KERNEL
);
1652 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1653 if (!intel_connector
) {
1658 intel_encoder
= &intel_tv
->base
;
1659 connector
= &intel_connector
->base
;
1661 drm_connector_init(dev
, connector
, &intel_tv_connector_funcs
,
1662 DRM_MODE_CONNECTOR_SVIDEO
);
1664 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_tv_enc_funcs
,
1665 DRM_MODE_ENCODER_TVDAC
);
1667 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1668 intel_encoder
->type
= INTEL_OUTPUT_TVOUT
;
1669 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
1670 intel_encoder
->clone_mask
= (1 << INTEL_TV_CLONE_BIT
);
1671 intel_encoder
->base
.possible_crtcs
= ((1 << 0) | (1 << 1));
1672 intel_encoder
->base
.possible_clones
= (1 << INTEL_OUTPUT_TVOUT
);
1673 intel_tv
->type
= DRM_MODE_CONNECTOR_Unknown
;
1675 /* BIOS margin values */
1676 intel_tv
->margin
[TV_MARGIN_LEFT
] = 54;
1677 intel_tv
->margin
[TV_MARGIN_TOP
] = 36;
1678 intel_tv
->margin
[TV_MARGIN_RIGHT
] = 46;
1679 intel_tv
->margin
[TV_MARGIN_BOTTOM
] = 37;
1681 intel_tv
->tv_format
= tv_modes
[initial_mode
].name
;
1683 drm_encoder_helper_add(&intel_encoder
->base
, &intel_tv_helper_funcs
);
1684 drm_connector_helper_add(connector
, &intel_tv_connector_helper_funcs
);
1685 connector
->interlace_allowed
= false;
1686 connector
->doublescan_allowed
= false;
1688 /* Create TV properties then attach current values */
1689 for (i
= 0; i
< ARRAY_SIZE(tv_modes
); i
++)
1690 tv_format_names
[i
] = (char *)tv_modes
[i
].name
;
1691 drm_mode_create_tv_properties(dev
,
1692 ARRAY_SIZE(tv_modes
),
1695 drm_connector_attach_property(connector
, dev
->mode_config
.tv_mode_property
,
1697 drm_connector_attach_property(connector
,
1698 dev
->mode_config
.tv_left_margin_property
,
1699 intel_tv
->margin
[TV_MARGIN_LEFT
]);
1700 drm_connector_attach_property(connector
,
1701 dev
->mode_config
.tv_top_margin_property
,
1702 intel_tv
->margin
[TV_MARGIN_TOP
]);
1703 drm_connector_attach_property(connector
,
1704 dev
->mode_config
.tv_right_margin_property
,
1705 intel_tv
->margin
[TV_MARGIN_RIGHT
]);
1706 drm_connector_attach_property(connector
,
1707 dev
->mode_config
.tv_bottom_margin_property
,
1708 intel_tv
->margin
[TV_MARGIN_BOTTOM
]);
1709 drm_sysfs_connector_add(connector
);