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drm/i915/bdw: enable eDRAM.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_uncore.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "i915_drv.h"
25 #include "intel_drv.h"
26
27 #define FORCEWAKE_ACK_TIMEOUT_MS 2
28
29 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
31
32 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
34
35 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
37
38 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
40
41 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
42
43 static void
44 assert_device_not_suspended(struct drm_i915_private *dev_priv)
45 {
46 WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
47 "Device suspended\n");
48 }
49
50 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
51 {
52 u32 gt_thread_status_mask;
53
54 if (IS_HASWELL(dev_priv->dev))
55 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
56 else
57 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
58
59 /* w/a for a sporadic read returning 0 by waiting for the GT
60 * thread to wake up.
61 */
62 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
63 DRM_ERROR("GT thread status wait timed out\n");
64 }
65
66 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
67 {
68 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
69 /* something from same cacheline, but !FORCEWAKE */
70 __raw_posting_read(dev_priv, ECOBUS);
71 }
72
73 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
74 int fw_engine)
75 {
76 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
77 FORCEWAKE_ACK_TIMEOUT_MS))
78 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
79
80 __raw_i915_write32(dev_priv, FORCEWAKE, 1);
81 /* something from same cacheline, but !FORCEWAKE */
82 __raw_posting_read(dev_priv, ECOBUS);
83
84 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
85 FORCEWAKE_ACK_TIMEOUT_MS))
86 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
87
88 /* WaRsForcewakeWaitTC0:snb */
89 __gen6_gt_wait_for_thread_c0(dev_priv);
90 }
91
92 static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
93 {
94 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
95 /* something from same cacheline, but !FORCEWAKE_MT */
96 __raw_posting_read(dev_priv, ECOBUS);
97 }
98
99 static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
100 int fw_engine)
101 {
102 u32 forcewake_ack;
103
104 if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
105 forcewake_ack = FORCEWAKE_ACK_HSW;
106 else
107 forcewake_ack = FORCEWAKE_MT_ACK;
108
109 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
110 FORCEWAKE_ACK_TIMEOUT_MS))
111 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
112
113 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
114 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
115 /* something from same cacheline, but !FORCEWAKE_MT */
116 __raw_posting_read(dev_priv, ECOBUS);
117
118 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
119 FORCEWAKE_ACK_TIMEOUT_MS))
120 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
121
122 /* WaRsForcewakeWaitTC0:ivb,hsw */
123 if (INTEL_INFO(dev_priv->dev)->gen < 8)
124 __gen6_gt_wait_for_thread_c0(dev_priv);
125 }
126
127 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
128 {
129 u32 gtfifodbg;
130
131 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
132 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
133 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
134 }
135
136 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
137 int fw_engine)
138 {
139 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
140 /* something from same cacheline, but !FORCEWAKE */
141 __raw_posting_read(dev_priv, ECOBUS);
142 gen6_gt_check_fifodbg(dev_priv);
143 }
144
145 static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
146 int fw_engine)
147 {
148 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
149 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
150 /* something from same cacheline, but !FORCEWAKE_MT */
151 __raw_posting_read(dev_priv, ECOBUS);
152
153 if (IS_GEN7(dev_priv->dev))
154 gen6_gt_check_fifodbg(dev_priv);
155 }
156
157 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
158 {
159 int ret = 0;
160
161 /* On VLV, FIFO will be shared by both SW and HW.
162 * So, we need to read the FREE_ENTRIES everytime */
163 if (IS_VALLEYVIEW(dev_priv->dev))
164 dev_priv->uncore.fifo_count =
165 __raw_i915_read32(dev_priv, GTFIFOCTL) &
166 GT_FIFO_FREE_ENTRIES_MASK;
167
168 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
169 int loop = 500;
170 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
171 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
172 udelay(10);
173 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
174 }
175 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
176 ++ret;
177 dev_priv->uncore.fifo_count = fifo;
178 }
179 dev_priv->uncore.fifo_count--;
180
181 return ret;
182 }
183
184 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
185 {
186 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
187 _MASKED_BIT_DISABLE(0xffff));
188 /* something from same cacheline, but !FORCEWAKE_VLV */
189 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
190 }
191
192 static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
193 int fw_engine)
194 {
195 /* Check for Render Engine */
196 if (FORCEWAKE_RENDER & fw_engine) {
197 if (wait_for_atomic((__raw_i915_read32(dev_priv,
198 FORCEWAKE_ACK_VLV) &
199 FORCEWAKE_KERNEL) == 0,
200 FORCEWAKE_ACK_TIMEOUT_MS))
201 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
202
203 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
204 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
205
206 if (wait_for_atomic((__raw_i915_read32(dev_priv,
207 FORCEWAKE_ACK_VLV) &
208 FORCEWAKE_KERNEL),
209 FORCEWAKE_ACK_TIMEOUT_MS))
210 DRM_ERROR("Timed out: waiting for Render to ack.\n");
211 }
212
213 /* Check for Media Engine */
214 if (FORCEWAKE_MEDIA & fw_engine) {
215 if (wait_for_atomic((__raw_i915_read32(dev_priv,
216 FORCEWAKE_ACK_MEDIA_VLV) &
217 FORCEWAKE_KERNEL) == 0,
218 FORCEWAKE_ACK_TIMEOUT_MS))
219 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
220
221 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
222 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
223
224 if (wait_for_atomic((__raw_i915_read32(dev_priv,
225 FORCEWAKE_ACK_MEDIA_VLV) &
226 FORCEWAKE_KERNEL),
227 FORCEWAKE_ACK_TIMEOUT_MS))
228 DRM_ERROR("Timed out: waiting for media to ack.\n");
229 }
230
231 /* WaRsForcewakeWaitTC0:vlv */
232 __gen6_gt_wait_for_thread_c0(dev_priv);
233
234 }
235
236 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
237 int fw_engine)
238 {
239
240 /* Check for Render Engine */
241 if (FORCEWAKE_RENDER & fw_engine)
242 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
243 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
244
245
246 /* Check for Media Engine */
247 if (FORCEWAKE_MEDIA & fw_engine)
248 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
249 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
250
251 /* The below doubles as a POSTING_READ */
252 gen6_gt_check_fifodbg(dev_priv);
253
254 }
255
256 static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
257 {
258 unsigned long irqflags;
259
260 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
261
262 if (fw_engine & FORCEWAKE_RENDER &&
263 dev_priv->uncore.fw_rendercount++ != 0)
264 fw_engine &= ~FORCEWAKE_RENDER;
265 if (fw_engine & FORCEWAKE_MEDIA &&
266 dev_priv->uncore.fw_mediacount++ != 0)
267 fw_engine &= ~FORCEWAKE_MEDIA;
268
269 if (fw_engine)
270 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
271
272 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
273 }
274
275 static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
276 {
277 unsigned long irqflags;
278
279 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
280
281 if (fw_engine & FORCEWAKE_RENDER) {
282 WARN_ON(!dev_priv->uncore.fw_rendercount);
283 if (--dev_priv->uncore.fw_rendercount != 0)
284 fw_engine &= ~FORCEWAKE_RENDER;
285 }
286
287 if (fw_engine & FORCEWAKE_MEDIA) {
288 WARN_ON(!dev_priv->uncore.fw_mediacount);
289 if (--dev_priv->uncore.fw_mediacount != 0)
290 fw_engine &= ~FORCEWAKE_MEDIA;
291 }
292
293 if (fw_engine)
294 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine);
295
296 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
297 }
298
299 static void gen6_force_wake_timer(unsigned long arg)
300 {
301 struct drm_i915_private *dev_priv = (void *)arg;
302 unsigned long irqflags;
303
304 assert_device_not_suspended(dev_priv);
305
306 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
307 WARN_ON(!dev_priv->uncore.forcewake_count);
308
309 if (--dev_priv->uncore.forcewake_count == 0)
310 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
311 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
312
313 intel_runtime_pm_put(dev_priv);
314 }
315
316 static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
317 {
318 struct drm_i915_private *dev_priv = dev->dev_private;
319 unsigned long irqflags;
320
321 del_timer_sync(&dev_priv->uncore.force_wake_timer);
322
323 /* Hold uncore.lock across reset to prevent any register access
324 * with forcewake not set correctly
325 */
326 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
327
328 if (IS_VALLEYVIEW(dev))
329 vlv_force_wake_reset(dev_priv);
330 else if (IS_GEN6(dev) || IS_GEN7(dev))
331 __gen6_gt_force_wake_reset(dev_priv);
332
333 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev))
334 __gen7_gt_force_wake_mt_reset(dev_priv);
335
336 if (restore) { /* If reset with a user forcewake, try to restore */
337 unsigned fw = 0;
338
339 if (IS_VALLEYVIEW(dev)) {
340 if (dev_priv->uncore.fw_rendercount)
341 fw |= FORCEWAKE_RENDER;
342
343 if (dev_priv->uncore.fw_mediacount)
344 fw |= FORCEWAKE_MEDIA;
345 } else {
346 if (dev_priv->uncore.forcewake_count)
347 fw = FORCEWAKE_ALL;
348 }
349
350 if (fw)
351 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
352
353 if (IS_GEN6(dev) || IS_GEN7(dev))
354 dev_priv->uncore.fifo_count =
355 __raw_i915_read32(dev_priv, GTFIFOCTL) &
356 GT_FIFO_FREE_ENTRIES_MASK;
357 } else {
358 dev_priv->uncore.forcewake_count = 0;
359 dev_priv->uncore.fw_rendercount = 0;
360 dev_priv->uncore.fw_mediacount = 0;
361 }
362
363 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
364 }
365
366 void intel_uncore_early_sanitize(struct drm_device *dev)
367 {
368 struct drm_i915_private *dev_priv = dev->dev_private;
369
370 if (HAS_FPGA_DBG_UNCLAIMED(dev))
371 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
372
373 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
374 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
375 /* The docs do not explain exactly how the calculation can be
376 * made. It is somewhat guessable, but for now, it's always
377 * 128MB.
378 * NB: We can't write IDICR yet because we do not have gt funcs
379 * set up */
380 dev_priv->ellc_size = 128;
381 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
382 }
383
384 /* clear out old GT FIFO errors */
385 if (IS_GEN6(dev) || IS_GEN7(dev))
386 __raw_i915_write32(dev_priv, GTFIFODBG,
387 __raw_i915_read32(dev_priv, GTFIFODBG));
388
389 intel_uncore_forcewake_reset(dev, false);
390 }
391
392 void intel_uncore_sanitize(struct drm_device *dev)
393 {
394 struct drm_i915_private *dev_priv = dev->dev_private;
395 u32 reg_val;
396
397 /* BIOS often leaves RC6 enabled, but disable it for hw init */
398 intel_disable_gt_powersave(dev);
399
400 /* Turn off power gate, require especially for the BIOS less system */
401 if (IS_VALLEYVIEW(dev)) {
402
403 mutex_lock(&dev_priv->rps.hw_lock);
404 reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
405
406 if (reg_val & (PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_RENDER) |
407 PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_MEDIA) |
408 PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_DISP2D)))
409 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
410
411 mutex_unlock(&dev_priv->rps.hw_lock);
412
413 }
414 }
415
416 /*
417 * Generally this is called implicitly by the register read function. However,
418 * if some sequence requires the GT to not power down then this function should
419 * be called at the beginning of the sequence followed by a call to
420 * gen6_gt_force_wake_put() at the end of the sequence.
421 */
422 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
423 {
424 unsigned long irqflags;
425
426 if (!dev_priv->uncore.funcs.force_wake_get)
427 return;
428
429 intel_runtime_pm_get(dev_priv);
430
431 /* Redirect to VLV specific routine */
432 if (IS_VALLEYVIEW(dev_priv->dev))
433 return vlv_force_wake_get(dev_priv, fw_engine);
434
435 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
436 if (dev_priv->uncore.forcewake_count++ == 0)
437 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
438 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
439 }
440
441 /*
442 * see gen6_gt_force_wake_get()
443 */
444 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
445 {
446 unsigned long irqflags;
447 bool delayed = false;
448
449 if (!dev_priv->uncore.funcs.force_wake_put)
450 return;
451
452 /* Redirect to VLV specific routine */
453 if (IS_VALLEYVIEW(dev_priv->dev)) {
454 vlv_force_wake_put(dev_priv, fw_engine);
455 goto out;
456 }
457
458
459 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
460 WARN_ON(!dev_priv->uncore.forcewake_count);
461
462 if (--dev_priv->uncore.forcewake_count == 0) {
463 dev_priv->uncore.forcewake_count++;
464 delayed = true;
465 mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
466 jiffies + 1);
467 }
468 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
469
470 out:
471 if (!delayed)
472 intel_runtime_pm_put(dev_priv);
473 }
474
475 void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
476 {
477 if (!dev_priv->uncore.funcs.force_wake_get)
478 return;
479
480 WARN_ON(dev_priv->uncore.forcewake_count > 0);
481 }
482
483 /* We give fast paths for the really cool registers */
484 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
485 ((reg) < 0x40000 && (reg) != FORCEWAKE)
486
487 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
488 (((reg) >= 0x2000 && (reg) < 0x4000) ||\
489 ((reg) >= 0x5000 && (reg) < 0x8000) ||\
490 ((reg) >= 0xB000 && (reg) < 0x12000) ||\
491 ((reg) >= 0x2E000 && (reg) < 0x30000))
492
493 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
494 (((reg) >= 0x12000 && (reg) < 0x14000) ||\
495 ((reg) >= 0x22000 && (reg) < 0x24000) ||\
496 ((reg) >= 0x30000 && (reg) < 0x40000))
497
498 static void
499 ilk_dummy_write(struct drm_i915_private *dev_priv)
500 {
501 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
502 * the chip from rc6 before touching it for real. MI_MODE is masked,
503 * hence harmless to write 0 into. */
504 __raw_i915_write32(dev_priv, MI_MODE, 0);
505 }
506
507 static void
508 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
509 {
510 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
511 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
512 reg);
513 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
514 }
515 }
516
517 static void
518 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
519 {
520 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
521 DRM_ERROR("Unclaimed write to %x\n", reg);
522 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
523 }
524 }
525
526 #define REG_READ_HEADER(x) \
527 unsigned long irqflags; \
528 u##x val = 0; \
529 assert_device_not_suspended(dev_priv); \
530 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
531
532 #define REG_READ_FOOTER \
533 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
534 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
535 return val
536
537 #define __gen4_read(x) \
538 static u##x \
539 gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
540 REG_READ_HEADER(x); \
541 val = __raw_i915_read##x(dev_priv, reg); \
542 REG_READ_FOOTER; \
543 }
544
545 #define __gen5_read(x) \
546 static u##x \
547 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
548 REG_READ_HEADER(x); \
549 ilk_dummy_write(dev_priv); \
550 val = __raw_i915_read##x(dev_priv, reg); \
551 REG_READ_FOOTER; \
552 }
553
554 #define __gen6_read(x) \
555 static u##x \
556 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
557 REG_READ_HEADER(x); \
558 if (dev_priv->uncore.forcewake_count == 0 && \
559 NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
560 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
561 FORCEWAKE_ALL); \
562 val = __raw_i915_read##x(dev_priv, reg); \
563 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
564 FORCEWAKE_ALL); \
565 } else { \
566 val = __raw_i915_read##x(dev_priv, reg); \
567 } \
568 REG_READ_FOOTER; \
569 }
570
571 #define __vlv_read(x) \
572 static u##x \
573 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
574 unsigned fwengine = 0; \
575 REG_READ_HEADER(x); \
576 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
577 if (dev_priv->uncore.fw_rendercount == 0) \
578 fwengine = FORCEWAKE_RENDER; \
579 } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
580 if (dev_priv->uncore.fw_mediacount == 0) \
581 fwengine = FORCEWAKE_MEDIA; \
582 } \
583 if (fwengine) \
584 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
585 val = __raw_i915_read##x(dev_priv, reg); \
586 if (fwengine) \
587 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
588 REG_READ_FOOTER; \
589 }
590
591
592 __vlv_read(8)
593 __vlv_read(16)
594 __vlv_read(32)
595 __vlv_read(64)
596 __gen6_read(8)
597 __gen6_read(16)
598 __gen6_read(32)
599 __gen6_read(64)
600 __gen5_read(8)
601 __gen5_read(16)
602 __gen5_read(32)
603 __gen5_read(64)
604 __gen4_read(8)
605 __gen4_read(16)
606 __gen4_read(32)
607 __gen4_read(64)
608
609 #undef __vlv_read
610 #undef __gen6_read
611 #undef __gen5_read
612 #undef __gen4_read
613 #undef REG_READ_FOOTER
614 #undef REG_READ_HEADER
615
616 #define REG_WRITE_HEADER \
617 unsigned long irqflags; \
618 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
619 assert_device_not_suspended(dev_priv); \
620 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
621
622 #define REG_WRITE_FOOTER \
623 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
624
625 #define __gen4_write(x) \
626 static void \
627 gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
628 REG_WRITE_HEADER; \
629 __raw_i915_write##x(dev_priv, reg, val); \
630 REG_WRITE_FOOTER; \
631 }
632
633 #define __gen5_write(x) \
634 static void \
635 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
636 REG_WRITE_HEADER; \
637 ilk_dummy_write(dev_priv); \
638 __raw_i915_write##x(dev_priv, reg, val); \
639 REG_WRITE_FOOTER; \
640 }
641
642 #define __gen6_write(x) \
643 static void \
644 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
645 u32 __fifo_ret = 0; \
646 REG_WRITE_HEADER; \
647 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
648 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
649 } \
650 __raw_i915_write##x(dev_priv, reg, val); \
651 if (unlikely(__fifo_ret)) { \
652 gen6_gt_check_fifodbg(dev_priv); \
653 } \
654 REG_WRITE_FOOTER; \
655 }
656
657 #define __hsw_write(x) \
658 static void \
659 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
660 u32 __fifo_ret = 0; \
661 REG_WRITE_HEADER; \
662 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
663 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
664 } \
665 hsw_unclaimed_reg_clear(dev_priv, reg); \
666 __raw_i915_write##x(dev_priv, reg, val); \
667 if (unlikely(__fifo_ret)) { \
668 gen6_gt_check_fifodbg(dev_priv); \
669 } \
670 hsw_unclaimed_reg_check(dev_priv, reg); \
671 REG_WRITE_FOOTER; \
672 }
673
674 static const u32 gen8_shadowed_regs[] = {
675 FORCEWAKE_MT,
676 GEN6_RPNSWREQ,
677 GEN6_RC_VIDEO_FREQ,
678 RING_TAIL(RENDER_RING_BASE),
679 RING_TAIL(GEN6_BSD_RING_BASE),
680 RING_TAIL(VEBOX_RING_BASE),
681 RING_TAIL(BLT_RING_BASE),
682 /* TODO: Other registers are not yet used */
683 };
684
685 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
686 {
687 int i;
688 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
689 if (reg == gen8_shadowed_regs[i])
690 return true;
691
692 return false;
693 }
694
695 #define __gen8_write(x) \
696 static void \
697 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
698 REG_WRITE_HEADER; \
699 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
700 if (dev_priv->uncore.forcewake_count == 0) \
701 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
702 FORCEWAKE_ALL); \
703 __raw_i915_write##x(dev_priv, reg, val); \
704 if (dev_priv->uncore.forcewake_count == 0) \
705 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
706 FORCEWAKE_ALL); \
707 } else { \
708 __raw_i915_write##x(dev_priv, reg, val); \
709 } \
710 REG_WRITE_FOOTER; \
711 }
712
713 __gen8_write(8)
714 __gen8_write(16)
715 __gen8_write(32)
716 __gen8_write(64)
717 __hsw_write(8)
718 __hsw_write(16)
719 __hsw_write(32)
720 __hsw_write(64)
721 __gen6_write(8)
722 __gen6_write(16)
723 __gen6_write(32)
724 __gen6_write(64)
725 __gen5_write(8)
726 __gen5_write(16)
727 __gen5_write(32)
728 __gen5_write(64)
729 __gen4_write(8)
730 __gen4_write(16)
731 __gen4_write(32)
732 __gen4_write(64)
733
734 #undef __gen8_write
735 #undef __hsw_write
736 #undef __gen6_write
737 #undef __gen5_write
738 #undef __gen4_write
739 #undef REG_WRITE_FOOTER
740 #undef REG_WRITE_HEADER
741
742 void intel_uncore_init(struct drm_device *dev)
743 {
744 struct drm_i915_private *dev_priv = dev->dev_private;
745
746 setup_timer(&dev_priv->uncore.force_wake_timer,
747 gen6_force_wake_timer, (unsigned long)dev_priv);
748
749 intel_uncore_early_sanitize(dev);
750
751 if (IS_VALLEYVIEW(dev)) {
752 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
753 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
754 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
755 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
756 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
757 } else if (IS_IVYBRIDGE(dev)) {
758 u32 ecobus;
759
760 /* IVB configs may use multi-threaded forcewake */
761
762 /* A small trick here - if the bios hasn't configured
763 * MT forcewake, and if the device is in RC6, then
764 * force_wake_mt_get will not wake the device and the
765 * ECOBUS read will return zero. Which will be
766 * (correctly) interpreted by the test below as MT
767 * forcewake being disabled.
768 */
769 mutex_lock(&dev->struct_mutex);
770 __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
771 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
772 __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
773 mutex_unlock(&dev->struct_mutex);
774
775 if (ecobus & FORCEWAKE_MT_ENABLE) {
776 dev_priv->uncore.funcs.force_wake_get =
777 __gen7_gt_force_wake_mt_get;
778 dev_priv->uncore.funcs.force_wake_put =
779 __gen7_gt_force_wake_mt_put;
780 } else {
781 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
782 DRM_INFO("when using vblank-synced partial screen updates.\n");
783 dev_priv->uncore.funcs.force_wake_get =
784 __gen6_gt_force_wake_get;
785 dev_priv->uncore.funcs.force_wake_put =
786 __gen6_gt_force_wake_put;
787 }
788 } else if (IS_GEN6(dev)) {
789 dev_priv->uncore.funcs.force_wake_get =
790 __gen6_gt_force_wake_get;
791 dev_priv->uncore.funcs.force_wake_put =
792 __gen6_gt_force_wake_put;
793 }
794
795 switch (INTEL_INFO(dev)->gen) {
796 default:
797 dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
798 dev_priv->uncore.funcs.mmio_writew = gen8_write16;
799 dev_priv->uncore.funcs.mmio_writel = gen8_write32;
800 dev_priv->uncore.funcs.mmio_writeq = gen8_write64;
801 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
802 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
803 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
804 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
805 break;
806 case 7:
807 case 6:
808 if (IS_HASWELL(dev)) {
809 dev_priv->uncore.funcs.mmio_writeb = hsw_write8;
810 dev_priv->uncore.funcs.mmio_writew = hsw_write16;
811 dev_priv->uncore.funcs.mmio_writel = hsw_write32;
812 dev_priv->uncore.funcs.mmio_writeq = hsw_write64;
813 } else {
814 dev_priv->uncore.funcs.mmio_writeb = gen6_write8;
815 dev_priv->uncore.funcs.mmio_writew = gen6_write16;
816 dev_priv->uncore.funcs.mmio_writel = gen6_write32;
817 dev_priv->uncore.funcs.mmio_writeq = gen6_write64;
818 }
819
820 if (IS_VALLEYVIEW(dev)) {
821 dev_priv->uncore.funcs.mmio_readb = vlv_read8;
822 dev_priv->uncore.funcs.mmio_readw = vlv_read16;
823 dev_priv->uncore.funcs.mmio_readl = vlv_read32;
824 dev_priv->uncore.funcs.mmio_readq = vlv_read64;
825 } else {
826 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
827 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
828 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
829 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
830 }
831 break;
832 case 5:
833 dev_priv->uncore.funcs.mmio_writeb = gen5_write8;
834 dev_priv->uncore.funcs.mmio_writew = gen5_write16;
835 dev_priv->uncore.funcs.mmio_writel = gen5_write32;
836 dev_priv->uncore.funcs.mmio_writeq = gen5_write64;
837 dev_priv->uncore.funcs.mmio_readb = gen5_read8;
838 dev_priv->uncore.funcs.mmio_readw = gen5_read16;
839 dev_priv->uncore.funcs.mmio_readl = gen5_read32;
840 dev_priv->uncore.funcs.mmio_readq = gen5_read64;
841 break;
842 case 4:
843 case 3:
844 case 2:
845 dev_priv->uncore.funcs.mmio_writeb = gen4_write8;
846 dev_priv->uncore.funcs.mmio_writew = gen4_write16;
847 dev_priv->uncore.funcs.mmio_writel = gen4_write32;
848 dev_priv->uncore.funcs.mmio_writeq = gen4_write64;
849 dev_priv->uncore.funcs.mmio_readb = gen4_read8;
850 dev_priv->uncore.funcs.mmio_readw = gen4_read16;
851 dev_priv->uncore.funcs.mmio_readl = gen4_read32;
852 dev_priv->uncore.funcs.mmio_readq = gen4_read64;
853 break;
854 }
855 }
856
857 void intel_uncore_fini(struct drm_device *dev)
858 {
859 /* Paranoia: make sure we have disabled everything before we exit. */
860 intel_uncore_sanitize(dev);
861 intel_uncore_forcewake_reset(dev, false);
862 }
863
864 #define GEN_RANGE(l, h) GENMASK(h, l)
865
866 static const struct register_whitelist {
867 uint64_t offset;
868 uint32_t size;
869 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
870 uint32_t gen_bitmask;
871 } whitelist[] = {
872 { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 8) },
873 };
874
875 int i915_reg_read_ioctl(struct drm_device *dev,
876 void *data, struct drm_file *file)
877 {
878 struct drm_i915_private *dev_priv = dev->dev_private;
879 struct drm_i915_reg_read *reg = data;
880 struct register_whitelist const *entry = whitelist;
881 int i, ret = 0;
882
883 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
884 if (entry->offset == reg->offset &&
885 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
886 break;
887 }
888
889 if (i == ARRAY_SIZE(whitelist))
890 return -EINVAL;
891
892 intel_runtime_pm_get(dev_priv);
893
894 switch (entry->size) {
895 case 8:
896 reg->val = I915_READ64(reg->offset);
897 break;
898 case 4:
899 reg->val = I915_READ(reg->offset);
900 break;
901 case 2:
902 reg->val = I915_READ16(reg->offset);
903 break;
904 case 1:
905 reg->val = I915_READ8(reg->offset);
906 break;
907 default:
908 WARN_ON(1);
909 ret = -EINVAL;
910 goto out;
911 }
912
913 out:
914 intel_runtime_pm_put(dev_priv);
915 return ret;
916 }
917
918 int i915_get_reset_stats_ioctl(struct drm_device *dev,
919 void *data, struct drm_file *file)
920 {
921 struct drm_i915_private *dev_priv = dev->dev_private;
922 struct drm_i915_reset_stats *args = data;
923 struct i915_ctx_hang_stats *hs;
924 struct i915_hw_context *ctx;
925 int ret;
926
927 if (args->flags || args->pad)
928 return -EINVAL;
929
930 if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN))
931 return -EPERM;
932
933 ret = mutex_lock_interruptible(&dev->struct_mutex);
934 if (ret)
935 return ret;
936
937 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
938 if (IS_ERR(ctx)) {
939 mutex_unlock(&dev->struct_mutex);
940 return PTR_ERR(ctx);
941 }
942 hs = &ctx->hang_stats;
943
944 if (capable(CAP_SYS_ADMIN))
945 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
946 else
947 args->reset_count = 0;
948
949 args->batch_active = hs->batch_active;
950 args->batch_pending = hs->batch_pending;
951
952 mutex_unlock(&dev->struct_mutex);
953
954 return 0;
955 }
956
957 static int i965_reset_complete(struct drm_device *dev)
958 {
959 u8 gdrst;
960 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
961 return (gdrst & GRDOM_RESET_ENABLE) == 0;
962 }
963
964 static int i965_do_reset(struct drm_device *dev)
965 {
966 int ret;
967
968 /*
969 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
970 * well as the reset bit (GR/bit 0). Setting the GR bit
971 * triggers the reset; when done, the hardware will clear it.
972 */
973 pci_write_config_byte(dev->pdev, I965_GDRST,
974 GRDOM_RENDER | GRDOM_RESET_ENABLE);
975 ret = wait_for(i965_reset_complete(dev), 500);
976 if (ret)
977 return ret;
978
979 /* We can't reset render&media without also resetting display ... */
980 pci_write_config_byte(dev->pdev, I965_GDRST,
981 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
982
983 ret = wait_for(i965_reset_complete(dev), 500);
984 if (ret)
985 return ret;
986
987 pci_write_config_byte(dev->pdev, I965_GDRST, 0);
988
989 return 0;
990 }
991
992 static int ironlake_do_reset(struct drm_device *dev)
993 {
994 struct drm_i915_private *dev_priv = dev->dev_private;
995 u32 gdrst;
996 int ret;
997
998 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
999 gdrst &= ~GRDOM_MASK;
1000 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1001 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
1002 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
1003 if (ret)
1004 return ret;
1005
1006 /* We can't reset render&media without also resetting display ... */
1007 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
1008 gdrst &= ~GRDOM_MASK;
1009 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1010 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1011 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
1012 }
1013
1014 static int gen6_do_reset(struct drm_device *dev)
1015 {
1016 struct drm_i915_private *dev_priv = dev->dev_private;
1017 int ret;
1018
1019 /* Reset the chip */
1020
1021 /* GEN6_GDRST is not in the gt power well, no need to check
1022 * for fifo space for the write or forcewake the chip for
1023 * the read
1024 */
1025 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1026
1027 /* Spin waiting for the device to ack the reset request */
1028 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1029
1030 intel_uncore_forcewake_reset(dev, true);
1031
1032 return ret;
1033 }
1034
1035 int intel_gpu_reset(struct drm_device *dev)
1036 {
1037 switch (INTEL_INFO(dev)->gen) {
1038 case 8:
1039 case 7:
1040 case 6: return gen6_do_reset(dev);
1041 case 5: return ironlake_do_reset(dev);
1042 case 4: return i965_do_reset(dev);
1043 default: return -ENODEV;
1044 }
1045 }
1046
1047 void intel_uncore_check_errors(struct drm_device *dev)
1048 {
1049 struct drm_i915_private *dev_priv = dev->dev_private;
1050
1051 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1052 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1053 DRM_ERROR("Unclaimed register before interrupt\n");
1054 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1055 }
1056 }
Linux kernel - Deliverables
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