2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
27 #define FORCEWAKE_ACK_TIMEOUT_MS 2
29 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
32 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
35 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
38 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
41 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
44 assert_device_not_suspended(struct drm_i915_private
*dev_priv
)
46 WARN(HAS_RUNTIME_PM(dev_priv
->dev
) && dev_priv
->pm
.suspended
,
47 "Device suspended\n");
50 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private
*dev_priv
)
52 u32 gt_thread_status_mask
;
54 if (IS_HASWELL(dev_priv
->dev
))
55 gt_thread_status_mask
= GEN6_GT_THREAD_STATUS_CORE_MASK_HSW
;
57 gt_thread_status_mask
= GEN6_GT_THREAD_STATUS_CORE_MASK
;
59 /* w/a for a sporadic read returning 0 by waiting for the GT
62 if (wait_for_atomic_us((__raw_i915_read32(dev_priv
, GEN6_GT_THREAD_STATUS_REG
) & gt_thread_status_mask
) == 0, 500))
63 DRM_ERROR("GT thread status wait timed out\n");
66 static void __gen6_gt_force_wake_reset(struct drm_i915_private
*dev_priv
)
68 __raw_i915_write32(dev_priv
, FORCEWAKE
, 0);
69 /* something from same cacheline, but !FORCEWAKE */
70 __raw_posting_read(dev_priv
, ECOBUS
);
73 static void __gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
,
76 if (wait_for_atomic((__raw_i915_read32(dev_priv
, FORCEWAKE_ACK
) & 1) == 0,
77 FORCEWAKE_ACK_TIMEOUT_MS
))
78 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
80 __raw_i915_write32(dev_priv
, FORCEWAKE
, 1);
81 /* something from same cacheline, but !FORCEWAKE */
82 __raw_posting_read(dev_priv
, ECOBUS
);
84 if (wait_for_atomic((__raw_i915_read32(dev_priv
, FORCEWAKE_ACK
) & 1),
85 FORCEWAKE_ACK_TIMEOUT_MS
))
86 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
88 /* WaRsForcewakeWaitTC0:snb */
89 __gen6_gt_wait_for_thread_c0(dev_priv
);
92 static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private
*dev_priv
)
94 __raw_i915_write32(dev_priv
, FORCEWAKE_MT
, _MASKED_BIT_DISABLE(0xffff));
95 /* something from same cacheline, but !FORCEWAKE_MT */
96 __raw_posting_read(dev_priv
, ECOBUS
);
99 static void __gen7_gt_force_wake_mt_get(struct drm_i915_private
*dev_priv
,
104 if (IS_HASWELL(dev_priv
->dev
) || IS_GEN8(dev_priv
->dev
))
105 forcewake_ack
= FORCEWAKE_ACK_HSW
;
107 forcewake_ack
= FORCEWAKE_MT_ACK
;
109 if (wait_for_atomic((__raw_i915_read32(dev_priv
, forcewake_ack
) & FORCEWAKE_KERNEL
) == 0,
110 FORCEWAKE_ACK_TIMEOUT_MS
))
111 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
113 __raw_i915_write32(dev_priv
, FORCEWAKE_MT
,
114 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
115 /* something from same cacheline, but !FORCEWAKE_MT */
116 __raw_posting_read(dev_priv
, ECOBUS
);
118 if (wait_for_atomic((__raw_i915_read32(dev_priv
, forcewake_ack
) & FORCEWAKE_KERNEL
),
119 FORCEWAKE_ACK_TIMEOUT_MS
))
120 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
122 /* WaRsForcewakeWaitTC0:ivb,hsw */
123 if (INTEL_INFO(dev_priv
->dev
)->gen
< 8)
124 __gen6_gt_wait_for_thread_c0(dev_priv
);
127 static void gen6_gt_check_fifodbg(struct drm_i915_private
*dev_priv
)
131 gtfifodbg
= __raw_i915_read32(dev_priv
, GTFIFODBG
);
132 if (WARN(gtfifodbg
, "GT wake FIFO error 0x%x\n", gtfifodbg
))
133 __raw_i915_write32(dev_priv
, GTFIFODBG
, gtfifodbg
);
136 static void __gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
,
139 __raw_i915_write32(dev_priv
, FORCEWAKE
, 0);
140 /* something from same cacheline, but !FORCEWAKE */
141 __raw_posting_read(dev_priv
, ECOBUS
);
142 gen6_gt_check_fifodbg(dev_priv
);
145 static void __gen7_gt_force_wake_mt_put(struct drm_i915_private
*dev_priv
,
148 __raw_i915_write32(dev_priv
, FORCEWAKE_MT
,
149 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
150 /* something from same cacheline, but !FORCEWAKE_MT */
151 __raw_posting_read(dev_priv
, ECOBUS
);
153 if (IS_GEN7(dev_priv
->dev
))
154 gen6_gt_check_fifodbg(dev_priv
);
157 static int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
161 /* On VLV, FIFO will be shared by both SW and HW.
162 * So, we need to read the FREE_ENTRIES everytime */
163 if (IS_VALLEYVIEW(dev_priv
->dev
))
164 dev_priv
->uncore
.fifo_count
=
165 __raw_i915_read32(dev_priv
, GTFIFOCTL
) &
166 GT_FIFO_FREE_ENTRIES_MASK
;
168 if (dev_priv
->uncore
.fifo_count
< GT_FIFO_NUM_RESERVED_ENTRIES
) {
170 u32 fifo
= __raw_i915_read32(dev_priv
, GTFIFOCTL
) & GT_FIFO_FREE_ENTRIES_MASK
;
171 while (fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
&& loop
--) {
173 fifo
= __raw_i915_read32(dev_priv
, GTFIFOCTL
) & GT_FIFO_FREE_ENTRIES_MASK
;
175 if (WARN_ON(loop
< 0 && fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
))
177 dev_priv
->uncore
.fifo_count
= fifo
;
179 dev_priv
->uncore
.fifo_count
--;
184 static void vlv_force_wake_reset(struct drm_i915_private
*dev_priv
)
186 __raw_i915_write32(dev_priv
, FORCEWAKE_VLV
,
187 _MASKED_BIT_DISABLE(0xffff));
188 /* something from same cacheline, but !FORCEWAKE_VLV */
189 __raw_posting_read(dev_priv
, FORCEWAKE_ACK_VLV
);
192 static void __vlv_force_wake_get(struct drm_i915_private
*dev_priv
,
195 /* Check for Render Engine */
196 if (FORCEWAKE_RENDER
& fw_engine
) {
197 if (wait_for_atomic((__raw_i915_read32(dev_priv
,
199 FORCEWAKE_KERNEL
) == 0,
200 FORCEWAKE_ACK_TIMEOUT_MS
))
201 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
203 __raw_i915_write32(dev_priv
, FORCEWAKE_VLV
,
204 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
206 if (wait_for_atomic((__raw_i915_read32(dev_priv
,
209 FORCEWAKE_ACK_TIMEOUT_MS
))
210 DRM_ERROR("Timed out: waiting for Render to ack.\n");
213 /* Check for Media Engine */
214 if (FORCEWAKE_MEDIA
& fw_engine
) {
215 if (wait_for_atomic((__raw_i915_read32(dev_priv
,
216 FORCEWAKE_ACK_MEDIA_VLV
) &
217 FORCEWAKE_KERNEL
) == 0,
218 FORCEWAKE_ACK_TIMEOUT_MS
))
219 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
221 __raw_i915_write32(dev_priv
, FORCEWAKE_MEDIA_VLV
,
222 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
224 if (wait_for_atomic((__raw_i915_read32(dev_priv
,
225 FORCEWAKE_ACK_MEDIA_VLV
) &
227 FORCEWAKE_ACK_TIMEOUT_MS
))
228 DRM_ERROR("Timed out: waiting for media to ack.\n");
231 /* WaRsForcewakeWaitTC0:vlv */
232 __gen6_gt_wait_for_thread_c0(dev_priv
);
236 static void __vlv_force_wake_put(struct drm_i915_private
*dev_priv
,
240 /* Check for Render Engine */
241 if (FORCEWAKE_RENDER
& fw_engine
)
242 __raw_i915_write32(dev_priv
, FORCEWAKE_VLV
,
243 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
246 /* Check for Media Engine */
247 if (FORCEWAKE_MEDIA
& fw_engine
)
248 __raw_i915_write32(dev_priv
, FORCEWAKE_MEDIA_VLV
,
249 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
251 /* The below doubles as a POSTING_READ */
252 gen6_gt_check_fifodbg(dev_priv
);
256 void vlv_force_wake_get(struct drm_i915_private
*dev_priv
,
259 unsigned long irqflags
;
261 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
263 if (fw_engine
& FORCEWAKE_RENDER
&&
264 dev_priv
->uncore
.fw_rendercount
++ != 0)
265 fw_engine
&= ~FORCEWAKE_RENDER
;
266 if (fw_engine
& FORCEWAKE_MEDIA
&&
267 dev_priv
->uncore
.fw_mediacount
++ != 0)
268 fw_engine
&= ~FORCEWAKE_MEDIA
;
271 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw_engine
);
273 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
276 void vlv_force_wake_put(struct drm_i915_private
*dev_priv
,
279 unsigned long irqflags
;
281 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
283 if (fw_engine
& FORCEWAKE_RENDER
&&
284 --dev_priv
->uncore
.fw_rendercount
!= 0)
285 fw_engine
&= ~FORCEWAKE_RENDER
;
286 if (fw_engine
& FORCEWAKE_MEDIA
&&
287 --dev_priv
->uncore
.fw_mediacount
!= 0)
288 fw_engine
&= ~FORCEWAKE_MEDIA
;
291 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, fw_engine
);
293 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
296 static void gen6_force_wake_timer(unsigned long arg
)
298 struct drm_i915_private
*dev_priv
= (void *)arg
;
299 unsigned long irqflags
;
301 assert_device_not_suspended(dev_priv
);
303 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
304 if (--dev_priv
->uncore
.forcewake_count
== 0)
305 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
306 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
308 intel_runtime_pm_put(dev_priv
);
311 static void intel_uncore_forcewake_reset(struct drm_device
*dev
)
313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
315 if (IS_VALLEYVIEW(dev
))
316 vlv_force_wake_reset(dev_priv
);
317 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
318 __gen6_gt_force_wake_reset(dev_priv
);
320 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
) || IS_GEN8(dev
))
321 __gen7_gt_force_wake_mt_reset(dev_priv
);
324 void intel_uncore_early_sanitize(struct drm_device
*dev
)
326 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
328 if (HAS_FPGA_DBG_UNCLAIMED(dev
))
329 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
331 if (IS_HASWELL(dev
) &&
332 (__raw_i915_read32(dev_priv
, HSW_EDRAM_PRESENT
) == 1)) {
333 /* The docs do not explain exactly how the calculation can be
334 * made. It is somewhat guessable, but for now, it's always
336 * NB: We can't write IDICR yet because we do not have gt funcs
338 dev_priv
->ellc_size
= 128;
339 DRM_INFO("Found %zuMB of eLLC\n", dev_priv
->ellc_size
);
342 /* clear out old GT FIFO errors */
343 if (IS_GEN6(dev
) || IS_GEN7(dev
))
344 __raw_i915_write32(dev_priv
, GTFIFODBG
,
345 __raw_i915_read32(dev_priv
, GTFIFODBG
));
347 intel_uncore_forcewake_reset(dev
);
350 void intel_uncore_sanitize(struct drm_device
*dev
)
352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
355 /* BIOS often leaves RC6 enabled, but disable it for hw init */
356 intel_disable_gt_powersave(dev
);
358 /* Turn off power gate, require especially for the BIOS less system */
359 if (IS_VALLEYVIEW(dev
)) {
361 mutex_lock(&dev_priv
->rps
.hw_lock
);
362 reg_val
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_STATUS
);
364 if (reg_val
& (PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_RENDER
) |
365 PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_MEDIA
) |
366 PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_DISP2D
)))
367 vlv_punit_write(dev_priv
, PUNIT_REG_PWRGT_CTRL
, 0x0);
369 mutex_unlock(&dev_priv
->rps
.hw_lock
);
375 * Generally this is called implicitly by the register read function. However,
376 * if some sequence requires the GT to not power down then this function should
377 * be called at the beginning of the sequence followed by a call to
378 * gen6_gt_force_wake_put() at the end of the sequence.
380 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
)
382 unsigned long irqflags
;
384 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
387 intel_runtime_pm_get(dev_priv
);
389 /* Redirect to VLV specific routine */
390 if (IS_VALLEYVIEW(dev_priv
->dev
))
391 return vlv_force_wake_get(dev_priv
, fw_engine
);
393 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
394 if (dev_priv
->uncore
.forcewake_count
++ == 0)
395 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
396 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
400 * see gen6_gt_force_wake_get()
402 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
)
404 unsigned long irqflags
;
405 bool delayed
= false;
407 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
410 /* Redirect to VLV specific routine */
411 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
412 vlv_force_wake_put(dev_priv
, fw_engine
);
417 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
418 if (--dev_priv
->uncore
.forcewake_count
== 0) {
419 dev_priv
->uncore
.forcewake_count
++;
421 mod_timer_pinned(&dev_priv
->uncore
.force_wake_timer
,
424 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
428 intel_runtime_pm_put(dev_priv
);
431 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
)
433 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
436 WARN_ON(dev_priv
->uncore
.forcewake_count
> 0);
439 /* We give fast paths for the really cool registers */
440 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
441 ((reg) < 0x40000 && (reg) != FORCEWAKE)
444 ilk_dummy_write(struct drm_i915_private
*dev_priv
)
446 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
447 * the chip from rc6 before touching it for real. MI_MODE is masked,
448 * hence harmless to write 0 into. */
449 __raw_i915_write32(dev_priv
, MI_MODE
, 0);
453 hsw_unclaimed_reg_clear(struct drm_i915_private
*dev_priv
, u32 reg
)
455 if (__raw_i915_read32(dev_priv
, FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
) {
456 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
458 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
463 hsw_unclaimed_reg_check(struct drm_i915_private
*dev_priv
, u32 reg
)
465 if (__raw_i915_read32(dev_priv
, FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
) {
466 DRM_ERROR("Unclaimed write to %x\n", reg
);
467 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
471 #define REG_READ_HEADER(x) \
472 unsigned long irqflags; \
474 assert_device_not_suspended(dev_priv); \
475 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
477 #define REG_READ_FOOTER \
478 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
479 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
482 #define __gen4_read(x) \
484 gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
485 REG_READ_HEADER(x); \
486 val = __raw_i915_read##x(dev_priv, reg); \
490 #define __gen5_read(x) \
492 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
493 REG_READ_HEADER(x); \
494 ilk_dummy_write(dev_priv); \
495 val = __raw_i915_read##x(dev_priv, reg); \
499 #define __gen6_read(x) \
501 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
502 REG_READ_HEADER(x); \
503 if (dev_priv->uncore.forcewake_count == 0 && \
504 NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
505 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
507 dev_priv->uncore.forcewake_count++; \
508 mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \
511 val = __raw_i915_read##x(dev_priv, reg); \
515 #define __vlv_read(x) \
517 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
518 unsigned fwengine = 0; \
519 REG_READ_HEADER(x); \
520 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
521 if (dev_priv->uncore.fw_rendercount == 0) \
522 fwengine = FORCEWAKE_RENDER; \
523 } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
524 if (dev_priv->uncore.fw_mediacount == 0) \
525 fwengine = FORCEWAKE_MEDIA; \
528 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
529 val = __raw_i915_read##x(dev_priv, reg); \
531 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
557 #undef REG_READ_FOOTER
558 #undef REG_READ_HEADER
560 #define REG_WRITE_HEADER \
561 unsigned long irqflags; \
562 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
563 assert_device_not_suspended(dev_priv); \
564 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
566 #define REG_WRITE_FOOTER \
567 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
569 #define __gen4_write(x) \
571 gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
573 __raw_i915_write##x(dev_priv, reg, val); \
577 #define __gen5_write(x) \
579 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
581 ilk_dummy_write(dev_priv); \
582 __raw_i915_write##x(dev_priv, reg, val); \
586 #define __gen6_write(x) \
588 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
589 u32 __fifo_ret = 0; \
591 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
592 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
594 __raw_i915_write##x(dev_priv, reg, val); \
595 if (unlikely(__fifo_ret)) { \
596 gen6_gt_check_fifodbg(dev_priv); \
601 #define __hsw_write(x) \
603 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
604 u32 __fifo_ret = 0; \
606 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
607 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
609 hsw_unclaimed_reg_clear(dev_priv, reg); \
610 __raw_i915_write##x(dev_priv, reg, val); \
611 if (unlikely(__fifo_ret)) { \
612 gen6_gt_check_fifodbg(dev_priv); \
614 hsw_unclaimed_reg_check(dev_priv, reg); \
618 static const u32 gen8_shadowed_regs
[] = {
622 RING_TAIL(RENDER_RING_BASE
),
623 RING_TAIL(GEN6_BSD_RING_BASE
),
624 RING_TAIL(VEBOX_RING_BASE
),
625 RING_TAIL(BLT_RING_BASE
),
626 /* TODO: Other registers are not yet used */
629 static bool is_gen8_shadowed(struct drm_i915_private
*dev_priv
, u32 reg
)
632 for (i
= 0; i
< ARRAY_SIZE(gen8_shadowed_regs
); i
++)
633 if (reg
== gen8_shadowed_regs
[i
])
639 #define __gen8_write(x) \
641 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
643 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
644 if (dev_priv->uncore.forcewake_count == 0) \
645 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
647 __raw_i915_write##x(dev_priv, reg, val); \
648 if (dev_priv->uncore.forcewake_count == 0) \
649 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
652 __raw_i915_write##x(dev_priv, reg, val); \
683 #undef REG_WRITE_FOOTER
684 #undef REG_WRITE_HEADER
686 void intel_uncore_init(struct drm_device
*dev
)
688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
690 setup_timer(&dev_priv
->uncore
.force_wake_timer
,
691 gen6_force_wake_timer
, (unsigned long)dev_priv
);
693 if (IS_VALLEYVIEW(dev
)) {
694 dev_priv
->uncore
.funcs
.force_wake_get
= __vlv_force_wake_get
;
695 dev_priv
->uncore
.funcs
.force_wake_put
= __vlv_force_wake_put
;
696 } else if (IS_HASWELL(dev
) || IS_GEN8(dev
)) {
697 dev_priv
->uncore
.funcs
.force_wake_get
= __gen7_gt_force_wake_mt_get
;
698 dev_priv
->uncore
.funcs
.force_wake_put
= __gen7_gt_force_wake_mt_put
;
699 } else if (IS_IVYBRIDGE(dev
)) {
702 /* IVB configs may use multi-threaded forcewake */
704 /* A small trick here - if the bios hasn't configured
705 * MT forcewake, and if the device is in RC6, then
706 * force_wake_mt_get will not wake the device and the
707 * ECOBUS read will return zero. Which will be
708 * (correctly) interpreted by the test below as MT
709 * forcewake being disabled.
711 mutex_lock(&dev
->struct_mutex
);
712 __gen7_gt_force_wake_mt_get(dev_priv
, FORCEWAKE_ALL
);
713 ecobus
= __raw_i915_read32(dev_priv
, ECOBUS
);
714 __gen7_gt_force_wake_mt_put(dev_priv
, FORCEWAKE_ALL
);
715 mutex_unlock(&dev
->struct_mutex
);
717 if (ecobus
& FORCEWAKE_MT_ENABLE
) {
718 dev_priv
->uncore
.funcs
.force_wake_get
=
719 __gen7_gt_force_wake_mt_get
;
720 dev_priv
->uncore
.funcs
.force_wake_put
=
721 __gen7_gt_force_wake_mt_put
;
723 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
724 DRM_INFO("when using vblank-synced partial screen updates.\n");
725 dev_priv
->uncore
.funcs
.force_wake_get
=
726 __gen6_gt_force_wake_get
;
727 dev_priv
->uncore
.funcs
.force_wake_put
=
728 __gen6_gt_force_wake_put
;
730 } else if (IS_GEN6(dev
)) {
731 dev_priv
->uncore
.funcs
.force_wake_get
=
732 __gen6_gt_force_wake_get
;
733 dev_priv
->uncore
.funcs
.force_wake_put
=
734 __gen6_gt_force_wake_put
;
737 switch (INTEL_INFO(dev
)->gen
) {
739 dev_priv
->uncore
.funcs
.mmio_writeb
= gen8_write8
;
740 dev_priv
->uncore
.funcs
.mmio_writew
= gen8_write16
;
741 dev_priv
->uncore
.funcs
.mmio_writel
= gen8_write32
;
742 dev_priv
->uncore
.funcs
.mmio_writeq
= gen8_write64
;
743 dev_priv
->uncore
.funcs
.mmio_readb
= gen6_read8
;
744 dev_priv
->uncore
.funcs
.mmio_readw
= gen6_read16
;
745 dev_priv
->uncore
.funcs
.mmio_readl
= gen6_read32
;
746 dev_priv
->uncore
.funcs
.mmio_readq
= gen6_read64
;
750 if (IS_HASWELL(dev
)) {
751 dev_priv
->uncore
.funcs
.mmio_writeb
= hsw_write8
;
752 dev_priv
->uncore
.funcs
.mmio_writew
= hsw_write16
;
753 dev_priv
->uncore
.funcs
.mmio_writel
= hsw_write32
;
754 dev_priv
->uncore
.funcs
.mmio_writeq
= hsw_write64
;
756 dev_priv
->uncore
.funcs
.mmio_writeb
= gen6_write8
;
757 dev_priv
->uncore
.funcs
.mmio_writew
= gen6_write16
;
758 dev_priv
->uncore
.funcs
.mmio_writel
= gen6_write32
;
759 dev_priv
->uncore
.funcs
.mmio_writeq
= gen6_write64
;
762 if (IS_VALLEYVIEW(dev
)) {
763 dev_priv
->uncore
.funcs
.mmio_readb
= vlv_read8
;
764 dev_priv
->uncore
.funcs
.mmio_readw
= vlv_read16
;
765 dev_priv
->uncore
.funcs
.mmio_readl
= vlv_read32
;
766 dev_priv
->uncore
.funcs
.mmio_readq
= vlv_read64
;
768 dev_priv
->uncore
.funcs
.mmio_readb
= gen6_read8
;
769 dev_priv
->uncore
.funcs
.mmio_readw
= gen6_read16
;
770 dev_priv
->uncore
.funcs
.mmio_readl
= gen6_read32
;
771 dev_priv
->uncore
.funcs
.mmio_readq
= gen6_read64
;
775 dev_priv
->uncore
.funcs
.mmio_writeb
= gen5_write8
;
776 dev_priv
->uncore
.funcs
.mmio_writew
= gen5_write16
;
777 dev_priv
->uncore
.funcs
.mmio_writel
= gen5_write32
;
778 dev_priv
->uncore
.funcs
.mmio_writeq
= gen5_write64
;
779 dev_priv
->uncore
.funcs
.mmio_readb
= gen5_read8
;
780 dev_priv
->uncore
.funcs
.mmio_readw
= gen5_read16
;
781 dev_priv
->uncore
.funcs
.mmio_readl
= gen5_read32
;
782 dev_priv
->uncore
.funcs
.mmio_readq
= gen5_read64
;
787 dev_priv
->uncore
.funcs
.mmio_writeb
= gen4_write8
;
788 dev_priv
->uncore
.funcs
.mmio_writew
= gen4_write16
;
789 dev_priv
->uncore
.funcs
.mmio_writel
= gen4_write32
;
790 dev_priv
->uncore
.funcs
.mmio_writeq
= gen4_write64
;
791 dev_priv
->uncore
.funcs
.mmio_readb
= gen4_read8
;
792 dev_priv
->uncore
.funcs
.mmio_readw
= gen4_read16
;
793 dev_priv
->uncore
.funcs
.mmio_readl
= gen4_read32
;
794 dev_priv
->uncore
.funcs
.mmio_readq
= gen4_read64
;
799 void intel_uncore_fini(struct drm_device
*dev
)
801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
803 del_timer_sync(&dev_priv
->uncore
.force_wake_timer
);
805 /* Paranoia: make sure we have disabled everything before we exit. */
806 intel_uncore_sanitize(dev
);
807 intel_uncore_forcewake_reset(dev
);
810 static const struct register_whitelist
{
813 uint32_t gen_bitmask
; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
815 { RING_TIMESTAMP(RENDER_RING_BASE
), 8, 0x1F0 },
818 int i915_reg_read_ioctl(struct drm_device
*dev
,
819 void *data
, struct drm_file
*file
)
821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
822 struct drm_i915_reg_read
*reg
= data
;
823 struct register_whitelist
const *entry
= whitelist
;
826 for (i
= 0; i
< ARRAY_SIZE(whitelist
); i
++, entry
++) {
827 if (entry
->offset
== reg
->offset
&&
828 (1 << INTEL_INFO(dev
)->gen
& entry
->gen_bitmask
))
832 if (i
== ARRAY_SIZE(whitelist
))
835 switch (entry
->size
) {
837 reg
->val
= I915_READ64(reg
->offset
);
840 reg
->val
= I915_READ(reg
->offset
);
843 reg
->val
= I915_READ16(reg
->offset
);
846 reg
->val
= I915_READ8(reg
->offset
);
856 int i915_get_reset_stats_ioctl(struct drm_device
*dev
,
857 void *data
, struct drm_file
*file
)
859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
860 struct drm_i915_reset_stats
*args
= data
;
861 struct i915_ctx_hang_stats
*hs
;
862 struct i915_hw_context
*ctx
;
865 if (args
->flags
|| args
->pad
)
868 if (args
->ctx_id
== DEFAULT_CONTEXT_ID
&& !capable(CAP_SYS_ADMIN
))
871 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
875 ctx
= i915_gem_context_get(file
->driver_priv
, args
->ctx_id
);
877 mutex_unlock(&dev
->struct_mutex
);
880 hs
= &ctx
->hang_stats
;
882 if (capable(CAP_SYS_ADMIN
))
883 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
885 args
->reset_count
= 0;
887 args
->batch_active
= hs
->batch_active
;
888 args
->batch_pending
= hs
->batch_pending
;
890 mutex_unlock(&dev
->struct_mutex
);
895 static int i965_reset_complete(struct drm_device
*dev
)
898 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
899 return (gdrst
& GRDOM_RESET_ENABLE
) == 0;
902 static int i965_do_reset(struct drm_device
*dev
)
907 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
908 * well as the reset bit (GR/bit 0). Setting the GR bit
909 * triggers the reset; when done, the hardware will clear it.
911 pci_write_config_byte(dev
->pdev
, I965_GDRST
,
912 GRDOM_RENDER
| GRDOM_RESET_ENABLE
);
913 ret
= wait_for(i965_reset_complete(dev
), 500);
917 /* We can't reset render&media without also resetting display ... */
918 pci_write_config_byte(dev
->pdev
, I965_GDRST
,
919 GRDOM_MEDIA
| GRDOM_RESET_ENABLE
);
921 ret
= wait_for(i965_reset_complete(dev
), 500);
925 pci_write_config_byte(dev
->pdev
, I965_GDRST
, 0);
930 static int ironlake_do_reset(struct drm_device
*dev
)
932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
936 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
937 gdrst
&= ~GRDOM_MASK
;
938 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
,
939 gdrst
| GRDOM_RENDER
| GRDOM_RESET_ENABLE
);
940 ret
= wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
944 /* We can't reset render&media without also resetting display ... */
945 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
946 gdrst
&= ~GRDOM_MASK
;
947 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
,
948 gdrst
| GRDOM_MEDIA
| GRDOM_RESET_ENABLE
);
949 return wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
952 static int gen6_do_reset(struct drm_device
*dev
)
954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
956 unsigned long irqflags
;
959 /* Hold uncore.lock across reset to prevent any register access
960 * with forcewake not set correctly
962 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
966 /* GEN6_GDRST is not in the gt power well, no need to check
967 * for fifo space for the write or forcewake the chip for
970 __raw_i915_write32(dev_priv
, GEN6_GDRST
, GEN6_GRDOM_FULL
);
972 /* Spin waiting for the device to ack the reset request */
973 ret
= wait_for((__raw_i915_read32(dev_priv
, GEN6_GDRST
) & GEN6_GRDOM_FULL
) == 0, 500);
975 intel_uncore_forcewake_reset(dev
);
977 /* If reset with a user forcewake, try to restore */
978 if (IS_VALLEYVIEW(dev
)) {
979 if (dev_priv
->uncore
.fw_rendercount
)
980 fw_engine
|= FORCEWAKE_RENDER
;
982 if (dev_priv
->uncore
.fw_mediacount
)
983 fw_engine
|= FORCEWAKE_MEDIA
;
985 if (dev_priv
->uncore
.forcewake_count
)
986 fw_engine
= FORCEWAKE_ALL
;
990 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw_engine
);
992 if (IS_GEN6(dev
) || IS_GEN7(dev
))
993 dev_priv
->uncore
.fifo_count
=
994 __raw_i915_read32(dev_priv
, GTFIFOCTL
) &
995 GT_FIFO_FREE_ENTRIES_MASK
;
997 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
1001 int intel_gpu_reset(struct drm_device
*dev
)
1003 switch (INTEL_INFO(dev
)->gen
) {
1006 case 6: return gen6_do_reset(dev
);
1007 case 5: return ironlake_do_reset(dev
);
1008 case 4: return i965_do_reset(dev
);
1009 default: return -ENODEV
;
1013 void intel_uncore_check_errors(struct drm_device
*dev
)
1015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1017 if (HAS_FPGA_DBG_UNCLAIMED(dev
) &&
1018 (__raw_i915_read32(dev_priv
, FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1019 DRM_ERROR("Unclaimed register before interrupt\n");
1020 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);