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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_uncore.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "i915_drv.h"
25 #include "intel_drv.h"
26
27 #define FORCEWAKE_ACK_TIMEOUT_MS 2
28
29 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
31
32 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
34
35 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
37
38 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
40
41 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
42
43 static void
44 assert_device_not_suspended(struct drm_i915_private *dev_priv)
45 {
46 WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
47 "Device suspended\n");
48 }
49
50 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
51 {
52 u32 gt_thread_status_mask;
53
54 if (IS_HASWELL(dev_priv->dev))
55 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
56 else
57 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
58
59 /* w/a for a sporadic read returning 0 by waiting for the GT
60 * thread to wake up.
61 */
62 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
63 DRM_ERROR("GT thread status wait timed out\n");
64 }
65
66 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
67 {
68 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
69 /* something from same cacheline, but !FORCEWAKE */
70 __raw_posting_read(dev_priv, ECOBUS);
71 }
72
73 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
74 int fw_engine)
75 {
76 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
77 FORCEWAKE_ACK_TIMEOUT_MS))
78 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
79
80 __raw_i915_write32(dev_priv, FORCEWAKE, 1);
81 /* something from same cacheline, but !FORCEWAKE */
82 __raw_posting_read(dev_priv, ECOBUS);
83
84 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
85 FORCEWAKE_ACK_TIMEOUT_MS))
86 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
87
88 /* WaRsForcewakeWaitTC0:snb */
89 __gen6_gt_wait_for_thread_c0(dev_priv);
90 }
91
92 static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
93 {
94 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
95 /* something from same cacheline, but !FORCEWAKE_MT */
96 __raw_posting_read(dev_priv, ECOBUS);
97 }
98
99 static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
100 int fw_engine)
101 {
102 u32 forcewake_ack;
103
104 if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
105 forcewake_ack = FORCEWAKE_ACK_HSW;
106 else
107 forcewake_ack = FORCEWAKE_MT_ACK;
108
109 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
110 FORCEWAKE_ACK_TIMEOUT_MS))
111 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
112
113 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
114 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
115 /* something from same cacheline, but !FORCEWAKE_MT */
116 __raw_posting_read(dev_priv, ECOBUS);
117
118 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
119 FORCEWAKE_ACK_TIMEOUT_MS))
120 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
121
122 /* WaRsForcewakeWaitTC0:ivb,hsw */
123 if (INTEL_INFO(dev_priv->dev)->gen < 8)
124 __gen6_gt_wait_for_thread_c0(dev_priv);
125 }
126
127 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
128 {
129 u32 gtfifodbg;
130
131 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
132 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
133 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
134 }
135
136 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
137 int fw_engine)
138 {
139 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
140 /* something from same cacheline, but !FORCEWAKE */
141 __raw_posting_read(dev_priv, ECOBUS);
142 gen6_gt_check_fifodbg(dev_priv);
143 }
144
145 static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
146 int fw_engine)
147 {
148 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
149 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
150 /* something from same cacheline, but !FORCEWAKE_MT */
151 __raw_posting_read(dev_priv, ECOBUS);
152
153 if (IS_GEN7(dev_priv->dev))
154 gen6_gt_check_fifodbg(dev_priv);
155 }
156
157 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
158 {
159 int ret = 0;
160
161 /* On VLV, FIFO will be shared by both SW and HW.
162 * So, we need to read the FREE_ENTRIES everytime */
163 if (IS_VALLEYVIEW(dev_priv->dev))
164 dev_priv->uncore.fifo_count =
165 __raw_i915_read32(dev_priv, GTFIFOCTL) &
166 GT_FIFO_FREE_ENTRIES_MASK;
167
168 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
169 int loop = 500;
170 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
171 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
172 udelay(10);
173 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
174 }
175 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
176 ++ret;
177 dev_priv->uncore.fifo_count = fifo;
178 }
179 dev_priv->uncore.fifo_count--;
180
181 return ret;
182 }
183
184 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
185 {
186 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
187 _MASKED_BIT_DISABLE(0xffff));
188 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
189 _MASKED_BIT_DISABLE(0xffff));
190 /* something from same cacheline, but !FORCEWAKE_VLV */
191 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
192 }
193
194 static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
195 int fw_engine)
196 {
197 /* Check for Render Engine */
198 if (FORCEWAKE_RENDER & fw_engine) {
199 if (wait_for_atomic((__raw_i915_read32(dev_priv,
200 FORCEWAKE_ACK_VLV) &
201 FORCEWAKE_KERNEL) == 0,
202 FORCEWAKE_ACK_TIMEOUT_MS))
203 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
204
205 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
206 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
207
208 if (wait_for_atomic((__raw_i915_read32(dev_priv,
209 FORCEWAKE_ACK_VLV) &
210 FORCEWAKE_KERNEL),
211 FORCEWAKE_ACK_TIMEOUT_MS))
212 DRM_ERROR("Timed out: waiting for Render to ack.\n");
213 }
214
215 /* Check for Media Engine */
216 if (FORCEWAKE_MEDIA & fw_engine) {
217 if (wait_for_atomic((__raw_i915_read32(dev_priv,
218 FORCEWAKE_ACK_MEDIA_VLV) &
219 FORCEWAKE_KERNEL) == 0,
220 FORCEWAKE_ACK_TIMEOUT_MS))
221 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
222
223 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
224 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
225
226 if (wait_for_atomic((__raw_i915_read32(dev_priv,
227 FORCEWAKE_ACK_MEDIA_VLV) &
228 FORCEWAKE_KERNEL),
229 FORCEWAKE_ACK_TIMEOUT_MS))
230 DRM_ERROR("Timed out: waiting for media to ack.\n");
231 }
232
233 /* WaRsForcewakeWaitTC0:vlv */
234 __gen6_gt_wait_for_thread_c0(dev_priv);
235
236 }
237
238 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
239 int fw_engine)
240 {
241
242 /* Check for Render Engine */
243 if (FORCEWAKE_RENDER & fw_engine)
244 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
245 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
246
247
248 /* Check for Media Engine */
249 if (FORCEWAKE_MEDIA & fw_engine)
250 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
251 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
252
253 /* The below doubles as a POSTING_READ */
254 gen6_gt_check_fifodbg(dev_priv);
255
256 }
257
258 static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
259 {
260 unsigned long irqflags;
261
262 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
263
264 if (fw_engine & FORCEWAKE_RENDER &&
265 dev_priv->uncore.fw_rendercount++ != 0)
266 fw_engine &= ~FORCEWAKE_RENDER;
267 if (fw_engine & FORCEWAKE_MEDIA &&
268 dev_priv->uncore.fw_mediacount++ != 0)
269 fw_engine &= ~FORCEWAKE_MEDIA;
270
271 if (fw_engine)
272 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
273
274 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
275 }
276
277 static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
278 {
279 unsigned long irqflags;
280
281 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
282
283 if (fw_engine & FORCEWAKE_RENDER) {
284 WARN_ON(!dev_priv->uncore.fw_rendercount);
285 if (--dev_priv->uncore.fw_rendercount != 0)
286 fw_engine &= ~FORCEWAKE_RENDER;
287 }
288
289 if (fw_engine & FORCEWAKE_MEDIA) {
290 WARN_ON(!dev_priv->uncore.fw_mediacount);
291 if (--dev_priv->uncore.fw_mediacount != 0)
292 fw_engine &= ~FORCEWAKE_MEDIA;
293 }
294
295 if (fw_engine)
296 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine);
297
298 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
299 }
300
301 static void gen6_force_wake_timer(unsigned long arg)
302 {
303 struct drm_i915_private *dev_priv = (void *)arg;
304 unsigned long irqflags;
305
306 assert_device_not_suspended(dev_priv);
307
308 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
309 WARN_ON(!dev_priv->uncore.forcewake_count);
310
311 if (--dev_priv->uncore.forcewake_count == 0)
312 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
313 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
314
315 intel_runtime_pm_put(dev_priv);
316 }
317
318 static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
319 {
320 struct drm_i915_private *dev_priv = dev->dev_private;
321 unsigned long irqflags;
322
323 del_timer_sync(&dev_priv->uncore.force_wake_timer);
324
325 /* Hold uncore.lock across reset to prevent any register access
326 * with forcewake not set correctly
327 */
328 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
329
330 if (IS_VALLEYVIEW(dev))
331 vlv_force_wake_reset(dev_priv);
332 else if (IS_GEN6(dev) || IS_GEN7(dev))
333 __gen6_gt_force_wake_reset(dev_priv);
334
335 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev))
336 __gen7_gt_force_wake_mt_reset(dev_priv);
337
338 if (restore) { /* If reset with a user forcewake, try to restore */
339 unsigned fw = 0;
340
341 if (IS_VALLEYVIEW(dev)) {
342 if (dev_priv->uncore.fw_rendercount)
343 fw |= FORCEWAKE_RENDER;
344
345 if (dev_priv->uncore.fw_mediacount)
346 fw |= FORCEWAKE_MEDIA;
347 } else {
348 if (dev_priv->uncore.forcewake_count)
349 fw = FORCEWAKE_ALL;
350 }
351
352 if (fw)
353 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
354
355 if (IS_GEN6(dev) || IS_GEN7(dev))
356 dev_priv->uncore.fifo_count =
357 __raw_i915_read32(dev_priv, GTFIFOCTL) &
358 GT_FIFO_FREE_ENTRIES_MASK;
359 } else {
360 dev_priv->uncore.forcewake_count = 0;
361 dev_priv->uncore.fw_rendercount = 0;
362 dev_priv->uncore.fw_mediacount = 0;
363 }
364
365 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
366 }
367
368 void intel_uncore_early_sanitize(struct drm_device *dev)
369 {
370 struct drm_i915_private *dev_priv = dev->dev_private;
371
372 if (HAS_FPGA_DBG_UNCLAIMED(dev))
373 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
374
375 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
376 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
377 /* The docs do not explain exactly how the calculation can be
378 * made. It is somewhat guessable, but for now, it's always
379 * 128MB.
380 * NB: We can't write IDICR yet because we do not have gt funcs
381 * set up */
382 dev_priv->ellc_size = 128;
383 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
384 }
385
386 /* clear out old GT FIFO errors */
387 if (IS_GEN6(dev) || IS_GEN7(dev))
388 __raw_i915_write32(dev_priv, GTFIFODBG,
389 __raw_i915_read32(dev_priv, GTFIFODBG));
390
391 intel_uncore_forcewake_reset(dev, false);
392 }
393
394 void intel_uncore_sanitize(struct drm_device *dev)
395 {
396 /* BIOS often leaves RC6 enabled, but disable it for hw init */
397 intel_disable_gt_powersave(dev);
398 }
399
400 /*
401 * Generally this is called implicitly by the register read function. However,
402 * if some sequence requires the GT to not power down then this function should
403 * be called at the beginning of the sequence followed by a call to
404 * gen6_gt_force_wake_put() at the end of the sequence.
405 */
406 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
407 {
408 unsigned long irqflags;
409
410 if (!dev_priv->uncore.funcs.force_wake_get)
411 return;
412
413 intel_runtime_pm_get(dev_priv);
414
415 /* Redirect to VLV specific routine */
416 if (IS_VALLEYVIEW(dev_priv->dev))
417 return vlv_force_wake_get(dev_priv, fw_engine);
418
419 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
420 if (dev_priv->uncore.forcewake_count++ == 0)
421 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
422 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
423 }
424
425 /*
426 * see gen6_gt_force_wake_get()
427 */
428 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
429 {
430 unsigned long irqflags;
431 bool delayed = false;
432
433 if (!dev_priv->uncore.funcs.force_wake_put)
434 return;
435
436 /* Redirect to VLV specific routine */
437 if (IS_VALLEYVIEW(dev_priv->dev)) {
438 vlv_force_wake_put(dev_priv, fw_engine);
439 goto out;
440 }
441
442
443 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
444 WARN_ON(!dev_priv->uncore.forcewake_count);
445
446 if (--dev_priv->uncore.forcewake_count == 0) {
447 dev_priv->uncore.forcewake_count++;
448 delayed = true;
449 mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
450 jiffies + 1);
451 }
452 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
453
454 out:
455 if (!delayed)
456 intel_runtime_pm_put(dev_priv);
457 }
458
459 void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
460 {
461 if (!dev_priv->uncore.funcs.force_wake_get)
462 return;
463
464 WARN_ON(dev_priv->uncore.forcewake_count > 0);
465 }
466
467 /* We give fast paths for the really cool registers */
468 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
469 ((reg) < 0x40000 && (reg) != FORCEWAKE)
470
471 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
472
473 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
474 (REG_RANGE((reg), 0x2000, 0x4000) || \
475 REG_RANGE((reg), 0x5000, 0x8000) || \
476 REG_RANGE((reg), 0xB000, 0x12000) || \
477 REG_RANGE((reg), 0x2E000, 0x30000))
478
479 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
480 (REG_RANGE((reg), 0x12000, 0x14000) || \
481 REG_RANGE((reg), 0x22000, 0x24000) || \
482 REG_RANGE((reg), 0x30000, 0x40000))
483
484 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
485 (REG_RANGE((reg), 0x2000, 0x4000) || \
486 REG_RANGE((reg), 0x5000, 0x8000) || \
487 REG_RANGE((reg), 0x8300, 0x8500) || \
488 REG_RANGE((reg), 0xB000, 0xC000) || \
489 REG_RANGE((reg), 0xE000, 0xE800))
490
491 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
492 (REG_RANGE((reg), 0x8800, 0x8900) || \
493 REG_RANGE((reg), 0xD000, 0xD800) || \
494 REG_RANGE((reg), 0x12000, 0x14000) || \
495 REG_RANGE((reg), 0x1A000, 0x1C000) || \
496 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
497 REG_RANGE((reg), 0x30000, 0x40000))
498
499 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
500 (REG_RANGE((reg), 0x4000, 0x5000) || \
501 REG_RANGE((reg), 0x8000, 0x8300) || \
502 REG_RANGE((reg), 0x8500, 0x8600) || \
503 REG_RANGE((reg), 0x9000, 0xB000) || \
504 REG_RANGE((reg), 0xC000, 0xC800) || \
505 REG_RANGE((reg), 0xF000, 0x10000) || \
506 REG_RANGE((reg), 0x14000, 0x14400) || \
507 REG_RANGE((reg), 0x22000, 0x24000))
508
509 static void
510 ilk_dummy_write(struct drm_i915_private *dev_priv)
511 {
512 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
513 * the chip from rc6 before touching it for real. MI_MODE is masked,
514 * hence harmless to write 0 into. */
515 __raw_i915_write32(dev_priv, MI_MODE, 0);
516 }
517
518 static void
519 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
520 {
521 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
522 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
523 reg);
524 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
525 }
526 }
527
528 static void
529 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
530 {
531 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
532 DRM_ERROR("Unclaimed write to %x\n", reg);
533 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
534 }
535 }
536
537 #define REG_READ_HEADER(x) \
538 unsigned long irqflags; \
539 u##x val = 0; \
540 assert_device_not_suspended(dev_priv); \
541 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
542
543 #define REG_READ_FOOTER \
544 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
545 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
546 return val
547
548 #define __gen4_read(x) \
549 static u##x \
550 gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
551 REG_READ_HEADER(x); \
552 val = __raw_i915_read##x(dev_priv, reg); \
553 REG_READ_FOOTER; \
554 }
555
556 #define __gen5_read(x) \
557 static u##x \
558 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
559 REG_READ_HEADER(x); \
560 ilk_dummy_write(dev_priv); \
561 val = __raw_i915_read##x(dev_priv, reg); \
562 REG_READ_FOOTER; \
563 }
564
565 #define __gen6_read(x) \
566 static u##x \
567 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
568 REG_READ_HEADER(x); \
569 if (dev_priv->uncore.forcewake_count == 0 && \
570 NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
571 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
572 FORCEWAKE_ALL); \
573 val = __raw_i915_read##x(dev_priv, reg); \
574 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
575 FORCEWAKE_ALL); \
576 } else { \
577 val = __raw_i915_read##x(dev_priv, reg); \
578 } \
579 REG_READ_FOOTER; \
580 }
581
582 #define __vlv_read(x) \
583 static u##x \
584 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
585 unsigned fwengine = 0; \
586 REG_READ_HEADER(x); \
587 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
588 if (dev_priv->uncore.fw_rendercount == 0) \
589 fwengine = FORCEWAKE_RENDER; \
590 } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
591 if (dev_priv->uncore.fw_mediacount == 0) \
592 fwengine = FORCEWAKE_MEDIA; \
593 } \
594 if (fwengine) \
595 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
596 val = __raw_i915_read##x(dev_priv, reg); \
597 if (fwengine) \
598 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
599 REG_READ_FOOTER; \
600 }
601
602 #define __chv_read(x) \
603 static u##x \
604 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
605 unsigned fwengine = 0; \
606 REG_READ_HEADER(x); \
607 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
608 if (dev_priv->uncore.fw_rendercount == 0) \
609 fwengine = FORCEWAKE_RENDER; \
610 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
611 if (dev_priv->uncore.fw_mediacount == 0) \
612 fwengine = FORCEWAKE_MEDIA; \
613 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
614 if (dev_priv->uncore.fw_rendercount == 0) \
615 fwengine |= FORCEWAKE_RENDER; \
616 if (dev_priv->uncore.fw_mediacount == 0) \
617 fwengine |= FORCEWAKE_MEDIA; \
618 } \
619 if (fwengine) \
620 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
621 val = __raw_i915_read##x(dev_priv, reg); \
622 if (fwengine) \
623 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
624 REG_READ_FOOTER; \
625 }
626
627 __chv_read(8)
628 __chv_read(16)
629 __chv_read(32)
630 __chv_read(64)
631 __vlv_read(8)
632 __vlv_read(16)
633 __vlv_read(32)
634 __vlv_read(64)
635 __gen6_read(8)
636 __gen6_read(16)
637 __gen6_read(32)
638 __gen6_read(64)
639 __gen5_read(8)
640 __gen5_read(16)
641 __gen5_read(32)
642 __gen5_read(64)
643 __gen4_read(8)
644 __gen4_read(16)
645 __gen4_read(32)
646 __gen4_read(64)
647
648 #undef __chv_read
649 #undef __vlv_read
650 #undef __gen6_read
651 #undef __gen5_read
652 #undef __gen4_read
653 #undef REG_READ_FOOTER
654 #undef REG_READ_HEADER
655
656 #define REG_WRITE_HEADER \
657 unsigned long irqflags; \
658 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
659 assert_device_not_suspended(dev_priv); \
660 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
661
662 #define REG_WRITE_FOOTER \
663 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
664
665 #define __gen4_write(x) \
666 static void \
667 gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
668 REG_WRITE_HEADER; \
669 __raw_i915_write##x(dev_priv, reg, val); \
670 REG_WRITE_FOOTER; \
671 }
672
673 #define __gen5_write(x) \
674 static void \
675 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
676 REG_WRITE_HEADER; \
677 ilk_dummy_write(dev_priv); \
678 __raw_i915_write##x(dev_priv, reg, val); \
679 REG_WRITE_FOOTER; \
680 }
681
682 #define __gen6_write(x) \
683 static void \
684 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
685 u32 __fifo_ret = 0; \
686 REG_WRITE_HEADER; \
687 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
688 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
689 } \
690 __raw_i915_write##x(dev_priv, reg, val); \
691 if (unlikely(__fifo_ret)) { \
692 gen6_gt_check_fifodbg(dev_priv); \
693 } \
694 REG_WRITE_FOOTER; \
695 }
696
697 #define __hsw_write(x) \
698 static void \
699 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
700 u32 __fifo_ret = 0; \
701 REG_WRITE_HEADER; \
702 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
703 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
704 } \
705 hsw_unclaimed_reg_clear(dev_priv, reg); \
706 __raw_i915_write##x(dev_priv, reg, val); \
707 if (unlikely(__fifo_ret)) { \
708 gen6_gt_check_fifodbg(dev_priv); \
709 } \
710 hsw_unclaimed_reg_check(dev_priv, reg); \
711 REG_WRITE_FOOTER; \
712 }
713
714 static const u32 gen8_shadowed_regs[] = {
715 FORCEWAKE_MT,
716 GEN6_RPNSWREQ,
717 GEN6_RC_VIDEO_FREQ,
718 RING_TAIL(RENDER_RING_BASE),
719 RING_TAIL(GEN6_BSD_RING_BASE),
720 RING_TAIL(VEBOX_RING_BASE),
721 RING_TAIL(BLT_RING_BASE),
722 /* TODO: Other registers are not yet used */
723 };
724
725 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
726 {
727 int i;
728 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
729 if (reg == gen8_shadowed_regs[i])
730 return true;
731
732 return false;
733 }
734
735 #define __gen8_write(x) \
736 static void \
737 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
738 REG_WRITE_HEADER; \
739 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
740 if (dev_priv->uncore.forcewake_count == 0) \
741 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
742 FORCEWAKE_ALL); \
743 __raw_i915_write##x(dev_priv, reg, val); \
744 if (dev_priv->uncore.forcewake_count == 0) \
745 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
746 FORCEWAKE_ALL); \
747 } else { \
748 __raw_i915_write##x(dev_priv, reg, val); \
749 } \
750 REG_WRITE_FOOTER; \
751 }
752
753 #define __chv_write(x) \
754 static void \
755 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
756 unsigned fwengine = 0; \
757 bool shadowed = is_gen8_shadowed(dev_priv, reg); \
758 REG_WRITE_HEADER; \
759 if (!shadowed) { \
760 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
761 if (dev_priv->uncore.fw_rendercount == 0) \
762 fwengine = FORCEWAKE_RENDER; \
763 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
764 if (dev_priv->uncore.fw_mediacount == 0) \
765 fwengine = FORCEWAKE_MEDIA; \
766 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
767 if (dev_priv->uncore.fw_rendercount == 0) \
768 fwengine |= FORCEWAKE_RENDER; \
769 if (dev_priv->uncore.fw_mediacount == 0) \
770 fwengine |= FORCEWAKE_MEDIA; \
771 } \
772 } \
773 if (fwengine) \
774 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
775 __raw_i915_write##x(dev_priv, reg, val); \
776 if (fwengine) \
777 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
778 REG_WRITE_FOOTER; \
779 }
780
781 __chv_write(8)
782 __chv_write(16)
783 __chv_write(32)
784 __chv_write(64)
785 __gen8_write(8)
786 __gen8_write(16)
787 __gen8_write(32)
788 __gen8_write(64)
789 __hsw_write(8)
790 __hsw_write(16)
791 __hsw_write(32)
792 __hsw_write(64)
793 __gen6_write(8)
794 __gen6_write(16)
795 __gen6_write(32)
796 __gen6_write(64)
797 __gen5_write(8)
798 __gen5_write(16)
799 __gen5_write(32)
800 __gen5_write(64)
801 __gen4_write(8)
802 __gen4_write(16)
803 __gen4_write(32)
804 __gen4_write(64)
805
806 #undef __chv_write
807 #undef __gen8_write
808 #undef __hsw_write
809 #undef __gen6_write
810 #undef __gen5_write
811 #undef __gen4_write
812 #undef REG_WRITE_FOOTER
813 #undef REG_WRITE_HEADER
814
815 void intel_uncore_init(struct drm_device *dev)
816 {
817 struct drm_i915_private *dev_priv = dev->dev_private;
818
819 setup_timer(&dev_priv->uncore.force_wake_timer,
820 gen6_force_wake_timer, (unsigned long)dev_priv);
821
822 intel_uncore_early_sanitize(dev);
823
824 if (IS_VALLEYVIEW(dev)) {
825 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
826 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
827 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
828 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
829 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
830 } else if (IS_IVYBRIDGE(dev)) {
831 u32 ecobus;
832
833 /* IVB configs may use multi-threaded forcewake */
834
835 /* A small trick here - if the bios hasn't configured
836 * MT forcewake, and if the device is in RC6, then
837 * force_wake_mt_get will not wake the device and the
838 * ECOBUS read will return zero. Which will be
839 * (correctly) interpreted by the test below as MT
840 * forcewake being disabled.
841 */
842 mutex_lock(&dev->struct_mutex);
843 __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
844 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
845 __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
846 mutex_unlock(&dev->struct_mutex);
847
848 if (ecobus & FORCEWAKE_MT_ENABLE) {
849 dev_priv->uncore.funcs.force_wake_get =
850 __gen7_gt_force_wake_mt_get;
851 dev_priv->uncore.funcs.force_wake_put =
852 __gen7_gt_force_wake_mt_put;
853 } else {
854 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
855 DRM_INFO("when using vblank-synced partial screen updates.\n");
856 dev_priv->uncore.funcs.force_wake_get =
857 __gen6_gt_force_wake_get;
858 dev_priv->uncore.funcs.force_wake_put =
859 __gen6_gt_force_wake_put;
860 }
861 } else if (IS_GEN6(dev)) {
862 dev_priv->uncore.funcs.force_wake_get =
863 __gen6_gt_force_wake_get;
864 dev_priv->uncore.funcs.force_wake_put =
865 __gen6_gt_force_wake_put;
866 }
867
868 switch (INTEL_INFO(dev)->gen) {
869 default:
870 if (IS_CHERRYVIEW(dev)) {
871 dev_priv->uncore.funcs.mmio_writeb = chv_write8;
872 dev_priv->uncore.funcs.mmio_writew = chv_write16;
873 dev_priv->uncore.funcs.mmio_writel = chv_write32;
874 dev_priv->uncore.funcs.mmio_writeq = chv_write64;
875 dev_priv->uncore.funcs.mmio_readb = chv_read8;
876 dev_priv->uncore.funcs.mmio_readw = chv_read16;
877 dev_priv->uncore.funcs.mmio_readl = chv_read32;
878 dev_priv->uncore.funcs.mmio_readq = chv_read64;
879
880 } else {
881 dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
882 dev_priv->uncore.funcs.mmio_writew = gen8_write16;
883 dev_priv->uncore.funcs.mmio_writel = gen8_write32;
884 dev_priv->uncore.funcs.mmio_writeq = gen8_write64;
885 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
886 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
887 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
888 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
889 }
890 break;
891 case 7:
892 case 6:
893 if (IS_HASWELL(dev)) {
894 dev_priv->uncore.funcs.mmio_writeb = hsw_write8;
895 dev_priv->uncore.funcs.mmio_writew = hsw_write16;
896 dev_priv->uncore.funcs.mmio_writel = hsw_write32;
897 dev_priv->uncore.funcs.mmio_writeq = hsw_write64;
898 } else {
899 dev_priv->uncore.funcs.mmio_writeb = gen6_write8;
900 dev_priv->uncore.funcs.mmio_writew = gen6_write16;
901 dev_priv->uncore.funcs.mmio_writel = gen6_write32;
902 dev_priv->uncore.funcs.mmio_writeq = gen6_write64;
903 }
904
905 if (IS_VALLEYVIEW(dev)) {
906 dev_priv->uncore.funcs.mmio_readb = vlv_read8;
907 dev_priv->uncore.funcs.mmio_readw = vlv_read16;
908 dev_priv->uncore.funcs.mmio_readl = vlv_read32;
909 dev_priv->uncore.funcs.mmio_readq = vlv_read64;
910 } else {
911 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
912 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
913 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
914 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
915 }
916 break;
917 case 5:
918 dev_priv->uncore.funcs.mmio_writeb = gen5_write8;
919 dev_priv->uncore.funcs.mmio_writew = gen5_write16;
920 dev_priv->uncore.funcs.mmio_writel = gen5_write32;
921 dev_priv->uncore.funcs.mmio_writeq = gen5_write64;
922 dev_priv->uncore.funcs.mmio_readb = gen5_read8;
923 dev_priv->uncore.funcs.mmio_readw = gen5_read16;
924 dev_priv->uncore.funcs.mmio_readl = gen5_read32;
925 dev_priv->uncore.funcs.mmio_readq = gen5_read64;
926 break;
927 case 4:
928 case 3:
929 case 2:
930 dev_priv->uncore.funcs.mmio_writeb = gen4_write8;
931 dev_priv->uncore.funcs.mmio_writew = gen4_write16;
932 dev_priv->uncore.funcs.mmio_writel = gen4_write32;
933 dev_priv->uncore.funcs.mmio_writeq = gen4_write64;
934 dev_priv->uncore.funcs.mmio_readb = gen4_read8;
935 dev_priv->uncore.funcs.mmio_readw = gen4_read16;
936 dev_priv->uncore.funcs.mmio_readl = gen4_read32;
937 dev_priv->uncore.funcs.mmio_readq = gen4_read64;
938 break;
939 }
940 }
941
942 void intel_uncore_fini(struct drm_device *dev)
943 {
944 /* Paranoia: make sure we have disabled everything before we exit. */
945 intel_uncore_sanitize(dev);
946 intel_uncore_forcewake_reset(dev, false);
947 }
948
949 #define GEN_RANGE(l, h) GENMASK(h, l)
950
951 static const struct register_whitelist {
952 uint64_t offset;
953 uint32_t size;
954 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
955 uint32_t gen_bitmask;
956 } whitelist[] = {
957 { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 8) },
958 };
959
960 int i915_reg_read_ioctl(struct drm_device *dev,
961 void *data, struct drm_file *file)
962 {
963 struct drm_i915_private *dev_priv = dev->dev_private;
964 struct drm_i915_reg_read *reg = data;
965 struct register_whitelist const *entry = whitelist;
966 int i, ret = 0;
967
968 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
969 if (entry->offset == reg->offset &&
970 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
971 break;
972 }
973
974 if (i == ARRAY_SIZE(whitelist))
975 return -EINVAL;
976
977 intel_runtime_pm_get(dev_priv);
978
979 switch (entry->size) {
980 case 8:
981 reg->val = I915_READ64(reg->offset);
982 break;
983 case 4:
984 reg->val = I915_READ(reg->offset);
985 break;
986 case 2:
987 reg->val = I915_READ16(reg->offset);
988 break;
989 case 1:
990 reg->val = I915_READ8(reg->offset);
991 break;
992 default:
993 WARN_ON(1);
994 ret = -EINVAL;
995 goto out;
996 }
997
998 out:
999 intel_runtime_pm_put(dev_priv);
1000 return ret;
1001 }
1002
1003 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1004 void *data, struct drm_file *file)
1005 {
1006 struct drm_i915_private *dev_priv = dev->dev_private;
1007 struct drm_i915_reset_stats *args = data;
1008 struct i915_ctx_hang_stats *hs;
1009 struct intel_context *ctx;
1010 int ret;
1011
1012 if (args->flags || args->pad)
1013 return -EINVAL;
1014
1015 if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN))
1016 return -EPERM;
1017
1018 ret = mutex_lock_interruptible(&dev->struct_mutex);
1019 if (ret)
1020 return ret;
1021
1022 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1023 if (IS_ERR(ctx)) {
1024 mutex_unlock(&dev->struct_mutex);
1025 return PTR_ERR(ctx);
1026 }
1027 hs = &ctx->hang_stats;
1028
1029 if (capable(CAP_SYS_ADMIN))
1030 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1031 else
1032 args->reset_count = 0;
1033
1034 args->batch_active = hs->batch_active;
1035 args->batch_pending = hs->batch_pending;
1036
1037 mutex_unlock(&dev->struct_mutex);
1038
1039 return 0;
1040 }
1041
1042 static int i965_reset_complete(struct drm_device *dev)
1043 {
1044 u8 gdrst;
1045 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
1046 return (gdrst & GRDOM_RESET_ENABLE) == 0;
1047 }
1048
1049 static int i965_do_reset(struct drm_device *dev)
1050 {
1051 int ret;
1052
1053 /* FIXME: i965g/gm need a display save/restore for gpu reset. */
1054 return -ENODEV;
1055
1056 /*
1057 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
1058 * well as the reset bit (GR/bit 0). Setting the GR bit
1059 * triggers the reset; when done, the hardware will clear it.
1060 */
1061 pci_write_config_byte(dev->pdev, I965_GDRST,
1062 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1063 ret = wait_for(i965_reset_complete(dev), 500);
1064 if (ret)
1065 return ret;
1066
1067 pci_write_config_byte(dev->pdev, I965_GDRST,
1068 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1069
1070 ret = wait_for(i965_reset_complete(dev), 500);
1071 if (ret)
1072 return ret;
1073
1074 pci_write_config_byte(dev->pdev, I965_GDRST, 0);
1075
1076 return 0;
1077 }
1078
1079 static int g4x_do_reset(struct drm_device *dev)
1080 {
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082 int ret;
1083
1084 pci_write_config_byte(dev->pdev, I965_GDRST,
1085 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1086 ret = wait_for(i965_reset_complete(dev), 500);
1087 if (ret)
1088 return ret;
1089
1090 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1091 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1092 POSTING_READ(VDECCLK_GATE_D);
1093
1094 pci_write_config_byte(dev->pdev, I965_GDRST,
1095 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1096 ret = wait_for(i965_reset_complete(dev), 500);
1097 if (ret)
1098 return ret;
1099
1100 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1101 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1102 POSTING_READ(VDECCLK_GATE_D);
1103
1104 pci_write_config_byte(dev->pdev, I965_GDRST, 0);
1105
1106 return 0;
1107 }
1108
1109 static int ironlake_do_reset(struct drm_device *dev)
1110 {
1111 struct drm_i915_private *dev_priv = dev->dev_private;
1112 int ret;
1113
1114 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1115 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1116 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1117 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1118 if (ret)
1119 return ret;
1120
1121 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1122 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1123 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1124 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1125 if (ret)
1126 return ret;
1127
1128 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1129
1130 return 0;
1131 }
1132
1133 static int gen6_do_reset(struct drm_device *dev)
1134 {
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 int ret;
1137
1138 /* Reset the chip */
1139
1140 /* GEN6_GDRST is not in the gt power well, no need to check
1141 * for fifo space for the write or forcewake the chip for
1142 * the read
1143 */
1144 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1145
1146 /* Spin waiting for the device to ack the reset request */
1147 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1148
1149 intel_uncore_forcewake_reset(dev, true);
1150
1151 return ret;
1152 }
1153
1154 int intel_gpu_reset(struct drm_device *dev)
1155 {
1156 switch (INTEL_INFO(dev)->gen) {
1157 case 8:
1158 case 7:
1159 case 6: return gen6_do_reset(dev);
1160 case 5: return ironlake_do_reset(dev);
1161 case 4:
1162 if (IS_G4X(dev))
1163 return g4x_do_reset(dev);
1164 else
1165 return i965_do_reset(dev);
1166 default: return -ENODEV;
1167 }
1168 }
1169
1170 void intel_uncore_check_errors(struct drm_device *dev)
1171 {
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173
1174 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1175 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1176 DRM_ERROR("Unclaimed register before interrupt\n");
1177 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1178 }
1179 }
Linux kernel - Deliverables
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