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drm/i915: Report all GTFIFODBG errors
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_uncore.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "i915_drv.h"
25 #include "intel_drv.h"
26
27 #define FORCEWAKE_ACK_TIMEOUT_MS 2
28
29 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
31
32 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
34
35 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
37
38 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
40
41 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
42
43
44 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
45 {
46 u32 gt_thread_status_mask;
47
48 if (IS_HASWELL(dev_priv->dev))
49 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
50 else
51 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
52
53 /* w/a for a sporadic read returning 0 by waiting for the GT
54 * thread to wake up.
55 */
56 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
57 DRM_ERROR("GT thread status wait timed out\n");
58 }
59
60 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
61 {
62 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
63 /* something from same cacheline, but !FORCEWAKE */
64 __raw_posting_read(dev_priv, ECOBUS);
65 }
66
67 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
68 int fw_engine)
69 {
70 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
71 FORCEWAKE_ACK_TIMEOUT_MS))
72 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
73
74 __raw_i915_write32(dev_priv, FORCEWAKE, 1);
75 /* something from same cacheline, but !FORCEWAKE */
76 __raw_posting_read(dev_priv, ECOBUS);
77
78 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
79 FORCEWAKE_ACK_TIMEOUT_MS))
80 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
81
82 /* WaRsForcewakeWaitTC0:snb */
83 __gen6_gt_wait_for_thread_c0(dev_priv);
84 }
85
86 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
87 {
88 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
89 /* something from same cacheline, but !FORCEWAKE_MT */
90 __raw_posting_read(dev_priv, ECOBUS);
91 }
92
93 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
94 int fw_engine)
95 {
96 u32 forcewake_ack;
97
98 if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
99 forcewake_ack = FORCEWAKE_ACK_HSW;
100 else
101 forcewake_ack = FORCEWAKE_MT_ACK;
102
103 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
104 FORCEWAKE_ACK_TIMEOUT_MS))
105 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
106
107 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
108 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
109 /* something from same cacheline, but !FORCEWAKE_MT */
110 __raw_posting_read(dev_priv, ECOBUS);
111
112 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
113 FORCEWAKE_ACK_TIMEOUT_MS))
114 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
115
116 /* WaRsForcewakeWaitTC0:ivb,hsw */
117 if (INTEL_INFO(dev_priv->dev)->gen < 8)
118 __gen6_gt_wait_for_thread_c0(dev_priv);
119 }
120
121 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
122 {
123 u32 gtfifodbg;
124
125 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
126 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
127 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
128 }
129
130 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
131 int fw_engine)
132 {
133 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
134 /* something from same cacheline, but !FORCEWAKE */
135 __raw_posting_read(dev_priv, ECOBUS);
136 gen6_gt_check_fifodbg(dev_priv);
137 }
138
139 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
140 int fw_engine)
141 {
142 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
143 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
144 /* something from same cacheline, but !FORCEWAKE_MT */
145 __raw_posting_read(dev_priv, ECOBUS);
146 gen6_gt_check_fifodbg(dev_priv);
147 }
148
149 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
150 {
151 int ret = 0;
152
153 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
154 int loop = 500;
155 u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
156 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
157 udelay(10);
158 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
159 }
160 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
161 ++ret;
162 dev_priv->uncore.fifo_count = fifo;
163 }
164 dev_priv->uncore.fifo_count--;
165
166 return ret;
167 }
168
169 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
170 {
171 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
172 _MASKED_BIT_DISABLE(0xffff));
173 /* something from same cacheline, but !FORCEWAKE_VLV */
174 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
175 }
176
177 static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
178 int fw_engine)
179 {
180 /* Check for Render Engine */
181 if (FORCEWAKE_RENDER & fw_engine) {
182 if (wait_for_atomic((__raw_i915_read32(dev_priv,
183 FORCEWAKE_ACK_VLV) &
184 FORCEWAKE_KERNEL) == 0,
185 FORCEWAKE_ACK_TIMEOUT_MS))
186 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
187
188 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
189 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
190
191 if (wait_for_atomic((__raw_i915_read32(dev_priv,
192 FORCEWAKE_ACK_VLV) &
193 FORCEWAKE_KERNEL),
194 FORCEWAKE_ACK_TIMEOUT_MS))
195 DRM_ERROR("Timed out: waiting for Render to ack.\n");
196 }
197
198 /* Check for Media Engine */
199 if (FORCEWAKE_MEDIA & fw_engine) {
200 if (wait_for_atomic((__raw_i915_read32(dev_priv,
201 FORCEWAKE_ACK_MEDIA_VLV) &
202 FORCEWAKE_KERNEL) == 0,
203 FORCEWAKE_ACK_TIMEOUT_MS))
204 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
205
206 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
207 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
208
209 if (wait_for_atomic((__raw_i915_read32(dev_priv,
210 FORCEWAKE_ACK_MEDIA_VLV) &
211 FORCEWAKE_KERNEL),
212 FORCEWAKE_ACK_TIMEOUT_MS))
213 DRM_ERROR("Timed out: waiting for media to ack.\n");
214 }
215
216 /* WaRsForcewakeWaitTC0:vlv */
217 __gen6_gt_wait_for_thread_c0(dev_priv);
218
219 }
220
221 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
222 int fw_engine)
223 {
224
225 /* Check for Render Engine */
226 if (FORCEWAKE_RENDER & fw_engine)
227 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
228 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
229
230
231 /* Check for Media Engine */
232 if (FORCEWAKE_MEDIA & fw_engine)
233 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
234 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
235
236 /* The below doubles as a POSTING_READ */
237 gen6_gt_check_fifodbg(dev_priv);
238
239 }
240
241 void vlv_force_wake_get(struct drm_i915_private *dev_priv,
242 int fw_engine)
243 {
244 unsigned long irqflags;
245
246 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
247 if (FORCEWAKE_RENDER & fw_engine) {
248 if (dev_priv->uncore.fw_rendercount++ == 0)
249 dev_priv->uncore.funcs.force_wake_get(dev_priv,
250 FORCEWAKE_RENDER);
251 }
252 if (FORCEWAKE_MEDIA & fw_engine) {
253 if (dev_priv->uncore.fw_mediacount++ == 0)
254 dev_priv->uncore.funcs.force_wake_get(dev_priv,
255 FORCEWAKE_MEDIA);
256 }
257
258 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
259 }
260
261 void vlv_force_wake_put(struct drm_i915_private *dev_priv,
262 int fw_engine)
263 {
264 unsigned long irqflags;
265
266 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
267
268 if (FORCEWAKE_RENDER & fw_engine) {
269 WARN_ON(dev_priv->uncore.fw_rendercount == 0);
270 if (--dev_priv->uncore.fw_rendercount == 0)
271 dev_priv->uncore.funcs.force_wake_put(dev_priv,
272 FORCEWAKE_RENDER);
273 }
274
275 if (FORCEWAKE_MEDIA & fw_engine) {
276 WARN_ON(dev_priv->uncore.fw_mediacount == 0);
277 if (--dev_priv->uncore.fw_mediacount == 0)
278 dev_priv->uncore.funcs.force_wake_put(dev_priv,
279 FORCEWAKE_MEDIA);
280 }
281
282 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
283 }
284
285 static void gen6_force_wake_work(struct work_struct *work)
286 {
287 struct drm_i915_private *dev_priv =
288 container_of(work, typeof(*dev_priv), uncore.force_wake_work.work);
289 unsigned long irqflags;
290
291 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
292 if (--dev_priv->uncore.forcewake_count == 0)
293 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
294 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
295 }
296
297 void intel_uncore_early_sanitize(struct drm_device *dev)
298 {
299 struct drm_i915_private *dev_priv = dev->dev_private;
300
301 if (HAS_FPGA_DBG_UNCLAIMED(dev))
302 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
303
304 if (IS_HASWELL(dev) &&
305 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
306 /* The docs do not explain exactly how the calculation can be
307 * made. It is somewhat guessable, but for now, it's always
308 * 128MB.
309 * NB: We can't write IDICR yet because we do not have gt funcs
310 * set up */
311 dev_priv->ellc_size = 128;
312 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
313 }
314 }
315
316 static void intel_uncore_forcewake_reset(struct drm_device *dev)
317 {
318 struct drm_i915_private *dev_priv = dev->dev_private;
319
320 if (IS_VALLEYVIEW(dev)) {
321 vlv_force_wake_reset(dev_priv);
322 } else if (INTEL_INFO(dev)->gen >= 6) {
323 __gen6_gt_force_wake_reset(dev_priv);
324 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
325 __gen6_gt_force_wake_mt_reset(dev_priv);
326 }
327 }
328
329 void intel_uncore_sanitize(struct drm_device *dev)
330 {
331 struct drm_i915_private *dev_priv = dev->dev_private;
332 u32 reg_val;
333
334 intel_uncore_forcewake_reset(dev);
335
336 /* BIOS often leaves RC6 enabled, but disable it for hw init */
337 intel_disable_gt_powersave(dev);
338
339 /* Turn off power gate, require especially for the BIOS less system */
340 if (IS_VALLEYVIEW(dev)) {
341
342 mutex_lock(&dev_priv->rps.hw_lock);
343 reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
344
345 if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT))
346 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
347
348 mutex_unlock(&dev_priv->rps.hw_lock);
349
350 }
351 }
352
353 /*
354 * Generally this is called implicitly by the register read function. However,
355 * if some sequence requires the GT to not power down then this function should
356 * be called at the beginning of the sequence followed by a call to
357 * gen6_gt_force_wake_put() at the end of the sequence.
358 */
359 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
360 {
361 unsigned long irqflags;
362
363 if (!dev_priv->uncore.funcs.force_wake_get)
364 return;
365
366 /* Redirect to VLV specific routine */
367 if (IS_VALLEYVIEW(dev_priv->dev))
368 return vlv_force_wake_get(dev_priv, fw_engine);
369
370 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
371 if (dev_priv->uncore.forcewake_count++ == 0)
372 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
373 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
374 }
375
376 /*
377 * see gen6_gt_force_wake_get()
378 */
379 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
380 {
381 unsigned long irqflags;
382
383 if (!dev_priv->uncore.funcs.force_wake_put)
384 return;
385
386 /* Redirect to VLV specific routine */
387 if (IS_VALLEYVIEW(dev_priv->dev))
388 return vlv_force_wake_put(dev_priv, fw_engine);
389
390
391 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
392 if (--dev_priv->uncore.forcewake_count == 0) {
393 dev_priv->uncore.forcewake_count++;
394 mod_delayed_work(dev_priv->wq,
395 &dev_priv->uncore.force_wake_work,
396 1);
397 }
398 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
399 }
400
401 /* We give fast paths for the really cool registers */
402 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
403 ((reg) < 0x40000 && (reg) != FORCEWAKE)
404
405 static void
406 ilk_dummy_write(struct drm_i915_private *dev_priv)
407 {
408 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
409 * the chip from rc6 before touching it for real. MI_MODE is masked,
410 * hence harmless to write 0 into. */
411 __raw_i915_write32(dev_priv, MI_MODE, 0);
412 }
413
414 static void
415 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
416 {
417 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
418 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
419 reg);
420 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
421 }
422 }
423
424 static void
425 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
426 {
427 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
428 DRM_ERROR("Unclaimed write to %x\n", reg);
429 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
430 }
431 }
432
433 #define REG_READ_HEADER(x) \
434 unsigned long irqflags; \
435 u##x val = 0; \
436 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
437
438 #define REG_READ_FOOTER \
439 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
440 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
441 return val
442
443 #define __gen4_read(x) \
444 static u##x \
445 gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
446 REG_READ_HEADER(x); \
447 val = __raw_i915_read##x(dev_priv, reg); \
448 REG_READ_FOOTER; \
449 }
450
451 #define __gen5_read(x) \
452 static u##x \
453 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
454 REG_READ_HEADER(x); \
455 ilk_dummy_write(dev_priv); \
456 val = __raw_i915_read##x(dev_priv, reg); \
457 REG_READ_FOOTER; \
458 }
459
460 #define __gen6_read(x) \
461 static u##x \
462 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
463 REG_READ_HEADER(x); \
464 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
465 if (dev_priv->uncore.forcewake_count == 0) \
466 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
467 FORCEWAKE_ALL); \
468 val = __raw_i915_read##x(dev_priv, reg); \
469 if (dev_priv->uncore.forcewake_count == 0) \
470 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
471 FORCEWAKE_ALL); \
472 } else { \
473 val = __raw_i915_read##x(dev_priv, reg); \
474 } \
475 REG_READ_FOOTER; \
476 }
477
478 #define __vlv_read(x) \
479 static u##x \
480 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
481 unsigned fwengine = 0; \
482 unsigned *fwcount = 0; \
483 REG_READ_HEADER(x); \
484 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
485 fwengine = FORCEWAKE_RENDER; \
486 fwcount = &dev_priv->uncore.fw_rendercount; \
487 } \
488 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
489 fwengine = FORCEWAKE_MEDIA; \
490 fwcount = &dev_priv->uncore.fw_mediacount; \
491 } \
492 if (fwengine != 0) { \
493 if ((*fwcount)++ == 0) \
494 (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
495 fwengine); \
496 val = __raw_i915_read##x(dev_priv, reg); \
497 if (--(*fwcount) == 0) \
498 (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
499 FORCEWAKE_ALL); \
500 } else { \
501 val = __raw_i915_read##x(dev_priv, reg); \
502 } \
503 REG_READ_FOOTER; \
504 }
505
506
507 __vlv_read(8)
508 __vlv_read(16)
509 __vlv_read(32)
510 __vlv_read(64)
511 __gen6_read(8)
512 __gen6_read(16)
513 __gen6_read(32)
514 __gen6_read(64)
515 __gen5_read(8)
516 __gen5_read(16)
517 __gen5_read(32)
518 __gen5_read(64)
519 __gen4_read(8)
520 __gen4_read(16)
521 __gen4_read(32)
522 __gen4_read(64)
523
524 #undef __vlv_read
525 #undef __gen6_read
526 #undef __gen5_read
527 #undef __gen4_read
528 #undef REG_READ_FOOTER
529 #undef REG_READ_HEADER
530
531 #define REG_WRITE_HEADER \
532 unsigned long irqflags; \
533 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
534 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
535
536 #define __gen4_write(x) \
537 static void \
538 gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
539 REG_WRITE_HEADER; \
540 __raw_i915_write##x(dev_priv, reg, val); \
541 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
542 }
543
544 #define __gen5_write(x) \
545 static void \
546 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
547 REG_WRITE_HEADER; \
548 ilk_dummy_write(dev_priv); \
549 __raw_i915_write##x(dev_priv, reg, val); \
550 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
551 }
552
553 #define __gen6_write(x) \
554 static void \
555 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
556 u32 __fifo_ret = 0; \
557 REG_WRITE_HEADER; \
558 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
559 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
560 } \
561 __raw_i915_write##x(dev_priv, reg, val); \
562 if (unlikely(__fifo_ret)) { \
563 gen6_gt_check_fifodbg(dev_priv); \
564 } \
565 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
566 }
567
568 #define __hsw_write(x) \
569 static void \
570 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
571 u32 __fifo_ret = 0; \
572 REG_WRITE_HEADER; \
573 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
574 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
575 } \
576 hsw_unclaimed_reg_clear(dev_priv, reg); \
577 __raw_i915_write##x(dev_priv, reg, val); \
578 if (unlikely(__fifo_ret)) { \
579 gen6_gt_check_fifodbg(dev_priv); \
580 } \
581 hsw_unclaimed_reg_check(dev_priv, reg); \
582 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
583 }
584
585 static const u32 gen8_shadowed_regs[] = {
586 FORCEWAKE_MT,
587 GEN6_RPNSWREQ,
588 GEN6_RC_VIDEO_FREQ,
589 RING_TAIL(RENDER_RING_BASE),
590 RING_TAIL(GEN6_BSD_RING_BASE),
591 RING_TAIL(VEBOX_RING_BASE),
592 RING_TAIL(BLT_RING_BASE),
593 /* TODO: Other registers are not yet used */
594 };
595
596 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
597 {
598 int i;
599 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
600 if (reg == gen8_shadowed_regs[i])
601 return true;
602
603 return false;
604 }
605
606 #define __gen8_write(x) \
607 static void \
608 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
609 bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
610 REG_WRITE_HEADER; \
611 if (__needs_put) { \
612 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
613 FORCEWAKE_ALL); \
614 } \
615 __raw_i915_write##x(dev_priv, reg, val); \
616 if (__needs_put) { \
617 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
618 FORCEWAKE_ALL); \
619 } \
620 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
621 }
622
623 __gen8_write(8)
624 __gen8_write(16)
625 __gen8_write(32)
626 __gen8_write(64)
627 __hsw_write(8)
628 __hsw_write(16)
629 __hsw_write(32)
630 __hsw_write(64)
631 __gen6_write(8)
632 __gen6_write(16)
633 __gen6_write(32)
634 __gen6_write(64)
635 __gen5_write(8)
636 __gen5_write(16)
637 __gen5_write(32)
638 __gen5_write(64)
639 __gen4_write(8)
640 __gen4_write(16)
641 __gen4_write(32)
642 __gen4_write(64)
643
644 #undef __gen8_write
645 #undef __hsw_write
646 #undef __gen6_write
647 #undef __gen5_write
648 #undef __gen4_write
649 #undef REG_WRITE_HEADER
650
651 void intel_uncore_init(struct drm_device *dev)
652 {
653 struct drm_i915_private *dev_priv = dev->dev_private;
654
655 INIT_DELAYED_WORK(&dev_priv->uncore.force_wake_work,
656 gen6_force_wake_work);
657
658 if (IS_VALLEYVIEW(dev)) {
659 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
660 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
661 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
662 dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get;
663 dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put;
664 } else if (IS_IVYBRIDGE(dev)) {
665 u32 ecobus;
666
667 /* IVB configs may use multi-threaded forcewake */
668
669 /* A small trick here - if the bios hasn't configured
670 * MT forcewake, and if the device is in RC6, then
671 * force_wake_mt_get will not wake the device and the
672 * ECOBUS read will return zero. Which will be
673 * (correctly) interpreted by the test below as MT
674 * forcewake being disabled.
675 */
676 mutex_lock(&dev->struct_mutex);
677 __gen6_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
678 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
679 __gen6_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
680 mutex_unlock(&dev->struct_mutex);
681
682 if (ecobus & FORCEWAKE_MT_ENABLE) {
683 dev_priv->uncore.funcs.force_wake_get =
684 __gen6_gt_force_wake_mt_get;
685 dev_priv->uncore.funcs.force_wake_put =
686 __gen6_gt_force_wake_mt_put;
687 } else {
688 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
689 DRM_INFO("when using vblank-synced partial screen updates.\n");
690 dev_priv->uncore.funcs.force_wake_get =
691 __gen6_gt_force_wake_get;
692 dev_priv->uncore.funcs.force_wake_put =
693 __gen6_gt_force_wake_put;
694 }
695 } else if (IS_GEN6(dev)) {
696 dev_priv->uncore.funcs.force_wake_get =
697 __gen6_gt_force_wake_get;
698 dev_priv->uncore.funcs.force_wake_put =
699 __gen6_gt_force_wake_put;
700 }
701
702 switch (INTEL_INFO(dev)->gen) {
703 default:
704 dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
705 dev_priv->uncore.funcs.mmio_writew = gen8_write16;
706 dev_priv->uncore.funcs.mmio_writel = gen8_write32;
707 dev_priv->uncore.funcs.mmio_writeq = gen8_write64;
708 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
709 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
710 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
711 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
712 break;
713 case 7:
714 case 6:
715 if (IS_HASWELL(dev)) {
716 dev_priv->uncore.funcs.mmio_writeb = hsw_write8;
717 dev_priv->uncore.funcs.mmio_writew = hsw_write16;
718 dev_priv->uncore.funcs.mmio_writel = hsw_write32;
719 dev_priv->uncore.funcs.mmio_writeq = hsw_write64;
720 } else {
721 dev_priv->uncore.funcs.mmio_writeb = gen6_write8;
722 dev_priv->uncore.funcs.mmio_writew = gen6_write16;
723 dev_priv->uncore.funcs.mmio_writel = gen6_write32;
724 dev_priv->uncore.funcs.mmio_writeq = gen6_write64;
725 }
726
727 if (IS_VALLEYVIEW(dev)) {
728 dev_priv->uncore.funcs.mmio_readb = vlv_read8;
729 dev_priv->uncore.funcs.mmio_readw = vlv_read16;
730 dev_priv->uncore.funcs.mmio_readl = vlv_read32;
731 dev_priv->uncore.funcs.mmio_readq = vlv_read64;
732 } else {
733 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
734 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
735 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
736 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
737 }
738 break;
739 case 5:
740 dev_priv->uncore.funcs.mmio_writeb = gen5_write8;
741 dev_priv->uncore.funcs.mmio_writew = gen5_write16;
742 dev_priv->uncore.funcs.mmio_writel = gen5_write32;
743 dev_priv->uncore.funcs.mmio_writeq = gen5_write64;
744 dev_priv->uncore.funcs.mmio_readb = gen5_read8;
745 dev_priv->uncore.funcs.mmio_readw = gen5_read16;
746 dev_priv->uncore.funcs.mmio_readl = gen5_read32;
747 dev_priv->uncore.funcs.mmio_readq = gen5_read64;
748 break;
749 case 4:
750 case 3:
751 case 2:
752 dev_priv->uncore.funcs.mmio_writeb = gen4_write8;
753 dev_priv->uncore.funcs.mmio_writew = gen4_write16;
754 dev_priv->uncore.funcs.mmio_writel = gen4_write32;
755 dev_priv->uncore.funcs.mmio_writeq = gen4_write64;
756 dev_priv->uncore.funcs.mmio_readb = gen4_read8;
757 dev_priv->uncore.funcs.mmio_readw = gen4_read16;
758 dev_priv->uncore.funcs.mmio_readl = gen4_read32;
759 dev_priv->uncore.funcs.mmio_readq = gen4_read64;
760 break;
761 }
762 }
763
764 void intel_uncore_fini(struct drm_device *dev)
765 {
766 struct drm_i915_private *dev_priv = dev->dev_private;
767
768 flush_delayed_work(&dev_priv->uncore.force_wake_work);
769
770 /* Paranoia: make sure we have disabled everything before we exit. */
771 intel_uncore_sanitize(dev);
772 }
773
774 static const struct register_whitelist {
775 uint64_t offset;
776 uint32_t size;
777 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
778 } whitelist[] = {
779 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
780 };
781
782 int i915_reg_read_ioctl(struct drm_device *dev,
783 void *data, struct drm_file *file)
784 {
785 struct drm_i915_private *dev_priv = dev->dev_private;
786 struct drm_i915_reg_read *reg = data;
787 struct register_whitelist const *entry = whitelist;
788 int i;
789
790 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
791 if (entry->offset == reg->offset &&
792 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
793 break;
794 }
795
796 if (i == ARRAY_SIZE(whitelist))
797 return -EINVAL;
798
799 switch (entry->size) {
800 case 8:
801 reg->val = I915_READ64(reg->offset);
802 break;
803 case 4:
804 reg->val = I915_READ(reg->offset);
805 break;
806 case 2:
807 reg->val = I915_READ16(reg->offset);
808 break;
809 case 1:
810 reg->val = I915_READ8(reg->offset);
811 break;
812 default:
813 WARN_ON(1);
814 return -EINVAL;
815 }
816
817 return 0;
818 }
819
820 int i915_get_reset_stats_ioctl(struct drm_device *dev,
821 void *data, struct drm_file *file)
822 {
823 struct drm_i915_private *dev_priv = dev->dev_private;
824 struct drm_i915_reset_stats *args = data;
825 struct i915_ctx_hang_stats *hs;
826 int ret;
827
828 if (args->flags || args->pad)
829 return -EINVAL;
830
831 if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN))
832 return -EPERM;
833
834 ret = mutex_lock_interruptible(&dev->struct_mutex);
835 if (ret)
836 return ret;
837
838 hs = i915_gem_context_get_hang_stats(dev, file, args->ctx_id);
839 if (IS_ERR(hs)) {
840 mutex_unlock(&dev->struct_mutex);
841 return PTR_ERR(hs);
842 }
843
844 if (capable(CAP_SYS_ADMIN))
845 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
846 else
847 args->reset_count = 0;
848
849 args->batch_active = hs->batch_active;
850 args->batch_pending = hs->batch_pending;
851
852 mutex_unlock(&dev->struct_mutex);
853
854 return 0;
855 }
856
857 static int i965_reset_complete(struct drm_device *dev)
858 {
859 u8 gdrst;
860 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
861 return (gdrst & GRDOM_RESET_ENABLE) == 0;
862 }
863
864 static int i965_do_reset(struct drm_device *dev)
865 {
866 int ret;
867
868 /*
869 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
870 * well as the reset bit (GR/bit 0). Setting the GR bit
871 * triggers the reset; when done, the hardware will clear it.
872 */
873 pci_write_config_byte(dev->pdev, I965_GDRST,
874 GRDOM_RENDER | GRDOM_RESET_ENABLE);
875 ret = wait_for(i965_reset_complete(dev), 500);
876 if (ret)
877 return ret;
878
879 /* We can't reset render&media without also resetting display ... */
880 pci_write_config_byte(dev->pdev, I965_GDRST,
881 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
882
883 ret = wait_for(i965_reset_complete(dev), 500);
884 if (ret)
885 return ret;
886
887 pci_write_config_byte(dev->pdev, I965_GDRST, 0);
888
889 return 0;
890 }
891
892 static int ironlake_do_reset(struct drm_device *dev)
893 {
894 struct drm_i915_private *dev_priv = dev->dev_private;
895 u32 gdrst;
896 int ret;
897
898 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
899 gdrst &= ~GRDOM_MASK;
900 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
901 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
902 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
903 if (ret)
904 return ret;
905
906 /* We can't reset render&media without also resetting display ... */
907 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
908 gdrst &= ~GRDOM_MASK;
909 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
910 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
911 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
912 }
913
914 static int gen6_do_reset(struct drm_device *dev)
915 {
916 struct drm_i915_private *dev_priv = dev->dev_private;
917 int ret;
918 unsigned long irqflags;
919
920 /* Hold uncore.lock across reset to prevent any register access
921 * with forcewake not set correctly
922 */
923 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
924
925 /* Reset the chip */
926
927 /* GEN6_GDRST is not in the gt power well, no need to check
928 * for fifo space for the write or forcewake the chip for
929 * the read
930 */
931 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
932
933 /* Spin waiting for the device to ack the reset request */
934 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
935
936 intel_uncore_forcewake_reset(dev);
937
938 /* If reset with a user forcewake, try to restore, otherwise turn it off */
939 if (dev_priv->uncore.forcewake_count)
940 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
941 else
942 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
943
944 /* Restore fifo count */
945 dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
946
947 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
948 return ret;
949 }
950
951 int intel_gpu_reset(struct drm_device *dev)
952 {
953 switch (INTEL_INFO(dev)->gen) {
954 case 8:
955 case 7:
956 case 6: return gen6_do_reset(dev);
957 case 5: return ironlake_do_reset(dev);
958 case 4: return i965_do_reset(dev);
959 default: return -ENODEV;
960 }
961 }
962
963 void intel_uncore_check_errors(struct drm_device *dev)
964 {
965 struct drm_i915_private *dev_priv = dev->dev_private;
966
967 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
968 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
969 DRM_ERROR("Unclaimed register before interrupt\n");
970 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
971 }
972 }
Linux kernel - Deliverables
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