2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
27 #define FORCEWAKE_ACK_TIMEOUT_MS 2
29 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
32 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
35 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
38 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
41 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
44 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private
*dev_priv
)
46 u32 gt_thread_status_mask
;
48 if (IS_HASWELL(dev_priv
->dev
))
49 gt_thread_status_mask
= GEN6_GT_THREAD_STATUS_CORE_MASK_HSW
;
51 gt_thread_status_mask
= GEN6_GT_THREAD_STATUS_CORE_MASK
;
53 /* w/a for a sporadic read returning 0 by waiting for the GT
56 if (wait_for_atomic_us((__raw_i915_read32(dev_priv
, GEN6_GT_THREAD_STATUS_REG
) & gt_thread_status_mask
) == 0, 500))
57 DRM_ERROR("GT thread status wait timed out\n");
60 static void __gen6_gt_force_wake_reset(struct drm_i915_private
*dev_priv
)
62 __raw_i915_write32(dev_priv
, FORCEWAKE
, 0);
63 /* something from same cacheline, but !FORCEWAKE */
64 __raw_posting_read(dev_priv
, ECOBUS
);
67 static void __gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
,
70 if (wait_for_atomic((__raw_i915_read32(dev_priv
, FORCEWAKE_ACK
) & 1) == 0,
71 FORCEWAKE_ACK_TIMEOUT_MS
))
72 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
74 __raw_i915_write32(dev_priv
, FORCEWAKE
, 1);
75 /* something from same cacheline, but !FORCEWAKE */
76 __raw_posting_read(dev_priv
, ECOBUS
);
78 if (wait_for_atomic((__raw_i915_read32(dev_priv
, FORCEWAKE_ACK
) & 1),
79 FORCEWAKE_ACK_TIMEOUT_MS
))
80 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
82 /* WaRsForcewakeWaitTC0:snb */
83 __gen6_gt_wait_for_thread_c0(dev_priv
);
86 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private
*dev_priv
)
88 __raw_i915_write32(dev_priv
, FORCEWAKE_MT
, _MASKED_BIT_DISABLE(0xffff));
89 /* something from same cacheline, but !FORCEWAKE_MT */
90 __raw_posting_read(dev_priv
, ECOBUS
);
93 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private
*dev_priv
,
98 if (IS_HASWELL(dev_priv
->dev
) || IS_GEN8(dev_priv
->dev
))
99 forcewake_ack
= FORCEWAKE_ACK_HSW
;
101 forcewake_ack
= FORCEWAKE_MT_ACK
;
103 if (wait_for_atomic((__raw_i915_read32(dev_priv
, forcewake_ack
) & FORCEWAKE_KERNEL
) == 0,
104 FORCEWAKE_ACK_TIMEOUT_MS
))
105 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
107 __raw_i915_write32(dev_priv
, FORCEWAKE_MT
,
108 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
109 /* something from same cacheline, but !FORCEWAKE_MT */
110 __raw_posting_read(dev_priv
, ECOBUS
);
112 if (wait_for_atomic((__raw_i915_read32(dev_priv
, forcewake_ack
) & FORCEWAKE_KERNEL
),
113 FORCEWAKE_ACK_TIMEOUT_MS
))
114 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
116 /* WaRsForcewakeWaitTC0:ivb,hsw */
117 if (INTEL_INFO(dev_priv
->dev
)->gen
< 8)
118 __gen6_gt_wait_for_thread_c0(dev_priv
);
121 static void gen6_gt_check_fifodbg(struct drm_i915_private
*dev_priv
)
125 gtfifodbg
= __raw_i915_read32(dev_priv
, GTFIFODBG
);
126 if (WARN(gtfifodbg
, "GT wake FIFO error 0x%x\n", gtfifodbg
))
127 __raw_i915_write32(dev_priv
, GTFIFODBG
, gtfifodbg
);
130 static void __gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
,
133 __raw_i915_write32(dev_priv
, FORCEWAKE
, 0);
134 /* something from same cacheline, but !FORCEWAKE */
135 __raw_posting_read(dev_priv
, ECOBUS
);
136 gen6_gt_check_fifodbg(dev_priv
);
139 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private
*dev_priv
,
142 __raw_i915_write32(dev_priv
, FORCEWAKE_MT
,
143 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
144 /* something from same cacheline, but !FORCEWAKE_MT */
145 __raw_posting_read(dev_priv
, ECOBUS
);
146 gen6_gt_check_fifodbg(dev_priv
);
149 static int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
153 /* On VLV, FIFO will be shared by both SW and HW.
154 * So, we need to read the FREE_ENTRIES everytime */
155 if (IS_VALLEYVIEW(dev_priv
->dev
))
156 dev_priv
->uncore
.fifo_count
=
157 __raw_i915_read32(dev_priv
, GTFIFOCTL
) &
158 GT_FIFO_FREE_ENTRIES_MASK
;
160 if (dev_priv
->uncore
.fifo_count
< GT_FIFO_NUM_RESERVED_ENTRIES
) {
162 u32 fifo
= __raw_i915_read32(dev_priv
, GTFIFOCTL
) & GT_FIFO_FREE_ENTRIES_MASK
;
163 while (fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
&& loop
--) {
165 fifo
= __raw_i915_read32(dev_priv
, GTFIFOCTL
) & GT_FIFO_FREE_ENTRIES_MASK
;
167 if (WARN_ON(loop
< 0 && fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
))
169 dev_priv
->uncore
.fifo_count
= fifo
;
171 dev_priv
->uncore
.fifo_count
--;
176 static void vlv_force_wake_reset(struct drm_i915_private
*dev_priv
)
178 __raw_i915_write32(dev_priv
, FORCEWAKE_VLV
,
179 _MASKED_BIT_DISABLE(0xffff));
180 /* something from same cacheline, but !FORCEWAKE_VLV */
181 __raw_posting_read(dev_priv
, FORCEWAKE_ACK_VLV
);
184 static void __vlv_force_wake_get(struct drm_i915_private
*dev_priv
,
187 /* Check for Render Engine */
188 if (FORCEWAKE_RENDER
& fw_engine
) {
189 if (wait_for_atomic((__raw_i915_read32(dev_priv
,
191 FORCEWAKE_KERNEL
) == 0,
192 FORCEWAKE_ACK_TIMEOUT_MS
))
193 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
195 __raw_i915_write32(dev_priv
, FORCEWAKE_VLV
,
196 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
198 if (wait_for_atomic((__raw_i915_read32(dev_priv
,
201 FORCEWAKE_ACK_TIMEOUT_MS
))
202 DRM_ERROR("Timed out: waiting for Render to ack.\n");
205 /* Check for Media Engine */
206 if (FORCEWAKE_MEDIA
& fw_engine
) {
207 if (wait_for_atomic((__raw_i915_read32(dev_priv
,
208 FORCEWAKE_ACK_MEDIA_VLV
) &
209 FORCEWAKE_KERNEL
) == 0,
210 FORCEWAKE_ACK_TIMEOUT_MS
))
211 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
213 __raw_i915_write32(dev_priv
, FORCEWAKE_MEDIA_VLV
,
214 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
216 if (wait_for_atomic((__raw_i915_read32(dev_priv
,
217 FORCEWAKE_ACK_MEDIA_VLV
) &
219 FORCEWAKE_ACK_TIMEOUT_MS
))
220 DRM_ERROR("Timed out: waiting for media to ack.\n");
223 /* WaRsForcewakeWaitTC0:vlv */
224 __gen6_gt_wait_for_thread_c0(dev_priv
);
228 static void __vlv_force_wake_put(struct drm_i915_private
*dev_priv
,
232 /* Check for Render Engine */
233 if (FORCEWAKE_RENDER
& fw_engine
)
234 __raw_i915_write32(dev_priv
, FORCEWAKE_VLV
,
235 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
238 /* Check for Media Engine */
239 if (FORCEWAKE_MEDIA
& fw_engine
)
240 __raw_i915_write32(dev_priv
, FORCEWAKE_MEDIA_VLV
,
241 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
243 /* The below doubles as a POSTING_READ */
244 gen6_gt_check_fifodbg(dev_priv
);
248 void vlv_force_wake_get(struct drm_i915_private
*dev_priv
,
251 unsigned long irqflags
;
253 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
254 if (FORCEWAKE_RENDER
& fw_engine
) {
255 if (dev_priv
->uncore
.fw_rendercount
++ == 0)
256 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
,
259 if (FORCEWAKE_MEDIA
& fw_engine
) {
260 if (dev_priv
->uncore
.fw_mediacount
++ == 0)
261 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
,
265 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
268 void vlv_force_wake_put(struct drm_i915_private
*dev_priv
,
271 unsigned long irqflags
;
273 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
275 if (FORCEWAKE_RENDER
& fw_engine
) {
276 WARN_ON(dev_priv
->uncore
.fw_rendercount
== 0);
277 if (--dev_priv
->uncore
.fw_rendercount
== 0)
278 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
,
282 if (FORCEWAKE_MEDIA
& fw_engine
) {
283 WARN_ON(dev_priv
->uncore
.fw_mediacount
== 0);
284 if (--dev_priv
->uncore
.fw_mediacount
== 0)
285 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
,
289 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
292 static void gen6_force_wake_work(struct work_struct
*work
)
294 struct drm_i915_private
*dev_priv
=
295 container_of(work
, typeof(*dev_priv
), uncore
.force_wake_work
.work
);
296 unsigned long irqflags
;
298 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
299 if (--dev_priv
->uncore
.forcewake_count
== 0)
300 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
301 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
304 static void intel_uncore_forcewake_reset(struct drm_device
*dev
)
306 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
308 if (IS_VALLEYVIEW(dev
)) {
309 vlv_force_wake_reset(dev_priv
);
310 } else if (INTEL_INFO(dev
)->gen
>= 6) {
311 __gen6_gt_force_wake_reset(dev_priv
);
312 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
313 __gen6_gt_force_wake_mt_reset(dev_priv
);
317 void intel_uncore_early_sanitize(struct drm_device
*dev
)
319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
321 if (HAS_FPGA_DBG_UNCLAIMED(dev
))
322 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
324 if (IS_HASWELL(dev
) &&
325 (__raw_i915_read32(dev_priv
, HSW_EDRAM_PRESENT
) == 1)) {
326 /* The docs do not explain exactly how the calculation can be
327 * made. It is somewhat guessable, but for now, it's always
329 * NB: We can't write IDICR yet because we do not have gt funcs
331 dev_priv
->ellc_size
= 128;
332 DRM_INFO("Found %zuMB of eLLC\n", dev_priv
->ellc_size
);
335 intel_uncore_forcewake_reset(dev
);
338 void intel_uncore_sanitize(struct drm_device
*dev
)
340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
343 /* BIOS often leaves RC6 enabled, but disable it for hw init */
344 intel_disable_gt_powersave(dev
);
346 /* Turn off power gate, require especially for the BIOS less system */
347 if (IS_VALLEYVIEW(dev
)) {
349 mutex_lock(&dev_priv
->rps
.hw_lock
);
350 reg_val
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_STATUS
);
352 if (reg_val
& (RENDER_PWRGT
| MEDIA_PWRGT
| DISP2D_PWRGT
))
353 vlv_punit_write(dev_priv
, PUNIT_REG_PWRGT_CTRL
, 0x0);
355 mutex_unlock(&dev_priv
->rps
.hw_lock
);
361 * Generally this is called implicitly by the register read function. However,
362 * if some sequence requires the GT to not power down then this function should
363 * be called at the beginning of the sequence followed by a call to
364 * gen6_gt_force_wake_put() at the end of the sequence.
366 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
)
368 unsigned long irqflags
;
370 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
373 /* Redirect to VLV specific routine */
374 if (IS_VALLEYVIEW(dev_priv
->dev
))
375 return vlv_force_wake_get(dev_priv
, fw_engine
);
377 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
378 if (dev_priv
->uncore
.forcewake_count
++ == 0)
379 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
380 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
384 * see gen6_gt_force_wake_get()
386 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
)
388 unsigned long irqflags
;
390 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
393 /* Redirect to VLV specific routine */
394 if (IS_VALLEYVIEW(dev_priv
->dev
))
395 return vlv_force_wake_put(dev_priv
, fw_engine
);
398 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
399 if (--dev_priv
->uncore
.forcewake_count
== 0) {
400 dev_priv
->uncore
.forcewake_count
++;
401 mod_delayed_work(dev_priv
->wq
,
402 &dev_priv
->uncore
.force_wake_work
,
405 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
408 /* We give fast paths for the really cool registers */
409 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
410 ((reg) < 0x40000 && (reg) != FORCEWAKE)
413 ilk_dummy_write(struct drm_i915_private
*dev_priv
)
415 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
416 * the chip from rc6 before touching it for real. MI_MODE is masked,
417 * hence harmless to write 0 into. */
418 __raw_i915_write32(dev_priv
, MI_MODE
, 0);
422 hsw_unclaimed_reg_clear(struct drm_i915_private
*dev_priv
, u32 reg
)
424 if (__raw_i915_read32(dev_priv
, FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
) {
425 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
427 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
432 hsw_unclaimed_reg_check(struct drm_i915_private
*dev_priv
, u32 reg
)
434 if (__raw_i915_read32(dev_priv
, FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
) {
435 DRM_ERROR("Unclaimed write to %x\n", reg
);
436 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
440 #define REG_READ_HEADER(x) \
441 unsigned long irqflags; \
443 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
445 #define REG_READ_FOOTER \
446 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
447 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
450 #define __gen4_read(x) \
452 gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
453 REG_READ_HEADER(x); \
454 val = __raw_i915_read##x(dev_priv, reg); \
458 #define __gen5_read(x) \
460 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
461 REG_READ_HEADER(x); \
462 ilk_dummy_write(dev_priv); \
463 val = __raw_i915_read##x(dev_priv, reg); \
467 #define __gen6_read(x) \
469 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
470 REG_READ_HEADER(x); \
471 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
472 if (dev_priv->uncore.forcewake_count == 0) \
473 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
475 val = __raw_i915_read##x(dev_priv, reg); \
476 if (dev_priv->uncore.forcewake_count == 0) \
477 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
480 val = __raw_i915_read##x(dev_priv, reg); \
485 #define __vlv_read(x) \
487 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
488 unsigned fwengine = 0; \
490 REG_READ_HEADER(x); \
491 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
492 fwengine = FORCEWAKE_RENDER; \
493 fwcount = &dev_priv->uncore.fw_rendercount; \
495 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
496 fwengine = FORCEWAKE_MEDIA; \
497 fwcount = &dev_priv->uncore.fw_mediacount; \
499 if (fwengine != 0) { \
500 if ((*fwcount)++ == 0) \
501 (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
503 val = __raw_i915_read##x(dev_priv, reg); \
504 if (--(*fwcount) == 0) \
505 (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
508 val = __raw_i915_read##x(dev_priv, reg); \
535 #undef REG_READ_FOOTER
536 #undef REG_READ_HEADER
538 #define REG_WRITE_HEADER \
539 unsigned long irqflags; \
540 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
541 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
543 #define REG_WRITE_FOOTER \
544 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
546 #define __gen4_write(x) \
548 gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
550 __raw_i915_write##x(dev_priv, reg, val); \
554 #define __gen5_write(x) \
556 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
558 ilk_dummy_write(dev_priv); \
559 __raw_i915_write##x(dev_priv, reg, val); \
563 #define __gen6_write(x) \
565 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
566 u32 __fifo_ret = 0; \
568 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
569 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
571 __raw_i915_write##x(dev_priv, reg, val); \
572 if (unlikely(__fifo_ret)) { \
573 gen6_gt_check_fifodbg(dev_priv); \
578 #define __hsw_write(x) \
580 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
581 u32 __fifo_ret = 0; \
583 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
584 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
586 hsw_unclaimed_reg_clear(dev_priv, reg); \
587 __raw_i915_write##x(dev_priv, reg, val); \
588 if (unlikely(__fifo_ret)) { \
589 gen6_gt_check_fifodbg(dev_priv); \
591 hsw_unclaimed_reg_check(dev_priv, reg); \
595 static const u32 gen8_shadowed_regs
[] = {
599 RING_TAIL(RENDER_RING_BASE
),
600 RING_TAIL(GEN6_BSD_RING_BASE
),
601 RING_TAIL(VEBOX_RING_BASE
),
602 RING_TAIL(BLT_RING_BASE
),
603 /* TODO: Other registers are not yet used */
606 static bool is_gen8_shadowed(struct drm_i915_private
*dev_priv
, u32 reg
)
609 for (i
= 0; i
< ARRAY_SIZE(gen8_shadowed_regs
); i
++)
610 if (reg
== gen8_shadowed_regs
[i
])
616 #define __gen8_write(x) \
618 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
619 bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
622 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
625 __raw_i915_write##x(dev_priv, reg, val); \
627 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
659 #undef REG_WRITE_FOOTER
660 #undef REG_WRITE_HEADER
662 void intel_uncore_init(struct drm_device
*dev
)
664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
666 INIT_DELAYED_WORK(&dev_priv
->uncore
.force_wake_work
,
667 gen6_force_wake_work
);
669 if (IS_VALLEYVIEW(dev
)) {
670 dev_priv
->uncore
.funcs
.force_wake_get
= __vlv_force_wake_get
;
671 dev_priv
->uncore
.funcs
.force_wake_put
= __vlv_force_wake_put
;
672 } else if (IS_HASWELL(dev
) || IS_GEN8(dev
)) {
673 dev_priv
->uncore
.funcs
.force_wake_get
= __gen6_gt_force_wake_mt_get
;
674 dev_priv
->uncore
.funcs
.force_wake_put
= __gen6_gt_force_wake_mt_put
;
675 } else if (IS_IVYBRIDGE(dev
)) {
678 /* IVB configs may use multi-threaded forcewake */
680 /* A small trick here - if the bios hasn't configured
681 * MT forcewake, and if the device is in RC6, then
682 * force_wake_mt_get will not wake the device and the
683 * ECOBUS read will return zero. Which will be
684 * (correctly) interpreted by the test below as MT
685 * forcewake being disabled.
687 mutex_lock(&dev
->struct_mutex
);
688 __gen6_gt_force_wake_mt_get(dev_priv
, FORCEWAKE_ALL
);
689 ecobus
= __raw_i915_read32(dev_priv
, ECOBUS
);
690 __gen6_gt_force_wake_mt_put(dev_priv
, FORCEWAKE_ALL
);
691 mutex_unlock(&dev
->struct_mutex
);
693 if (ecobus
& FORCEWAKE_MT_ENABLE
) {
694 dev_priv
->uncore
.funcs
.force_wake_get
=
695 __gen6_gt_force_wake_mt_get
;
696 dev_priv
->uncore
.funcs
.force_wake_put
=
697 __gen6_gt_force_wake_mt_put
;
699 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
700 DRM_INFO("when using vblank-synced partial screen updates.\n");
701 dev_priv
->uncore
.funcs
.force_wake_get
=
702 __gen6_gt_force_wake_get
;
703 dev_priv
->uncore
.funcs
.force_wake_put
=
704 __gen6_gt_force_wake_put
;
706 } else if (IS_GEN6(dev
)) {
707 dev_priv
->uncore
.funcs
.force_wake_get
=
708 __gen6_gt_force_wake_get
;
709 dev_priv
->uncore
.funcs
.force_wake_put
=
710 __gen6_gt_force_wake_put
;
713 switch (INTEL_INFO(dev
)->gen
) {
715 dev_priv
->uncore
.funcs
.mmio_writeb
= gen8_write8
;
716 dev_priv
->uncore
.funcs
.mmio_writew
= gen8_write16
;
717 dev_priv
->uncore
.funcs
.mmio_writel
= gen8_write32
;
718 dev_priv
->uncore
.funcs
.mmio_writeq
= gen8_write64
;
719 dev_priv
->uncore
.funcs
.mmio_readb
= gen6_read8
;
720 dev_priv
->uncore
.funcs
.mmio_readw
= gen6_read16
;
721 dev_priv
->uncore
.funcs
.mmio_readl
= gen6_read32
;
722 dev_priv
->uncore
.funcs
.mmio_readq
= gen6_read64
;
726 if (IS_HASWELL(dev
)) {
727 dev_priv
->uncore
.funcs
.mmio_writeb
= hsw_write8
;
728 dev_priv
->uncore
.funcs
.mmio_writew
= hsw_write16
;
729 dev_priv
->uncore
.funcs
.mmio_writel
= hsw_write32
;
730 dev_priv
->uncore
.funcs
.mmio_writeq
= hsw_write64
;
732 dev_priv
->uncore
.funcs
.mmio_writeb
= gen6_write8
;
733 dev_priv
->uncore
.funcs
.mmio_writew
= gen6_write16
;
734 dev_priv
->uncore
.funcs
.mmio_writel
= gen6_write32
;
735 dev_priv
->uncore
.funcs
.mmio_writeq
= gen6_write64
;
738 if (IS_VALLEYVIEW(dev
)) {
739 dev_priv
->uncore
.funcs
.mmio_readb
= vlv_read8
;
740 dev_priv
->uncore
.funcs
.mmio_readw
= vlv_read16
;
741 dev_priv
->uncore
.funcs
.mmio_readl
= vlv_read32
;
742 dev_priv
->uncore
.funcs
.mmio_readq
= vlv_read64
;
744 dev_priv
->uncore
.funcs
.mmio_readb
= gen6_read8
;
745 dev_priv
->uncore
.funcs
.mmio_readw
= gen6_read16
;
746 dev_priv
->uncore
.funcs
.mmio_readl
= gen6_read32
;
747 dev_priv
->uncore
.funcs
.mmio_readq
= gen6_read64
;
751 dev_priv
->uncore
.funcs
.mmio_writeb
= gen5_write8
;
752 dev_priv
->uncore
.funcs
.mmio_writew
= gen5_write16
;
753 dev_priv
->uncore
.funcs
.mmio_writel
= gen5_write32
;
754 dev_priv
->uncore
.funcs
.mmio_writeq
= gen5_write64
;
755 dev_priv
->uncore
.funcs
.mmio_readb
= gen5_read8
;
756 dev_priv
->uncore
.funcs
.mmio_readw
= gen5_read16
;
757 dev_priv
->uncore
.funcs
.mmio_readl
= gen5_read32
;
758 dev_priv
->uncore
.funcs
.mmio_readq
= gen5_read64
;
763 dev_priv
->uncore
.funcs
.mmio_writeb
= gen4_write8
;
764 dev_priv
->uncore
.funcs
.mmio_writew
= gen4_write16
;
765 dev_priv
->uncore
.funcs
.mmio_writel
= gen4_write32
;
766 dev_priv
->uncore
.funcs
.mmio_writeq
= gen4_write64
;
767 dev_priv
->uncore
.funcs
.mmio_readb
= gen4_read8
;
768 dev_priv
->uncore
.funcs
.mmio_readw
= gen4_read16
;
769 dev_priv
->uncore
.funcs
.mmio_readl
= gen4_read32
;
770 dev_priv
->uncore
.funcs
.mmio_readq
= gen4_read64
;
775 void intel_uncore_fini(struct drm_device
*dev
)
777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
779 flush_delayed_work(&dev_priv
->uncore
.force_wake_work
);
781 /* Paranoia: make sure we have disabled everything before we exit. */
782 intel_uncore_sanitize(dev
);
785 static const struct register_whitelist
{
788 uint32_t gen_bitmask
; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
790 { RING_TIMESTAMP(RENDER_RING_BASE
), 8, 0xF0 },
793 int i915_reg_read_ioctl(struct drm_device
*dev
,
794 void *data
, struct drm_file
*file
)
796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
797 struct drm_i915_reg_read
*reg
= data
;
798 struct register_whitelist
const *entry
= whitelist
;
801 for (i
= 0; i
< ARRAY_SIZE(whitelist
); i
++, entry
++) {
802 if (entry
->offset
== reg
->offset
&&
803 (1 << INTEL_INFO(dev
)->gen
& entry
->gen_bitmask
))
807 if (i
== ARRAY_SIZE(whitelist
))
810 switch (entry
->size
) {
812 reg
->val
= I915_READ64(reg
->offset
);
815 reg
->val
= I915_READ(reg
->offset
);
818 reg
->val
= I915_READ16(reg
->offset
);
821 reg
->val
= I915_READ8(reg
->offset
);
831 int i915_get_reset_stats_ioctl(struct drm_device
*dev
,
832 void *data
, struct drm_file
*file
)
834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
835 struct drm_i915_reset_stats
*args
= data
;
836 struct i915_ctx_hang_stats
*hs
;
839 if (args
->flags
|| args
->pad
)
842 if (args
->ctx_id
== DEFAULT_CONTEXT_ID
&& !capable(CAP_SYS_ADMIN
))
845 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
849 hs
= i915_gem_context_get_hang_stats(dev
, file
, args
->ctx_id
);
851 mutex_unlock(&dev
->struct_mutex
);
855 if (capable(CAP_SYS_ADMIN
))
856 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
858 args
->reset_count
= 0;
860 args
->batch_active
= hs
->batch_active
;
861 args
->batch_pending
= hs
->batch_pending
;
863 mutex_unlock(&dev
->struct_mutex
);
868 static int i965_reset_complete(struct drm_device
*dev
)
871 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
872 return (gdrst
& GRDOM_RESET_ENABLE
) == 0;
875 static int i965_do_reset(struct drm_device
*dev
)
880 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
881 * well as the reset bit (GR/bit 0). Setting the GR bit
882 * triggers the reset; when done, the hardware will clear it.
884 pci_write_config_byte(dev
->pdev
, I965_GDRST
,
885 GRDOM_RENDER
| GRDOM_RESET_ENABLE
);
886 ret
= wait_for(i965_reset_complete(dev
), 500);
890 /* We can't reset render&media without also resetting display ... */
891 pci_write_config_byte(dev
->pdev
, I965_GDRST
,
892 GRDOM_MEDIA
| GRDOM_RESET_ENABLE
);
894 ret
= wait_for(i965_reset_complete(dev
), 500);
898 pci_write_config_byte(dev
->pdev
, I965_GDRST
, 0);
903 static int ironlake_do_reset(struct drm_device
*dev
)
905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
909 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
910 gdrst
&= ~GRDOM_MASK
;
911 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
,
912 gdrst
| GRDOM_RENDER
| GRDOM_RESET_ENABLE
);
913 ret
= wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
917 /* We can't reset render&media without also resetting display ... */
918 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
919 gdrst
&= ~GRDOM_MASK
;
920 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
,
921 gdrst
| GRDOM_MEDIA
| GRDOM_RESET_ENABLE
);
922 return wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
925 static int gen6_do_reset(struct drm_device
*dev
)
927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
929 unsigned long irqflags
;
931 /* Hold uncore.lock across reset to prevent any register access
932 * with forcewake not set correctly
934 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
938 /* GEN6_GDRST is not in the gt power well, no need to check
939 * for fifo space for the write or forcewake the chip for
942 __raw_i915_write32(dev_priv
, GEN6_GDRST
, GEN6_GRDOM_FULL
);
944 /* Spin waiting for the device to ack the reset request */
945 ret
= wait_for((__raw_i915_read32(dev_priv
, GEN6_GDRST
) & GEN6_GRDOM_FULL
) == 0, 500);
947 intel_uncore_forcewake_reset(dev
);
949 /* If reset with a user forcewake, try to restore, otherwise turn it off */
950 if (dev_priv
->uncore
.forcewake_count
)
951 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
953 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
955 /* Restore fifo count */
956 dev_priv
->uncore
.fifo_count
= __raw_i915_read32(dev_priv
, GTFIFOCTL
) & GT_FIFO_FREE_ENTRIES_MASK
;
958 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
962 int intel_gpu_reset(struct drm_device
*dev
)
964 switch (INTEL_INFO(dev
)->gen
) {
967 case 6: return gen6_do_reset(dev
);
968 case 5: return ironlake_do_reset(dev
);
969 case 4: return i965_do_reset(dev
);
970 default: return -ENODEV
;
974 void intel_uncore_check_errors(struct drm_device
*dev
)
976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
978 if (HAS_FPGA_DBG_UNCLAIMED(dev
) &&
979 (__raw_i915_read32(dev_priv
, FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
980 DRM_ERROR("Unclaimed register before interrupt\n");
981 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);