drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26
  27 #include <linux/pm_runtime.h>
  28
  29 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  30
  31 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
  32 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
  33
  34 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
  35 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
  36
  37 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  38 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
  39
  40 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
  41 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
  42
  43 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  44
  45 static const char * const forcewake_domain_names[] = {
  46         "render",
  47         "blitter",
  48         "media",
  49 };
  50
  51 const char *
  52 intel_uncore_forcewake_domain_to_str(const int id)
  53 {
  54         BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) !=
  55                      FW_DOMAIN_ID_COUNT);
  56
  57         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  58                 return forcewake_domain_names[id];
  59
  60         WARN_ON(id);
  61
  62         return "unknown";
  63 }
  64
  65 static void
  66 assert_device_not_suspended(struct drm_i915_private *dev_priv)
  67 {
  68         WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
  69                   "Device suspended\n");
  70 }
  71
  72 static inline void
  73 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  74 {
  75         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  76 }
  77
  78 static inline void
  79 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  80 {
  81         mod_timer_pinned(&d->timer, jiffies + 1);
  82 }
  83
  84 static inline void
  85 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  86 {
  87         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  88                              FORCEWAKE_KERNEL) == 0,
  89                             FORCEWAKE_ACK_TIMEOUT_MS))
  90                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  91                           intel_uncore_forcewake_domain_to_str(d->id));
  92 }
  93
  94 static inline void
  95 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  96 {
  97         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  98 }
  99
 100 static inline void
 101 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
 102 {
 103         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
 104                              FORCEWAKE_KERNEL),
 105                             FORCEWAKE_ACK_TIMEOUT_MS))
 106                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 107                           intel_uncore_forcewake_domain_to_str(d->id));
 108 }
 109
 110 static inline void
 111 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 112 {
 113         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 114 }
 115
 116 static inline void
 117 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 118 {
 119         /* something from same cacheline, but not from the set register */
 120         if (d->reg_post)
 121                 __raw_posting_read(d->i915, d->reg_post);
 122 }
 123
 124 static void
 125 fw_domains_get(struct drm_i915_private *dev_priv, int fw_domains)
 126 {
 127         struct intel_uncore_forcewake_domain *d;
 128         int id;
 129
 130         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 131                 fw_domain_wait_ack_clear(d);
 132                 fw_domain_get(d);
 133                 fw_domain_posting_read(d);
 134                 fw_domain_wait_ack(d);
 135         }
 136 }
 137
 138 static void
 139 fw_domains_put(struct drm_i915_private *dev_priv, int fw_domains)
 140 {
 141         struct intel_uncore_forcewake_domain *d;
 142         int id;
 143
 144         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 145                 fw_domain_put(d);
 146                 fw_domain_posting_read(d);
 147         }
 148 }
 149
 150 static void
 151 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 152 {
 153         struct intel_uncore_forcewake_domain *d;
 154         int id;
 155
 156         /* No need to do for all, just do for first found */
 157         for_each_fw_domain(d, dev_priv, id) {
 158                 fw_domain_posting_read(d);
 159                 break;
 160         }
 161 }
 162
 163 static void
 164 fw_domains_reset(struct drm_i915_private *dev_priv, const unsigned fw_domains)
 165 {
 166         struct intel_uncore_forcewake_domain *d;
 167         int id;
 168
 169         for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
 170                 fw_domain_reset(d);
 171
 172         fw_domains_posting_read(dev_priv);
 173 }
 174
 175 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 176 {
 177         /* w/a for a sporadic read returning 0 by waiting for the GT
 178          * thread to wake up.
 179          */
 180         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 181                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 182                 DRM_ERROR("GT thread status wait timed out\n");
 183 }
 184
 185 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 186                                               int fw_domains)
 187 {
 188         fw_domains_get(dev_priv, fw_domains);
 189
 190         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 191         __gen6_gt_wait_for_thread_c0(dev_priv);
 192 }
 193
 194 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 195 {
 196         u32 gtfifodbg;
 197
 198         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 199         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 200                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 201 }
 202
 203 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 204                                      int fw_domains)
 205 {
 206         fw_domains_put(dev_priv, fw_domains);
 207         gen6_gt_check_fifodbg(dev_priv);
 208 }
 209
 210 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 211 {
 212         int ret = 0;
 213
 214         /* On VLV, FIFO will be shared by both SW and HW.
 215          * So, we need to read the FREE_ENTRIES everytime */
 216         if (IS_VALLEYVIEW(dev_priv->dev))
 217                 dev_priv->uncore.fifo_count =
 218                         __raw_i915_read32(dev_priv, GTFIFOCTL) &
 219                                                 GT_FIFO_FREE_ENTRIES_MASK;
 220
 221         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 222                 int loop = 500;
 223                 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 224                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 225                         udelay(10);
 226                         fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 227                 }
 228                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 229                         ++ret;
 230                 dev_priv->uncore.fifo_count = fifo;
 231         }
 232         dev_priv->uncore.fifo_count--;
 233
 234         return ret;
 235 }
 236
 237 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
 238                                  int fw_engine)
 239 {
 240         fw_domains_put(dev_priv, fw_engine);
 241         fw_domains_posting_read(dev_priv);
 242
 243         if (!IS_CHERRYVIEW(dev_priv->dev))
 244                 gen6_gt_check_fifodbg(dev_priv);
 245 }
 246
 247 static void gen6_force_wake_timer(unsigned long arg)
 248 {
 249         struct intel_uncore_forcewake_domain *domain = (void *)arg;
 250         unsigned long irqflags;
 251
 252         assert_device_not_suspended(domain->i915);
 253
 254         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 255         if (WARN_ON(domain->wake_count == 0))
 256                 domain->wake_count++;
 257
 258         if (--domain->wake_count == 0)
 259                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 260                                                           1 << domain->id);
 261
 262         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 263 }
 264
 265 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 266 {
 267         struct drm_i915_private *dev_priv = dev->dev_private;
 268         unsigned long irqflags, fw = 0;
 269         struct intel_uncore_forcewake_domain *domain;
 270         int id, active_domains, retry_count = 100;
 271
 272         /* Hold uncore.lock across reset to prevent any register access
 273          * with forcewake not set correctly. Wait until all pending
 274          * timers are run before holding.
 275          */
 276         while (1) {
 277                 active_domains = 0;
 278
 279                 for_each_fw_domain(domain, dev_priv, id) {
 280                         if (del_timer_sync(&domain->timer) == 0)
 281                                 continue;
 282
 283                         gen6_force_wake_timer((unsigned long)domain);
 284                 }
 285
 286                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 287
 288                 for_each_fw_domain(domain, dev_priv, id) {
 289                         if (timer_pending(&domain->timer))
 290                                 active_domains |= (1 << id);
 291                 }
 292
 293                 if (active_domains == 0)
 294                         break;
 295
 296                 if (--retry_count == 0) {
 297                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 298                         break;
 299                 }
 300
 301                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 302                 cond_resched();
 303         }
 304
 305         WARN_ON(active_domains);
 306
 307         for_each_fw_domain(domain, dev_priv, id)
 308                 if (domain->wake_count)
 309                         fw |= 1 << id;
 310
 311         if (fw)
 312                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 313
 314         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 315
 316         if (restore) { /* If reset with a user forcewake, try to restore */
 317                 if (fw)
 318                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 319
 320                 if (IS_GEN6(dev) || IS_GEN7(dev))
 321                         dev_priv->uncore.fifo_count =
 322                                 __raw_i915_read32(dev_priv, GTFIFOCTL) &
 323                                 GT_FIFO_FREE_ENTRIES_MASK;
 324         }
 325
 326         if (!restore)
 327                 assert_force_wake_inactive(dev_priv);
 328
 329         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 330 }
 331
 332 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 333                                           bool restore_forcewake)
 334 {
 335         struct drm_i915_private *dev_priv = dev->dev_private;
 336
 337         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 338                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 339
 340         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
 341             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
 342                 /* The docs do not explain exactly how the calculation can be
 343                  * made. It is somewhat guessable, but for now, it's always
 344                  * 128MB.
 345                  * NB: We can't write IDICR yet because we do not have gt funcs
 346                  * set up */
 347                 dev_priv->ellc_size = 128;
 348                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 349         }
 350
 351         /* clear out old GT FIFO errors */
 352         if (IS_GEN6(dev) || IS_GEN7(dev))
 353                 __raw_i915_write32(dev_priv, GTFIFODBG,
 354                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 355
 356         intel_uncore_forcewake_reset(dev, restore_forcewake);
 357 }
 358
 359 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 360 {
 361         __intel_uncore_early_sanitize(dev, restore_forcewake);
 362         i915_check_and_clear_faults(dev);
 363 }
 364
 365 void intel_uncore_sanitize(struct drm_device *dev)
 366 {
 367         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 368         intel_disable_gt_powersave(dev);
 369 }
 370
 371 /*
 372  * Generally this is called implicitly by the register read function. However,
 373  * if some sequence requires the GT to not power down then this function should
 374  * be called at the beginning of the sequence followed by a call to
 375  * gen6_gt_force_wake_put() at the end of the sequence.
 376  */
 377 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
 378                             unsigned fw_domains)
 379 {
 380         unsigned long irqflags;
 381         struct intel_uncore_forcewake_domain *domain;
 382         int id;
 383
 384         if (!dev_priv->uncore.funcs.force_wake_get)
 385                 return;
 386
 387         WARN_ON(dev_priv->pm.suspended);
 388
 389         fw_domains &= dev_priv->uncore.fw_domains;
 390
 391         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 392
 393         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 394                 if (domain->wake_count++)
 395                         fw_domains &= ~(1 << id);
 396         }
 397
 398         if (fw_domains)
 399                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 400
 401         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 402 }
 403
 404 /*
 405  * see gen6_gt_force_wake_get()
 406  */
 407 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
 408                             unsigned fw_domains)
 409 {
 410         unsigned long irqflags;
 411         struct intel_uncore_forcewake_domain *domain;
 412         int id;
 413
 414         if (!dev_priv->uncore.funcs.force_wake_put)
 415                 return;
 416
 417         fw_domains &= dev_priv->uncore.fw_domains;
 418
 419         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 420
 421         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 422                 if (WARN_ON(domain->wake_count == 0))
 423                         continue;
 424
 425                 if (--domain->wake_count)
 426                         continue;
 427
 428                 domain->wake_count++;
 429                 fw_domain_arm_timer(domain);
 430         }
 431
 432         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 433 }
 434
 435 void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
 436 {
 437         struct intel_uncore_forcewake_domain *domain;
 438         int id;
 439
 440         if (!dev_priv->uncore.funcs.force_wake_get)
 441                 return;
 442
 443         for_each_fw_domain(domain, dev_priv, id)
 444                 WARN_ON(domain->wake_count);
 445 }
 446
 447 /* We give fast paths for the really cool registers */
 448 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 449          ((reg) < 0x40000 && (reg) != FORCEWAKE)
 450
 451 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 452
 453 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 454         (REG_RANGE((reg), 0x2000, 0x4000) || \
 455          REG_RANGE((reg), 0x5000, 0x8000) || \
 456          REG_RANGE((reg), 0xB000, 0x12000) || \
 457          REG_RANGE((reg), 0x2E000, 0x30000))
 458
 459 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 460         (REG_RANGE((reg), 0x12000, 0x14000) || \
 461          REG_RANGE((reg), 0x22000, 0x24000) || \
 462          REG_RANGE((reg), 0x30000, 0x40000))
 463
 464 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 465         (REG_RANGE((reg), 0x2000, 0x4000) || \
 466          REG_RANGE((reg), 0x5200, 0x8000) || \
 467          REG_RANGE((reg), 0x8300, 0x8500) || \
 468          REG_RANGE((reg), 0xB000, 0xB480) || \
 469          REG_RANGE((reg), 0xE000, 0xE800))
 470
 471 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 472         (REG_RANGE((reg), 0x8800, 0x8900) || \
 473          REG_RANGE((reg), 0xD000, 0xD800) || \
 474          REG_RANGE((reg), 0x12000, 0x14000) || \
 475          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 476          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 477          REG_RANGE((reg), 0x30000, 0x38000))
 478
 479 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 480         (REG_RANGE((reg), 0x4000, 0x5000) || \
 481          REG_RANGE((reg), 0x8000, 0x8300) || \
 482          REG_RANGE((reg), 0x8500, 0x8600) || \
 483          REG_RANGE((reg), 0x9000, 0xB000) || \
 484          REG_RANGE((reg), 0xF000, 0x10000))
 485
 486 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 487         REG_RANGE((reg), 0xB00,  0x2000)
 488
 489 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 490         (REG_RANGE((reg), 0x2000, 0x2700) || \
 491          REG_RANGE((reg), 0x3000, 0x4000) || \
 492          REG_RANGE((reg), 0x5200, 0x8000) || \
 493          REG_RANGE((reg), 0x8140, 0x8160) || \
 494          REG_RANGE((reg), 0x8300, 0x8500) || \
 495          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 496          REG_RANGE((reg), 0xB000, 0xB480) || \
 497          REG_RANGE((reg), 0xE000, 0xE900) || \
 498          REG_RANGE((reg), 0x24400, 0x24800))
 499
 500 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 501         (REG_RANGE((reg), 0x8130, 0x8140) || \
 502          REG_RANGE((reg), 0x8800, 0x8A00) || \
 503          REG_RANGE((reg), 0xD000, 0xD800) || \
 504          REG_RANGE((reg), 0x12000, 0x14000) || \
 505          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 506          REG_RANGE((reg), 0x30000, 0x40000))
 507
 508 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 509         REG_RANGE((reg), 0x9400, 0x9800)
 510
 511 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 512         ((reg) < 0x40000 &&\
 513          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 514          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 515          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 516          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 517
 518 static void
 519 ilk_dummy_write(struct drm_i915_private *dev_priv)
 520 {
 521         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 522          * the chip from rc6 before touching it for real. MI_MODE is masked,
 523          * hence harmless to write 0 into. */
 524         __raw_i915_write32(dev_priv, MI_MODE, 0);
 525 }
 526
 527 static void
 528 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
 529                         bool before)
 530 {
 531         const char *op = read ? "reading" : "writing to";
 532         const char *when = before ? "before" : "after";
 533
 534         if (!i915.mmio_debug)
 535                 return;
 536
 537         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 538                 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 539                      when, op, reg);
 540                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 541         }
 542 }
 543
 544 static void
 545 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 546 {
 547         if (i915.mmio_debug)
 548                 return;
 549
 550         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 551                 DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
 552                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 553         }
 554 }
 555
 556 #define GEN2_READ_HEADER(x) \
 557         u##x val = 0; \
 558         assert_device_not_suspended(dev_priv);
 559
 560 #define GEN2_READ_FOOTER \
 561         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 562         return val
 563
 564 #define __gen2_read(x) \
 565 static u##x \
 566 gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 567         GEN2_READ_HEADER(x); \
 568         val = __raw_i915_read##x(dev_priv, reg); \
 569         GEN2_READ_FOOTER; \
 570 }
 571
 572 #define __gen5_read(x) \
 573 static u##x \
 574 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 575         GEN2_READ_HEADER(x); \
 576         ilk_dummy_write(dev_priv); \
 577         val = __raw_i915_read##x(dev_priv, reg); \
 578         GEN2_READ_FOOTER; \
 579 }
 580
 581 __gen5_read(8)
 582 __gen5_read(16)
 583 __gen5_read(32)
 584 __gen5_read(64)
 585 __gen2_read(8)
 586 __gen2_read(16)
 587 __gen2_read(32)
 588 __gen2_read(64)
 589
 590 #undef __gen5_read
 591 #undef __gen2_read
 592
 593 #undef GEN2_READ_FOOTER
 594 #undef GEN2_READ_HEADER
 595
 596 #define GEN6_READ_HEADER(x) \
 597         unsigned long irqflags; \
 598         u##x val = 0; \
 599         assert_device_not_suspended(dev_priv); \
 600         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 601
 602 #define GEN6_READ_FOOTER \
 603         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 604         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 605         return val
 606
 607 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
 608                                     unsigned fw_domains)
 609 {
 610         struct intel_uncore_forcewake_domain *domain;
 611         int id;
 612
 613         if (WARN_ON(!fw_domains))
 614                 return;
 615
 616         /* Ideally GCC would be constant-fold and eliminate this loop */
 617         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 618                 if (domain->wake_count) {
 619                         fw_domains &= ~(1 << id);
 620                         continue;
 621                 }
 622
 623                 domain->wake_count++;
 624                 fw_domain_arm_timer(domain);
 625         }
 626
 627         if (fw_domains)
 628                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 629 }
 630
 631 #define __gen6_read(x) \
 632 static u##x \
 633 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 634         GEN6_READ_HEADER(x); \
 635         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 636         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
 637                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 638         val = __raw_i915_read##x(dev_priv, reg); \
 639         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 640         GEN6_READ_FOOTER; \
 641 }
 642
 643 #define __vlv_read(x) \
 644 static u##x \
 645 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 646         GEN6_READ_HEADER(x); \
 647         if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
 648                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 649         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \
 650                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 651         val = __raw_i915_read##x(dev_priv, reg); \
 652         GEN6_READ_FOOTER; \
 653 }
 654
 655 #define __chv_read(x) \
 656 static u##x \
 657 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 658         GEN6_READ_HEADER(x); \
 659         if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 660                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 661         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 662                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 663         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 664                 __force_wake_get(dev_priv, \
 665                                  FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 666         val = __raw_i915_read##x(dev_priv, reg); \
 667         GEN6_READ_FOOTER; \
 668 }
 669
 670 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)     \
 671          ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 672
 673 #define __gen9_read(x) \
 674 static u##x \
 675 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 676         unsigned fw_engine; \
 677         GEN6_READ_HEADER(x); \
 678         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)))   \
 679                 fw_engine = 0; \
 680         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg))       \
 681                 fw_engine = FORCEWAKE_RENDER; \
 682         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 683                 fw_engine = FORCEWAKE_MEDIA; \
 684         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 685                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 686         else \
 687                 fw_engine = FORCEWAKE_BLITTER; \
 688         if (fw_engine) \
 689                 __force_wake_get(dev_priv, fw_engine); \
 690         val = __raw_i915_read##x(dev_priv, reg); \
 691         GEN6_READ_FOOTER; \
 692 }
 693
 694 __gen9_read(8)
 695 __gen9_read(16)
 696 __gen9_read(32)
 697 __gen9_read(64)
 698 __chv_read(8)
 699 __chv_read(16)
 700 __chv_read(32)
 701 __chv_read(64)
 702 __vlv_read(8)
 703 __vlv_read(16)
 704 __vlv_read(32)
 705 __vlv_read(64)
 706 __gen6_read(8)
 707 __gen6_read(16)
 708 __gen6_read(32)
 709 __gen6_read(64)
 710
 711 #undef __gen9_read
 712 #undef __chv_read
 713 #undef __vlv_read
 714 #undef __gen6_read
 715 #undef GEN6_READ_FOOTER
 716 #undef GEN6_READ_HEADER
 717
 718 #define GEN2_WRITE_HEADER \
 719         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 720         assert_device_not_suspended(dev_priv); \
 721
 722 #define GEN2_WRITE_FOOTER
 723
 724 #define __gen2_write(x) \
 725 static void \
 726 gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 727         GEN2_WRITE_HEADER; \
 728         __raw_i915_write##x(dev_priv, reg, val); \
 729         GEN2_WRITE_FOOTER; \
 730 }
 731
 732 #define __gen5_write(x) \
 733 static void \
 734 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 735         GEN2_WRITE_HEADER; \
 736         ilk_dummy_write(dev_priv); \
 737         __raw_i915_write##x(dev_priv, reg, val); \
 738         GEN2_WRITE_FOOTER; \
 739 }
 740
 741 __gen5_write(8)
 742 __gen5_write(16)
 743 __gen5_write(32)
 744 __gen5_write(64)
 745 __gen2_write(8)
 746 __gen2_write(16)
 747 __gen2_write(32)
 748 __gen2_write(64)
 749
 750 #undef __gen5_write
 751 #undef __gen2_write
 752
 753 #undef GEN2_WRITE_FOOTER
 754 #undef GEN2_WRITE_HEADER
 755
 756 #define GEN6_WRITE_HEADER \
 757         unsigned long irqflags; \
 758         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 759         assert_device_not_suspended(dev_priv); \
 760         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 761
 762 #define GEN6_WRITE_FOOTER \
 763         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 764
 765 #define __gen6_write(x) \
 766 static void \
 767 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 768         u32 __fifo_ret = 0; \
 769         GEN6_WRITE_HEADER; \
 770         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 771                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 772         } \
 773         __raw_i915_write##x(dev_priv, reg, val); \
 774         if (unlikely(__fifo_ret)) { \
 775                 gen6_gt_check_fifodbg(dev_priv); \
 776         } \
 777         GEN6_WRITE_FOOTER; \
 778 }
 779
 780 #define __hsw_write(x) \
 781 static void \
 782 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 783         u32 __fifo_ret = 0; \
 784         GEN6_WRITE_HEADER; \
 785         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 786                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 787         } \
 788         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 789         __raw_i915_write##x(dev_priv, reg, val); \
 790         if (unlikely(__fifo_ret)) { \
 791                 gen6_gt_check_fifodbg(dev_priv); \
 792         } \
 793         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 794         hsw_unclaimed_reg_detect(dev_priv); \
 795         GEN6_WRITE_FOOTER; \
 796 }
 797
 798 static const u32 gen8_shadowed_regs[] = {
 799         FORCEWAKE_MT,
 800         GEN6_RPNSWREQ,
 801         GEN6_RC_VIDEO_FREQ,
 802         RING_TAIL(RENDER_RING_BASE),
 803         RING_TAIL(GEN6_BSD_RING_BASE),
 804         RING_TAIL(VEBOX_RING_BASE),
 805         RING_TAIL(BLT_RING_BASE),
 806         /* TODO: Other registers are not yet used */
 807 };
 808
 809 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 810 {
 811         int i;
 812         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 813                 if (reg == gen8_shadowed_regs[i])
 814                         return true;
 815
 816         return false;
 817 }
 818
 819 #define __gen8_write(x) \
 820 static void \
 821 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 822         GEN6_WRITE_HEADER; \
 823         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 824         if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
 825                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 826         __raw_i915_write##x(dev_priv, reg, val); \
 827         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 828         hsw_unclaimed_reg_detect(dev_priv); \
 829         GEN6_WRITE_FOOTER; \
 830 }
 831
 832 #define __chv_write(x) \
 833 static void \
 834 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 835         bool shadowed = is_gen8_shadowed(dev_priv, reg); \
 836         GEN6_WRITE_HEADER; \
 837         if (!shadowed) { \
 838                 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 839                         __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 840                 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 841                         __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 842                 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 843                         __force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 844         } \
 845         __raw_i915_write##x(dev_priv, reg, val); \
 846         GEN6_WRITE_FOOTER; \
 847 }
 848
 849 static const u32 gen9_shadowed_regs[] = {
 850         RING_TAIL(RENDER_RING_BASE),
 851         RING_TAIL(GEN6_BSD_RING_BASE),
 852         RING_TAIL(VEBOX_RING_BASE),
 853         RING_TAIL(BLT_RING_BASE),
 854         FORCEWAKE_BLITTER_GEN9,
 855         FORCEWAKE_RENDER_GEN9,
 856         FORCEWAKE_MEDIA_GEN9,
 857         GEN6_RPNSWREQ,
 858         GEN6_RC_VIDEO_FREQ,
 859         /* TODO: Other registers are not yet used */
 860 };
 861
 862 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 863 {
 864         int i;
 865         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 866                 if (reg == gen9_shadowed_regs[i])
 867                         return true;
 868
 869         return false;
 870 }
 871
 872 #define __gen9_write(x) \
 873 static void \
 874 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
 875                 bool trace) { \
 876         unsigned fw_engine; \
 877         GEN6_WRITE_HEADER; \
 878         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
 879             is_gen9_shadowed(dev_priv, reg)) \
 880                 fw_engine = 0; \
 881         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
 882                 fw_engine = FORCEWAKE_RENDER; \
 883         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 884                 fw_engine = FORCEWAKE_MEDIA; \
 885         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 886                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 887         else \
 888                 fw_engine = FORCEWAKE_BLITTER; \
 889         if (fw_engine) \
 890                 __force_wake_get(dev_priv, fw_engine); \
 891         __raw_i915_write##x(dev_priv, reg, val); \
 892         GEN6_WRITE_FOOTER; \
 893 }
 894
 895 __gen9_write(8)
 896 __gen9_write(16)
 897 __gen9_write(32)
 898 __gen9_write(64)
 899 __chv_write(8)
 900 __chv_write(16)
 901 __chv_write(32)
 902 __chv_write(64)
 903 __gen8_write(8)
 904 __gen8_write(16)
 905 __gen8_write(32)
 906 __gen8_write(64)
 907 __hsw_write(8)
 908 __hsw_write(16)
 909 __hsw_write(32)
 910 __hsw_write(64)
 911 __gen6_write(8)
 912 __gen6_write(16)
 913 __gen6_write(32)
 914 __gen6_write(64)
 915
 916 #undef __gen9_write
 917 #undef __chv_write
 918 #undef __gen8_write
 919 #undef __hsw_write
 920 #undef __gen6_write
 921 #undef GEN6_WRITE_FOOTER
 922 #undef GEN6_WRITE_HEADER
 923
 924 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
 925 do { \
 926         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
 927         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
 928         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
 929         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
 930 } while (0)
 931
 932 #define ASSIGN_READ_MMIO_VFUNCS(x) \
 933 do { \
 934         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
 935         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
 936         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
 937         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
 938 } while (0)
 939
 940
 941 static void fw_domain_init(struct drm_i915_private *dev_priv,
 942                            u32 domain_id, u32 reg_set, u32 reg_ack)
 943 {
 944         struct intel_uncore_forcewake_domain *d;
 945
 946         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
 947                 return;
 948
 949         d = &dev_priv->uncore.fw_domain[domain_id];
 950
 951         WARN_ON(d->wake_count);
 952
 953         d->wake_count = 0;
 954         d->reg_set = reg_set;
 955         d->reg_ack = reg_ack;
 956
 957         if (IS_GEN6(dev_priv)) {
 958                 d->val_reset = 0;
 959                 d->val_set = FORCEWAKE_KERNEL;
 960                 d->val_clear = 0;
 961         } else {
 962                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
 963                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
 964                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
 965         }
 966
 967         if (IS_VALLEYVIEW(dev_priv))
 968                 d->reg_post = FORCEWAKE_ACK_VLV;
 969         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
 970                 d->reg_post = ECOBUS;
 971         else
 972                 d->reg_post = 0;
 973
 974         d->i915 = dev_priv;
 975         d->id = domain_id;
 976
 977         setup_timer(&d->timer, gen6_force_wake_timer, (unsigned long)d);
 978
 979         dev_priv->uncore.fw_domains |= (1 << domain_id);
 980 }
 981
 982 void intel_uncore_init(struct drm_device *dev)
 983 {
 984         struct drm_i915_private *dev_priv = dev->dev_private;
 985
 986         __intel_uncore_early_sanitize(dev, false);
 987
 988         if (IS_GEN9(dev)) {
 989                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
 990                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
 991                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
 992                                FORCEWAKE_RENDER_GEN9,
 993                                FORCEWAKE_ACK_RENDER_GEN9);
 994                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
 995                                FORCEWAKE_BLITTER_GEN9,
 996                                FORCEWAKE_ACK_BLITTER_GEN9);
 997                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
 998                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
 999         } else if (IS_VALLEYVIEW(dev)) {
1000                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1001                 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
1002                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1003                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1004                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1005                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1006         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1007                 dev_priv->uncore.funcs.force_wake_get =
1008                         fw_domains_get_with_thread_status;
1009                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1010                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1011                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1012         } else if (IS_IVYBRIDGE(dev)) {
1013                 u32 ecobus;
1014
1015                 /* IVB configs may use multi-threaded forcewake */
1016
1017                 /* A small trick here - if the bios hasn't configured
1018                  * MT forcewake, and if the device is in RC6, then
1019                  * force_wake_mt_get will not wake the device and the
1020                  * ECOBUS read will return zero. Which will be
1021                  * (correctly) interpreted by the test below as MT
1022                  * forcewake being disabled.
1023                  */
1024                 dev_priv->uncore.funcs.force_wake_get =
1025                         fw_domains_get_with_thread_status;
1026                 dev_priv->uncore.funcs.force_wake_put =
1027                         fw_domains_put_with_fifo;
1028
1029                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1030                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1031                 mutex_lock(&dev->struct_mutex);
1032                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1033                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1034                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1035                 mutex_unlock(&dev->struct_mutex);
1036
1037                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1038                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1039                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1040                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1041                                        FORCEWAKE, FORCEWAKE_ACK);
1042                 }
1043         } else if (IS_GEN6(dev)) {
1044                 dev_priv->uncore.funcs.force_wake_get =
1045                         fw_domains_get_with_thread_status;
1046                 dev_priv->uncore.funcs.force_wake_put =
1047                         fw_domains_put_with_fifo;
1048                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1049                                FORCEWAKE, FORCEWAKE_ACK);
1050         }
1051
1052         switch (INTEL_INFO(dev)->gen) {
1053         default:
1054                 MISSING_CASE(INTEL_INFO(dev)->gen);
1055                 return;
1056         case 9:
1057                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1058                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1059                 break;
1060         case 8:
1061                 if (IS_CHERRYVIEW(dev)) {
1062                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1063                         ASSIGN_READ_MMIO_VFUNCS(chv);
1064
1065                 } else {
1066                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1067                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1068                 }
1069                 break;
1070         case 7:
1071         case 6:
1072                 if (IS_HASWELL(dev)) {
1073                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1074                 } else {
1075                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1076                 }
1077
1078                 if (IS_VALLEYVIEW(dev)) {
1079                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1080                 } else {
1081                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1082                 }
1083                 break;
1084         case 5:
1085                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1086                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1087                 break;
1088         case 4:
1089         case 3:
1090         case 2:
1091                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1092                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1093                 break;
1094         }
1095
1096         i915_check_and_clear_faults(dev);
1097 }
1098 #undef ASSIGN_WRITE_MMIO_VFUNCS
1099 #undef ASSIGN_READ_MMIO_VFUNCS
1100
1101 void intel_uncore_fini(struct drm_device *dev)
1102 {
1103         /* Paranoia: make sure we have disabled everything before we exit. */
1104         intel_uncore_sanitize(dev);
1105         intel_uncore_forcewake_reset(dev, false);
1106 }
1107
1108 #define GEN_RANGE(l, h) GENMASK(h, l)
1109
1110 static const struct register_whitelist {
1111         uint64_t offset;
1112         uint32_t size;
1113         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1114         uint32_t gen_bitmask;
1115 } whitelist[] = {
1116         { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1117 };
1118
1119 int i915_reg_read_ioctl(struct drm_device *dev,
1120                         void *data, struct drm_file *file)
1121 {
1122         struct drm_i915_private *dev_priv = dev->dev_private;
1123         struct drm_i915_reg_read *reg = data;
1124         struct register_whitelist const *entry = whitelist;
1125         int i, ret = 0;
1126
1127         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1128                 if (entry->offset == reg->offset &&
1129                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1130                         break;
1131         }
1132
1133         if (i == ARRAY_SIZE(whitelist))
1134                 return -EINVAL;
1135
1136         intel_runtime_pm_get(dev_priv);
1137
1138         switch (entry->size) {
1139         case 8:
1140                 reg->val = I915_READ64(reg->offset);
1141                 break;
1142         case 4:
1143                 reg->val = I915_READ(reg->offset);
1144                 break;
1145         case 2:
1146                 reg->val = I915_READ16(reg->offset);
1147                 break;
1148         case 1:
1149                 reg->val = I915_READ8(reg->offset);
1150                 break;
1151         default:
1152                 MISSING_CASE(entry->size);
1153                 ret = -EINVAL;
1154                 goto out;
1155         }
1156
1157 out:
1158         intel_runtime_pm_put(dev_priv);
1159         return ret;
1160 }
1161
1162 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1163                                void *data, struct drm_file *file)
1164 {
1165         struct drm_i915_private *dev_priv = dev->dev_private;
1166         struct drm_i915_reset_stats *args = data;
1167         struct i915_ctx_hang_stats *hs;
1168         struct intel_context *ctx;
1169         int ret;
1170
1171         if (args->flags || args->pad)
1172                 return -EINVAL;
1173
1174         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1175                 return -EPERM;
1176
1177         ret = mutex_lock_interruptible(&dev->struct_mutex);
1178         if (ret)
1179                 return ret;
1180
1181         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1182         if (IS_ERR(ctx)) {
1183                 mutex_unlock(&dev->struct_mutex);
1184                 return PTR_ERR(ctx);
1185         }
1186         hs = &ctx->hang_stats;
1187
1188         if (capable(CAP_SYS_ADMIN))
1189                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1190         else
1191                 args->reset_count = 0;
1192
1193         args->batch_active = hs->batch_active;
1194         args->batch_pending = hs->batch_pending;
1195
1196         mutex_unlock(&dev->struct_mutex);
1197
1198         return 0;
1199 }
1200
1201 static int i915_reset_complete(struct drm_device *dev)
1202 {
1203         u8 gdrst;
1204         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1205         return (gdrst & GRDOM_RESET_STATUS) == 0;
1206 }
1207
1208 static int i915_do_reset(struct drm_device *dev)
1209 {
1210         /* assert reset for at least 20 usec */
1211         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1212         udelay(20);
1213         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1214
1215         return wait_for(i915_reset_complete(dev), 500);
1216 }
1217
1218 static int g4x_reset_complete(struct drm_device *dev)
1219 {
1220         u8 gdrst;
1221         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1222         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1223 }
1224
1225 static int g33_do_reset(struct drm_device *dev)
1226 {
1227         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1228         return wait_for(g4x_reset_complete(dev), 500);
1229 }
1230
1231 static int g4x_do_reset(struct drm_device *dev)
1232 {
1233         struct drm_i915_private *dev_priv = dev->dev_private;
1234         int ret;
1235
1236         pci_write_config_byte(dev->pdev, I915_GDRST,
1237                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1238         ret =  wait_for(g4x_reset_complete(dev), 500);
1239         if (ret)
1240                 return ret;
1241
1242         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1243         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1244         POSTING_READ(VDECCLK_GATE_D);
1245
1246         pci_write_config_byte(dev->pdev, I915_GDRST,
1247                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1248         ret =  wait_for(g4x_reset_complete(dev), 500);
1249         if (ret)
1250                 return ret;
1251
1252         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1253         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1254         POSTING_READ(VDECCLK_GATE_D);
1255
1256         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1257
1258         return 0;
1259 }
1260
1261 static int ironlake_do_reset(struct drm_device *dev)
1262 {
1263         struct drm_i915_private *dev_priv = dev->dev_private;
1264         int ret;
1265
1266         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1267                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1268         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1269                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1270         if (ret)
1271                 return ret;
1272
1273         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1274                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1275         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1276                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1277         if (ret)
1278                 return ret;
1279
1280         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1281
1282         return 0;
1283 }
1284
1285 static int gen6_do_reset(struct drm_device *dev)
1286 {
1287         struct drm_i915_private *dev_priv = dev->dev_private;
1288         int     ret;
1289
1290         /* Reset the chip */
1291
1292         /* GEN6_GDRST is not in the gt power well, no need to check
1293          * for fifo space for the write or forcewake the chip for
1294          * the read
1295          */
1296         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1297
1298         /* Spin waiting for the device to ack the reset request */
1299         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1300
1301         intel_uncore_forcewake_reset(dev, true);
1302
1303         return ret;
1304 }
1305
1306 int intel_gpu_reset(struct drm_device *dev)
1307 {
1308         if (INTEL_INFO(dev)->gen >= 6)
1309                 return gen6_do_reset(dev);
1310         else if (IS_GEN5(dev))
1311                 return ironlake_do_reset(dev);
1312         else if (IS_G4X(dev))
1313                 return g4x_do_reset(dev);
1314         else if (IS_G33(dev))
1315                 return g33_do_reset(dev);
1316         else if (INTEL_INFO(dev)->gen >= 3)
1317                 return i915_do_reset(dev);
1318         else
1319                 return -ENODEV;
1320 }
1321
1322 void intel_uncore_check_errors(struct drm_device *dev)
1323 {
1324         struct drm_i915_private *dev_priv = dev->dev_private;
1325
1326         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1327             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1328                 DRM_ERROR("Unclaimed register before interrupt\n");
1329                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1330         }
1331 }