2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
28 #include <linux/pm_runtime.h>
30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
34 static const char * const forcewake_domain_names
[] = {
41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
)
43 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names
) != FW_DOMAIN_ID_COUNT
);
45 if (id
>= 0 && id
< FW_DOMAIN_ID_COUNT
)
46 return forcewake_domain_names
[id
];
54 fw_domain_reset(const struct intel_uncore_forcewake_domain
*d
)
56 WARN_ON(!i915_mmio_reg_valid(d
->reg_set
));
57 __raw_i915_write32(d
->i915
, d
->reg_set
, d
->val_reset
);
61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain
*d
)
63 mod_timer_pinned(&d
->timer
, jiffies
+ 1);
67 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain
*d
)
69 if (wait_for_atomic((__raw_i915_read32(d
->i915
, d
->reg_ack
) &
70 FORCEWAKE_KERNEL
) == 0,
71 FORCEWAKE_ACK_TIMEOUT_MS
))
72 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
73 intel_uncore_forcewake_domain_to_str(d
->id
));
77 fw_domain_get(const struct intel_uncore_forcewake_domain
*d
)
79 __raw_i915_write32(d
->i915
, d
->reg_set
, d
->val_set
);
83 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain
*d
)
85 if (wait_for_atomic((__raw_i915_read32(d
->i915
, d
->reg_ack
) &
87 FORCEWAKE_ACK_TIMEOUT_MS
))
88 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
89 intel_uncore_forcewake_domain_to_str(d
->id
));
93 fw_domain_put(const struct intel_uncore_forcewake_domain
*d
)
95 __raw_i915_write32(d
->i915
, d
->reg_set
, d
->val_clear
);
99 fw_domain_posting_read(const struct intel_uncore_forcewake_domain
*d
)
101 /* something from same cacheline, but not from the set register */
102 if (i915_mmio_reg_valid(d
->reg_post
))
103 __raw_posting_read(d
->i915
, d
->reg_post
);
107 fw_domains_get(struct drm_i915_private
*dev_priv
, enum forcewake_domains fw_domains
)
109 struct intel_uncore_forcewake_domain
*d
;
110 enum forcewake_domain_id id
;
112 for_each_fw_domain_mask(d
, fw_domains
, dev_priv
, id
) {
113 fw_domain_wait_ack_clear(d
);
115 fw_domain_wait_ack(d
);
120 fw_domains_put(struct drm_i915_private
*dev_priv
, enum forcewake_domains fw_domains
)
122 struct intel_uncore_forcewake_domain
*d
;
123 enum forcewake_domain_id id
;
125 for_each_fw_domain_mask(d
, fw_domains
, dev_priv
, id
) {
127 fw_domain_posting_read(d
);
132 fw_domains_posting_read(struct drm_i915_private
*dev_priv
)
134 struct intel_uncore_forcewake_domain
*d
;
135 enum forcewake_domain_id id
;
137 /* No need to do for all, just do for first found */
138 for_each_fw_domain(d
, dev_priv
, id
) {
139 fw_domain_posting_read(d
);
145 fw_domains_reset(struct drm_i915_private
*dev_priv
, enum forcewake_domains fw_domains
)
147 struct intel_uncore_forcewake_domain
*d
;
148 enum forcewake_domain_id id
;
150 if (dev_priv
->uncore
.fw_domains
== 0)
153 for_each_fw_domain_mask(d
, fw_domains
, dev_priv
, id
)
156 fw_domains_posting_read(dev_priv
);
159 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private
*dev_priv
)
161 /* w/a for a sporadic read returning 0 by waiting for the GT
164 if (wait_for_atomic_us((__raw_i915_read32(dev_priv
, GEN6_GT_THREAD_STATUS_REG
) &
165 GEN6_GT_THREAD_STATUS_CORE_MASK
) == 0, 500))
166 DRM_ERROR("GT thread status wait timed out\n");
169 static void fw_domains_get_with_thread_status(struct drm_i915_private
*dev_priv
,
170 enum forcewake_domains fw_domains
)
172 fw_domains_get(dev_priv
, fw_domains
);
174 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
175 __gen6_gt_wait_for_thread_c0(dev_priv
);
178 static void gen6_gt_check_fifodbg(struct drm_i915_private
*dev_priv
)
182 gtfifodbg
= __raw_i915_read32(dev_priv
, GTFIFODBG
);
183 if (WARN(gtfifodbg
, "GT wake FIFO error 0x%x\n", gtfifodbg
))
184 __raw_i915_write32(dev_priv
, GTFIFODBG
, gtfifodbg
);
187 static void fw_domains_put_with_fifo(struct drm_i915_private
*dev_priv
,
188 enum forcewake_domains fw_domains
)
190 fw_domains_put(dev_priv
, fw_domains
);
191 gen6_gt_check_fifodbg(dev_priv
);
194 static inline u32
fifo_free_entries(struct drm_i915_private
*dev_priv
)
196 u32 count
= __raw_i915_read32(dev_priv
, GTFIFOCTL
);
198 return count
& GT_FIFO_FREE_ENTRIES_MASK
;
201 static int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
205 /* On VLV, FIFO will be shared by both SW and HW.
206 * So, we need to read the FREE_ENTRIES everytime */
207 if (IS_VALLEYVIEW(dev_priv
->dev
))
208 dev_priv
->uncore
.fifo_count
= fifo_free_entries(dev_priv
);
210 if (dev_priv
->uncore
.fifo_count
< GT_FIFO_NUM_RESERVED_ENTRIES
) {
212 u32 fifo
= fifo_free_entries(dev_priv
);
214 while (fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
&& loop
--) {
216 fifo
= fifo_free_entries(dev_priv
);
218 if (WARN_ON(loop
< 0 && fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
))
220 dev_priv
->uncore
.fifo_count
= fifo
;
222 dev_priv
->uncore
.fifo_count
--;
227 static void intel_uncore_fw_release_timer(unsigned long arg
)
229 struct intel_uncore_forcewake_domain
*domain
= (void *)arg
;
230 unsigned long irqflags
;
232 assert_rpm_device_not_suspended(domain
->i915
);
234 spin_lock_irqsave(&domain
->i915
->uncore
.lock
, irqflags
);
235 if (WARN_ON(domain
->wake_count
== 0))
236 domain
->wake_count
++;
238 if (--domain
->wake_count
== 0)
239 domain
->i915
->uncore
.funcs
.force_wake_put(domain
->i915
,
242 spin_unlock_irqrestore(&domain
->i915
->uncore
.lock
, irqflags
);
245 void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
)
247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
248 unsigned long irqflags
;
249 struct intel_uncore_forcewake_domain
*domain
;
250 int retry_count
= 100;
251 enum forcewake_domain_id id
;
252 enum forcewake_domains fw
= 0, active_domains
;
254 /* Hold uncore.lock across reset to prevent any register access
255 * with forcewake not set correctly. Wait until all pending
256 * timers are run before holding.
261 for_each_fw_domain(domain
, dev_priv
, id
) {
262 if (del_timer_sync(&domain
->timer
) == 0)
265 intel_uncore_fw_release_timer((unsigned long)domain
);
268 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
270 for_each_fw_domain(domain
, dev_priv
, id
) {
271 if (timer_pending(&domain
->timer
))
272 active_domains
|= (1 << id
);
275 if (active_domains
== 0)
278 if (--retry_count
== 0) {
279 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
283 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
287 WARN_ON(active_domains
);
289 for_each_fw_domain(domain
, dev_priv
, id
)
290 if (domain
->wake_count
)
294 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, fw
);
296 fw_domains_reset(dev_priv
, FORCEWAKE_ALL
);
298 if (restore
) { /* If reset with a user forcewake, try to restore */
300 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw
);
302 if (IS_GEN6(dev
) || IS_GEN7(dev
))
303 dev_priv
->uncore
.fifo_count
=
304 fifo_free_entries(dev_priv
);
308 assert_forcewakes_inactive(dev_priv
);
310 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
313 static void intel_uncore_ellc_detect(struct drm_device
*dev
)
315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
317 if ((IS_HASWELL(dev
) || IS_BROADWELL(dev
) ||
318 INTEL_INFO(dev
)->gen
>= 9) &&
319 (__raw_i915_read32(dev_priv
, HSW_EDRAM_PRESENT
) & EDRAM_ENABLED
)) {
320 /* The docs do not explain exactly how the calculation can be
321 * made. It is somewhat guessable, but for now, it's always
323 * NB: We can't write IDICR yet because we do not have gt funcs
325 dev_priv
->ellc_size
= 128;
326 DRM_INFO("Found %zuMB of eLLC\n", dev_priv
->ellc_size
);
331 fpga_check_for_unclaimed_mmio(struct drm_i915_private
*dev_priv
)
335 dbg
= __raw_i915_read32(dev_priv
, FPGA_DBG
);
336 if (likely(!(dbg
& FPGA_DBG_RM_NOCLAIM
)))
339 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
345 vlv_check_for_unclaimed_mmio(struct drm_i915_private
*dev_priv
)
349 cer
= __raw_i915_read32(dev_priv
, CLAIM_ER
);
350 if (likely(!(cer
& (CLAIM_ER_OVERFLOW
| CLAIM_ER_CTR_MASK
))))
353 __raw_i915_write32(dev_priv
, CLAIM_ER
, CLAIM_ER_CLR
);
359 check_for_unclaimed_mmio(struct drm_i915_private
*dev_priv
)
361 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv
))
362 return fpga_check_for_unclaimed_mmio(dev_priv
);
364 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
365 return vlv_check_for_unclaimed_mmio(dev_priv
);
370 static void __intel_uncore_early_sanitize(struct drm_device
*dev
,
371 bool restore_forcewake
)
373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
375 /* clear out unclaimed reg detection bit */
376 if (check_for_unclaimed_mmio(dev_priv
))
377 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
379 /* clear out old GT FIFO errors */
380 if (IS_GEN6(dev
) || IS_GEN7(dev
))
381 __raw_i915_write32(dev_priv
, GTFIFODBG
,
382 __raw_i915_read32(dev_priv
, GTFIFODBG
));
384 /* WaDisableShadowRegForCpd:chv */
385 if (IS_CHERRYVIEW(dev
)) {
386 __raw_i915_write32(dev_priv
, GTFIFOCTL
,
387 __raw_i915_read32(dev_priv
, GTFIFOCTL
) |
388 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL
|
389 GT_FIFO_CTL_RC6_POLICY_STALL
);
392 intel_uncore_forcewake_reset(dev
, restore_forcewake
);
395 void intel_uncore_early_sanitize(struct drm_device
*dev
, bool restore_forcewake
)
397 __intel_uncore_early_sanitize(dev
, restore_forcewake
);
398 i915_check_and_clear_faults(dev
);
401 void intel_uncore_sanitize(struct drm_device
*dev
)
403 i915
.enable_rc6
= sanitize_rc6_option(dev
, i915
.enable_rc6
);
405 /* BIOS often leaves RC6 enabled, but disable it for hw init */
406 intel_disable_gt_powersave(dev
);
409 static void __intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
410 enum forcewake_domains fw_domains
)
412 struct intel_uncore_forcewake_domain
*domain
;
413 enum forcewake_domain_id id
;
415 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
418 fw_domains
&= dev_priv
->uncore
.fw_domains
;
420 for_each_fw_domain_mask(domain
, fw_domains
, dev_priv
, id
) {
421 if (domain
->wake_count
++)
422 fw_domains
&= ~(1 << id
);
426 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw_domains
);
430 * intel_uncore_forcewake_get - grab forcewake domain references
431 * @dev_priv: i915 device instance
432 * @fw_domains: forcewake domains to get reference on
434 * This function can be used get GT's forcewake domain references.
435 * Normal register access will handle the forcewake domains automatically.
436 * However if some sequence requires the GT to not power down a particular
437 * forcewake domains this function should be called at the beginning of the
438 * sequence. And subsequently the reference should be dropped by symmetric
439 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
440 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
442 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
443 enum forcewake_domains fw_domains
)
445 unsigned long irqflags
;
447 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
450 assert_rpm_wakelock_held(dev_priv
);
452 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
453 __intel_uncore_forcewake_get(dev_priv
, fw_domains
);
454 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
458 * intel_uncore_forcewake_get__locked - grab forcewake domain references
459 * @dev_priv: i915 device instance
460 * @fw_domains: forcewake domains to get reference on
462 * See intel_uncore_forcewake_get(). This variant places the onus
463 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
465 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
466 enum forcewake_domains fw_domains
)
468 assert_spin_locked(&dev_priv
->uncore
.lock
);
470 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
473 __intel_uncore_forcewake_get(dev_priv
, fw_domains
);
476 static void __intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
477 enum forcewake_domains fw_domains
)
479 struct intel_uncore_forcewake_domain
*domain
;
480 enum forcewake_domain_id id
;
482 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
485 fw_domains
&= dev_priv
->uncore
.fw_domains
;
487 for_each_fw_domain_mask(domain
, fw_domains
, dev_priv
, id
) {
488 if (WARN_ON(domain
->wake_count
== 0))
491 if (--domain
->wake_count
)
494 domain
->wake_count
++;
495 fw_domain_arm_timer(domain
);
500 * intel_uncore_forcewake_put - release a forcewake domain reference
501 * @dev_priv: i915 device instance
502 * @fw_domains: forcewake domains to put references
504 * This function drops the device-level forcewakes for specified
505 * domains obtained by intel_uncore_forcewake_get().
507 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
508 enum forcewake_domains fw_domains
)
510 unsigned long irqflags
;
512 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
515 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
516 __intel_uncore_forcewake_put(dev_priv
, fw_domains
);
517 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
521 * intel_uncore_forcewake_put__locked - grab forcewake domain references
522 * @dev_priv: i915 device instance
523 * @fw_domains: forcewake domains to get reference on
525 * See intel_uncore_forcewake_put(). This variant places the onus
526 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
528 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
529 enum forcewake_domains fw_domains
)
531 assert_spin_locked(&dev_priv
->uncore
.lock
);
533 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
536 __intel_uncore_forcewake_put(dev_priv
, fw_domains
);
539 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
)
541 struct intel_uncore_forcewake_domain
*domain
;
542 enum forcewake_domain_id id
;
544 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
547 for_each_fw_domain(domain
, dev_priv
, id
)
548 WARN_ON(domain
->wake_count
);
551 /* We give fast paths for the really cool registers */
552 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
554 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
556 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
557 (REG_RANGE((reg), 0x2000, 0x4000) || \
558 REG_RANGE((reg), 0x5000, 0x8000) || \
559 REG_RANGE((reg), 0xB000, 0x12000) || \
560 REG_RANGE((reg), 0x2E000, 0x30000))
562 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
563 (REG_RANGE((reg), 0x12000, 0x14000) || \
564 REG_RANGE((reg), 0x22000, 0x24000) || \
565 REG_RANGE((reg), 0x30000, 0x40000))
567 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
568 (REG_RANGE((reg), 0x2000, 0x4000) || \
569 REG_RANGE((reg), 0x5200, 0x8000) || \
570 REG_RANGE((reg), 0x8300, 0x8500) || \
571 REG_RANGE((reg), 0xB000, 0xB480) || \
572 REG_RANGE((reg), 0xE000, 0xE800))
574 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
575 (REG_RANGE((reg), 0x8800, 0x8900) || \
576 REG_RANGE((reg), 0xD000, 0xD800) || \
577 REG_RANGE((reg), 0x12000, 0x14000) || \
578 REG_RANGE((reg), 0x1A000, 0x1C000) || \
579 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
580 REG_RANGE((reg), 0x30000, 0x38000))
582 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
583 (REG_RANGE((reg), 0x4000, 0x5000) || \
584 REG_RANGE((reg), 0x8000, 0x8300) || \
585 REG_RANGE((reg), 0x8500, 0x8600) || \
586 REG_RANGE((reg), 0x9000, 0xB000) || \
587 REG_RANGE((reg), 0xF000, 0x10000))
589 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
590 REG_RANGE((reg), 0xB00, 0x2000)
592 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
593 (REG_RANGE((reg), 0x2000, 0x2700) || \
594 REG_RANGE((reg), 0x3000, 0x4000) || \
595 REG_RANGE((reg), 0x5200, 0x8000) || \
596 REG_RANGE((reg), 0x8140, 0x8160) || \
597 REG_RANGE((reg), 0x8300, 0x8500) || \
598 REG_RANGE((reg), 0x8C00, 0x8D00) || \
599 REG_RANGE((reg), 0xB000, 0xB480) || \
600 REG_RANGE((reg), 0xE000, 0xE900) || \
601 REG_RANGE((reg), 0x24400, 0x24800))
603 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
604 (REG_RANGE((reg), 0x8130, 0x8140) || \
605 REG_RANGE((reg), 0x8800, 0x8A00) || \
606 REG_RANGE((reg), 0xD000, 0xD800) || \
607 REG_RANGE((reg), 0x12000, 0x14000) || \
608 REG_RANGE((reg), 0x1A000, 0x1EA00) || \
609 REG_RANGE((reg), 0x30000, 0x40000))
611 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
612 REG_RANGE((reg), 0x9400, 0x9800)
614 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
615 ((reg) < 0x40000 && \
616 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
617 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
618 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
619 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
622 ilk_dummy_write(struct drm_i915_private
*dev_priv
)
624 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
625 * the chip from rc6 before touching it for real. MI_MODE is masked,
626 * hence harmless to write 0 into. */
627 __raw_i915_write32(dev_priv
, MI_MODE
, 0);
631 __unclaimed_reg_debug(struct drm_i915_private
*dev_priv
,
632 const i915_reg_t reg
,
636 /* XXX. We limit the auto arming traces for mmio
637 * debugs on these platforms. There are just too many
638 * revealed by these and CI/Bat suffers from the noise.
639 * Please fix and then re-enable the automatic traces.
641 if (i915
.mmio_debug
< 2 &&
642 (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
645 if (WARN(check_for_unclaimed_mmio(dev_priv
),
646 "Unclaimed register detected %s %s register 0x%x\n",
647 before
? "before" : "after",
648 read
? "reading" : "writing to",
649 i915_mmio_reg_offset(reg
)))
650 i915
.mmio_debug
--; /* Only report the first N failures */
654 unclaimed_reg_debug(struct drm_i915_private
*dev_priv
,
655 const i915_reg_t reg
,
659 if (likely(!i915
.mmio_debug
))
662 __unclaimed_reg_debug(dev_priv
, reg
, read
, before
);
665 #define GEN2_READ_HEADER(x) \
667 assert_rpm_wakelock_held(dev_priv);
669 #define GEN2_READ_FOOTER \
670 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
673 #define __gen2_read(x) \
675 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
676 GEN2_READ_HEADER(x); \
677 val = __raw_i915_read##x(dev_priv, reg); \
681 #define __gen5_read(x) \
683 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
684 GEN2_READ_HEADER(x); \
685 ilk_dummy_write(dev_priv); \
686 val = __raw_i915_read##x(dev_priv, reg); \
702 #undef GEN2_READ_FOOTER
703 #undef GEN2_READ_HEADER
705 #define GEN6_READ_HEADER(x) \
706 u32 offset = i915_mmio_reg_offset(reg); \
707 unsigned long irqflags; \
709 assert_rpm_wakelock_held(dev_priv); \
710 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
711 unclaimed_reg_debug(dev_priv, reg, true, true)
713 #define GEN6_READ_FOOTER \
714 unclaimed_reg_debug(dev_priv, reg, true, false); \
715 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
716 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
719 static inline void __force_wake_get(struct drm_i915_private
*dev_priv
,
720 enum forcewake_domains fw_domains
)
722 struct intel_uncore_forcewake_domain
*domain
;
723 enum forcewake_domain_id id
;
725 if (WARN_ON(!fw_domains
))
728 /* Ideally GCC would be constant-fold and eliminate this loop */
729 for_each_fw_domain_mask(domain
, fw_domains
, dev_priv
, id
) {
730 if (domain
->wake_count
) {
731 fw_domains
&= ~(1 << id
);
735 domain
->wake_count
++;
736 fw_domain_arm_timer(domain
);
740 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw_domains
);
743 #define __gen6_read(x) \
745 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
746 GEN6_READ_HEADER(x); \
747 if (NEEDS_FORCE_WAKE(offset)) \
748 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
749 val = __raw_i915_read##x(dev_priv, reg); \
753 #define __vlv_read(x) \
755 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
756 enum forcewake_domains fw_engine = 0; \
757 GEN6_READ_HEADER(x); \
758 if (!NEEDS_FORCE_WAKE(offset)) \
760 else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
761 fw_engine = FORCEWAKE_RENDER; \
762 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
763 fw_engine = FORCEWAKE_MEDIA; \
765 __force_wake_get(dev_priv, fw_engine); \
766 val = __raw_i915_read##x(dev_priv, reg); \
770 #define __chv_read(x) \
772 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
773 enum forcewake_domains fw_engine = 0; \
774 GEN6_READ_HEADER(x); \
775 if (!NEEDS_FORCE_WAKE(offset)) \
777 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
778 fw_engine = FORCEWAKE_RENDER; \
779 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
780 fw_engine = FORCEWAKE_MEDIA; \
781 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
782 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
784 __force_wake_get(dev_priv, fw_engine); \
785 val = __raw_i915_read##x(dev_priv, reg); \
789 #define SKL_NEEDS_FORCE_WAKE(reg) \
790 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
792 #define __gen9_read(x) \
794 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
795 enum forcewake_domains fw_engine; \
796 GEN6_READ_HEADER(x); \
797 if (!SKL_NEEDS_FORCE_WAKE(offset)) \
799 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
800 fw_engine = FORCEWAKE_RENDER; \
801 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
802 fw_engine = FORCEWAKE_MEDIA; \
803 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
804 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
806 fw_engine = FORCEWAKE_BLITTER; \
808 __force_wake_get(dev_priv, fw_engine); \
809 val = __raw_i915_read##x(dev_priv, reg); \
834 #undef GEN6_READ_FOOTER
835 #undef GEN6_READ_HEADER
837 #define VGPU_READ_HEADER(x) \
838 unsigned long irqflags; \
840 assert_rpm_device_not_suspended(dev_priv); \
841 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
843 #define VGPU_READ_FOOTER \
844 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
845 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
848 #define __vgpu_read(x) \
850 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
851 VGPU_READ_HEADER(x); \
852 val = __raw_i915_read##x(dev_priv, reg); \
862 #undef VGPU_READ_FOOTER
863 #undef VGPU_READ_HEADER
865 #define GEN2_WRITE_HEADER \
866 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
867 assert_rpm_wakelock_held(dev_priv); \
869 #define GEN2_WRITE_FOOTER
871 #define __gen2_write(x) \
873 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
875 __raw_i915_write##x(dev_priv, reg, val); \
879 #define __gen5_write(x) \
881 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
883 ilk_dummy_write(dev_priv); \
884 __raw_i915_write##x(dev_priv, reg, val); \
900 #undef GEN2_WRITE_FOOTER
901 #undef GEN2_WRITE_HEADER
903 #define GEN6_WRITE_HEADER \
904 u32 offset = i915_mmio_reg_offset(reg); \
905 unsigned long irqflags; \
906 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
907 assert_rpm_wakelock_held(dev_priv); \
908 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
909 unclaimed_reg_debug(dev_priv, reg, false, true)
911 #define GEN6_WRITE_FOOTER \
912 unclaimed_reg_debug(dev_priv, reg, false, false); \
913 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
915 #define __gen6_write(x) \
917 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
918 u32 __fifo_ret = 0; \
920 if (NEEDS_FORCE_WAKE(offset)) { \
921 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
923 __raw_i915_write##x(dev_priv, reg, val); \
924 if (unlikely(__fifo_ret)) { \
925 gen6_gt_check_fifodbg(dev_priv); \
930 #define __hsw_write(x) \
932 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
933 u32 __fifo_ret = 0; \
935 if (NEEDS_FORCE_WAKE(offset)) { \
936 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
938 __raw_i915_write##x(dev_priv, reg, val); \
939 if (unlikely(__fifo_ret)) { \
940 gen6_gt_check_fifodbg(dev_priv); \
945 static const i915_reg_t gen8_shadowed_regs
[] = {
949 RING_TAIL(RENDER_RING_BASE
),
950 RING_TAIL(GEN6_BSD_RING_BASE
),
951 RING_TAIL(VEBOX_RING_BASE
),
952 RING_TAIL(BLT_RING_BASE
),
953 /* TODO: Other registers are not yet used */
956 static bool is_gen8_shadowed(struct drm_i915_private
*dev_priv
,
960 for (i
= 0; i
< ARRAY_SIZE(gen8_shadowed_regs
); i
++)
961 if (i915_mmio_reg_equal(reg
, gen8_shadowed_regs
[i
]))
967 #define __gen8_write(x) \
969 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
971 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(dev_priv, reg)) \
972 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
973 __raw_i915_write##x(dev_priv, reg, val); \
977 #define __chv_write(x) \
979 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
980 enum forcewake_domains fw_engine = 0; \
982 if (!NEEDS_FORCE_WAKE(offset) || \
983 is_gen8_shadowed(dev_priv, reg)) \
985 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
986 fw_engine = FORCEWAKE_RENDER; \
987 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
988 fw_engine = FORCEWAKE_MEDIA; \
989 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
990 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
992 __force_wake_get(dev_priv, fw_engine); \
993 __raw_i915_write##x(dev_priv, reg, val); \
997 static const i915_reg_t gen9_shadowed_regs
[] = {
998 RING_TAIL(RENDER_RING_BASE
),
999 RING_TAIL(GEN6_BSD_RING_BASE
),
1000 RING_TAIL(VEBOX_RING_BASE
),
1001 RING_TAIL(BLT_RING_BASE
),
1002 FORCEWAKE_BLITTER_GEN9
,
1003 FORCEWAKE_RENDER_GEN9
,
1004 FORCEWAKE_MEDIA_GEN9
,
1007 /* TODO: Other registers are not yet used */
1010 static bool is_gen9_shadowed(struct drm_i915_private
*dev_priv
,
1014 for (i
= 0; i
< ARRAY_SIZE(gen9_shadowed_regs
); i
++)
1015 if (i915_mmio_reg_equal(reg
, gen9_shadowed_regs
[i
]))
1021 #define __gen9_write(x) \
1023 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
1025 enum forcewake_domains fw_engine; \
1026 GEN6_WRITE_HEADER; \
1027 if (!SKL_NEEDS_FORCE_WAKE(offset) || \
1028 is_gen9_shadowed(dev_priv, reg)) \
1030 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
1031 fw_engine = FORCEWAKE_RENDER; \
1032 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
1033 fw_engine = FORCEWAKE_MEDIA; \
1034 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
1035 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
1037 fw_engine = FORCEWAKE_BLITTER; \
1039 __force_wake_get(dev_priv, fw_engine); \
1040 __raw_i915_write##x(dev_priv, reg, val); \
1041 GEN6_WRITE_FOOTER; \
1070 #undef GEN6_WRITE_FOOTER
1071 #undef GEN6_WRITE_HEADER
1073 #define VGPU_WRITE_HEADER \
1074 unsigned long irqflags; \
1075 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1076 assert_rpm_device_not_suspended(dev_priv); \
1077 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1079 #define VGPU_WRITE_FOOTER \
1080 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1082 #define __vgpu_write(x) \
1083 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1084 i915_reg_t reg, u##x val, bool trace) { \
1085 VGPU_WRITE_HEADER; \
1086 __raw_i915_write##x(dev_priv, reg, val); \
1087 VGPU_WRITE_FOOTER; \
1096 #undef VGPU_WRITE_FOOTER
1097 #undef VGPU_WRITE_HEADER
1099 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1101 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1102 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1103 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1104 dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1107 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1109 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1110 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1111 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1112 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1116 static void fw_domain_init(struct drm_i915_private
*dev_priv
,
1117 enum forcewake_domain_id domain_id
,
1121 struct intel_uncore_forcewake_domain
*d
;
1123 if (WARN_ON(domain_id
>= FW_DOMAIN_ID_COUNT
))
1126 d
= &dev_priv
->uncore
.fw_domain
[domain_id
];
1128 WARN_ON(d
->wake_count
);
1131 d
->reg_set
= reg_set
;
1132 d
->reg_ack
= reg_ack
;
1134 if (IS_GEN6(dev_priv
)) {
1136 d
->val_set
= FORCEWAKE_KERNEL
;
1139 /* WaRsClearFWBitsAtReset:bdw,skl */
1140 d
->val_reset
= _MASKED_BIT_DISABLE(0xffff);
1141 d
->val_set
= _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
);
1142 d
->val_clear
= _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
);
1145 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1146 d
->reg_post
= FORCEWAKE_ACK_VLV
;
1147 else if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
) || IS_GEN8(dev_priv
))
1148 d
->reg_post
= ECOBUS
;
1153 setup_timer(&d
->timer
, intel_uncore_fw_release_timer
, (unsigned long)d
);
1155 dev_priv
->uncore
.fw_domains
|= (1 << domain_id
);
1160 static void intel_uncore_fw_domains_init(struct drm_device
*dev
)
1162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1164 if (INTEL_INFO(dev_priv
->dev
)->gen
<= 5)
1168 dev_priv
->uncore
.funcs
.force_wake_get
= fw_domains_get
;
1169 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1170 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1171 FORCEWAKE_RENDER_GEN9
,
1172 FORCEWAKE_ACK_RENDER_GEN9
);
1173 fw_domain_init(dev_priv
, FW_DOMAIN_ID_BLITTER
,
1174 FORCEWAKE_BLITTER_GEN9
,
1175 FORCEWAKE_ACK_BLITTER_GEN9
);
1176 fw_domain_init(dev_priv
, FW_DOMAIN_ID_MEDIA
,
1177 FORCEWAKE_MEDIA_GEN9
, FORCEWAKE_ACK_MEDIA_GEN9
);
1178 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1179 dev_priv
->uncore
.funcs
.force_wake_get
= fw_domains_get
;
1180 if (!IS_CHERRYVIEW(dev
))
1181 dev_priv
->uncore
.funcs
.force_wake_put
=
1182 fw_domains_put_with_fifo
;
1184 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1185 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1186 FORCEWAKE_VLV
, FORCEWAKE_ACK_VLV
);
1187 fw_domain_init(dev_priv
, FW_DOMAIN_ID_MEDIA
,
1188 FORCEWAKE_MEDIA_VLV
, FORCEWAKE_ACK_MEDIA_VLV
);
1189 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
1190 dev_priv
->uncore
.funcs
.force_wake_get
=
1191 fw_domains_get_with_thread_status
;
1192 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1193 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1194 FORCEWAKE_MT
, FORCEWAKE_ACK_HSW
);
1195 } else if (IS_IVYBRIDGE(dev
)) {
1198 /* IVB configs may use multi-threaded forcewake */
1200 /* A small trick here - if the bios hasn't configured
1201 * MT forcewake, and if the device is in RC6, then
1202 * force_wake_mt_get will not wake the device and the
1203 * ECOBUS read will return zero. Which will be
1204 * (correctly) interpreted by the test below as MT
1205 * forcewake being disabled.
1207 dev_priv
->uncore
.funcs
.force_wake_get
=
1208 fw_domains_get_with_thread_status
;
1209 dev_priv
->uncore
.funcs
.force_wake_put
=
1210 fw_domains_put_with_fifo
;
1212 /* We need to init first for ECOBUS access and then
1213 * determine later if we want to reinit, in case of MT access is
1214 * not working. In this stage we don't know which flavour this
1215 * ivb is, so it is better to reset also the gen6 fw registers
1216 * before the ecobus check.
1219 __raw_i915_write32(dev_priv
, FORCEWAKE
, 0);
1220 __raw_posting_read(dev_priv
, ECOBUS
);
1222 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1223 FORCEWAKE_MT
, FORCEWAKE_MT_ACK
);
1225 mutex_lock(&dev
->struct_mutex
);
1226 fw_domains_get_with_thread_status(dev_priv
, FORCEWAKE_ALL
);
1227 ecobus
= __raw_i915_read32(dev_priv
, ECOBUS
);
1228 fw_domains_put_with_fifo(dev_priv
, FORCEWAKE_ALL
);
1229 mutex_unlock(&dev
->struct_mutex
);
1231 if (!(ecobus
& FORCEWAKE_MT_ENABLE
)) {
1232 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1233 DRM_INFO("when using vblank-synced partial screen updates.\n");
1234 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1235 FORCEWAKE
, FORCEWAKE_ACK
);
1237 } else if (IS_GEN6(dev
)) {
1238 dev_priv
->uncore
.funcs
.force_wake_get
=
1239 fw_domains_get_with_thread_status
;
1240 dev_priv
->uncore
.funcs
.force_wake_put
=
1241 fw_domains_put_with_fifo
;
1242 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1243 FORCEWAKE
, FORCEWAKE_ACK
);
1246 /* All future platforms are expected to require complex power gating */
1247 WARN_ON(dev_priv
->uncore
.fw_domains
== 0);
1250 void intel_uncore_init(struct drm_device
*dev
)
1252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1254 i915_check_vgpu(dev
);
1256 intel_uncore_ellc_detect(dev
);
1257 intel_uncore_fw_domains_init(dev
);
1258 __intel_uncore_early_sanitize(dev
, false);
1260 dev_priv
->uncore
.unclaimed_mmio_check
= 1;
1262 switch (INTEL_INFO(dev
)->gen
) {
1265 ASSIGN_WRITE_MMIO_VFUNCS(gen9
);
1266 ASSIGN_READ_MMIO_VFUNCS(gen9
);
1269 if (IS_CHERRYVIEW(dev
)) {
1270 ASSIGN_WRITE_MMIO_VFUNCS(chv
);
1271 ASSIGN_READ_MMIO_VFUNCS(chv
);
1274 ASSIGN_WRITE_MMIO_VFUNCS(gen8
);
1275 ASSIGN_READ_MMIO_VFUNCS(gen6
);
1280 if (IS_HASWELL(dev
)) {
1281 ASSIGN_WRITE_MMIO_VFUNCS(hsw
);
1283 ASSIGN_WRITE_MMIO_VFUNCS(gen6
);
1286 if (IS_VALLEYVIEW(dev
)) {
1287 ASSIGN_READ_MMIO_VFUNCS(vlv
);
1289 ASSIGN_READ_MMIO_VFUNCS(gen6
);
1293 ASSIGN_WRITE_MMIO_VFUNCS(gen5
);
1294 ASSIGN_READ_MMIO_VFUNCS(gen5
);
1299 ASSIGN_WRITE_MMIO_VFUNCS(gen2
);
1300 ASSIGN_READ_MMIO_VFUNCS(gen2
);
1304 if (intel_vgpu_active(dev
)) {
1305 ASSIGN_WRITE_MMIO_VFUNCS(vgpu
);
1306 ASSIGN_READ_MMIO_VFUNCS(vgpu
);
1309 i915_check_and_clear_faults(dev
);
1311 #undef ASSIGN_WRITE_MMIO_VFUNCS
1312 #undef ASSIGN_READ_MMIO_VFUNCS
1314 void intel_uncore_fini(struct drm_device
*dev
)
1316 /* Paranoia: make sure we have disabled everything before we exit. */
1317 intel_uncore_sanitize(dev
);
1318 intel_uncore_forcewake_reset(dev
, false);
1321 #define GEN_RANGE(l, h) GENMASK(h, l)
1323 static const struct register_whitelist
{
1324 i915_reg_t offset_ldw
, offset_udw
;
1326 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1327 uint32_t gen_bitmask
;
1329 { .offset_ldw
= RING_TIMESTAMP(RENDER_RING_BASE
),
1330 .offset_udw
= RING_TIMESTAMP_UDW(RENDER_RING_BASE
),
1331 .size
= 8, .gen_bitmask
= GEN_RANGE(4, 9) },
1334 int i915_reg_read_ioctl(struct drm_device
*dev
,
1335 void *data
, struct drm_file
*file
)
1337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1338 struct drm_i915_reg_read
*reg
= data
;
1339 struct register_whitelist
const *entry
= whitelist
;
1341 i915_reg_t offset_ldw
, offset_udw
;
1344 for (i
= 0; i
< ARRAY_SIZE(whitelist
); i
++, entry
++) {
1345 if (i915_mmio_reg_offset(entry
->offset_ldw
) == (reg
->offset
& -entry
->size
) &&
1346 (1 << INTEL_INFO(dev
)->gen
& entry
->gen_bitmask
))
1350 if (i
== ARRAY_SIZE(whitelist
))
1353 /* We use the low bits to encode extra flags as the register should
1354 * be naturally aligned (and those that are not so aligned merely
1355 * limit the available flags for that register).
1357 offset_ldw
= entry
->offset_ldw
;
1358 offset_udw
= entry
->offset_udw
;
1360 size
|= reg
->offset
^ i915_mmio_reg_offset(offset_ldw
);
1362 intel_runtime_pm_get(dev_priv
);
1366 reg
->val
= I915_READ64_2x32(offset_ldw
, offset_udw
);
1369 reg
->val
= I915_READ64(offset_ldw
);
1372 reg
->val
= I915_READ(offset_ldw
);
1375 reg
->val
= I915_READ16(offset_ldw
);
1378 reg
->val
= I915_READ8(offset_ldw
);
1386 intel_runtime_pm_put(dev_priv
);
1390 int i915_get_reset_stats_ioctl(struct drm_device
*dev
,
1391 void *data
, struct drm_file
*file
)
1393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1394 struct drm_i915_reset_stats
*args
= data
;
1395 struct i915_ctx_hang_stats
*hs
;
1396 struct intel_context
*ctx
;
1399 if (args
->flags
|| args
->pad
)
1402 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
&& !capable(CAP_SYS_ADMIN
))
1405 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1409 ctx
= i915_gem_context_get(file
->driver_priv
, args
->ctx_id
);
1411 mutex_unlock(&dev
->struct_mutex
);
1412 return PTR_ERR(ctx
);
1414 hs
= &ctx
->hang_stats
;
1416 if (capable(CAP_SYS_ADMIN
))
1417 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
1419 args
->reset_count
= 0;
1421 args
->batch_active
= hs
->batch_active
;
1422 args
->batch_pending
= hs
->batch_pending
;
1424 mutex_unlock(&dev
->struct_mutex
);
1429 static int i915_reset_complete(struct drm_device
*dev
)
1432 pci_read_config_byte(dev
->pdev
, I915_GDRST
, &gdrst
);
1433 return (gdrst
& GRDOM_RESET_STATUS
) == 0;
1436 static int i915_do_reset(struct drm_device
*dev
)
1438 /* assert reset for at least 20 usec */
1439 pci_write_config_byte(dev
->pdev
, I915_GDRST
, GRDOM_RESET_ENABLE
);
1441 pci_write_config_byte(dev
->pdev
, I915_GDRST
, 0);
1443 return wait_for(i915_reset_complete(dev
), 500);
1446 static int g4x_reset_complete(struct drm_device
*dev
)
1449 pci_read_config_byte(dev
->pdev
, I915_GDRST
, &gdrst
);
1450 return (gdrst
& GRDOM_RESET_ENABLE
) == 0;
1453 static int g33_do_reset(struct drm_device
*dev
)
1455 pci_write_config_byte(dev
->pdev
, I915_GDRST
, GRDOM_RESET_ENABLE
);
1456 return wait_for(g4x_reset_complete(dev
), 500);
1459 static int g4x_do_reset(struct drm_device
*dev
)
1461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1464 pci_write_config_byte(dev
->pdev
, I915_GDRST
,
1465 GRDOM_RENDER
| GRDOM_RESET_ENABLE
);
1466 ret
= wait_for(g4x_reset_complete(dev
), 500);
1470 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1471 I915_WRITE(VDECCLK_GATE_D
, I915_READ(VDECCLK_GATE_D
) | VCP_UNIT_CLOCK_GATE_DISABLE
);
1472 POSTING_READ(VDECCLK_GATE_D
);
1474 pci_write_config_byte(dev
->pdev
, I915_GDRST
,
1475 GRDOM_MEDIA
| GRDOM_RESET_ENABLE
);
1476 ret
= wait_for(g4x_reset_complete(dev
), 500);
1480 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1481 I915_WRITE(VDECCLK_GATE_D
, I915_READ(VDECCLK_GATE_D
) & ~VCP_UNIT_CLOCK_GATE_DISABLE
);
1482 POSTING_READ(VDECCLK_GATE_D
);
1484 pci_write_config_byte(dev
->pdev
, I915_GDRST
, 0);
1489 static int ironlake_do_reset(struct drm_device
*dev
)
1491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1494 I915_WRITE(ILK_GDSR
,
1495 ILK_GRDOM_RENDER
| ILK_GRDOM_RESET_ENABLE
);
1496 ret
= wait_for((I915_READ(ILK_GDSR
) &
1497 ILK_GRDOM_RESET_ENABLE
) == 0, 500);
1501 I915_WRITE(ILK_GDSR
,
1502 ILK_GRDOM_MEDIA
| ILK_GRDOM_RESET_ENABLE
);
1503 ret
= wait_for((I915_READ(ILK_GDSR
) &
1504 ILK_GRDOM_RESET_ENABLE
) == 0, 500);
1508 I915_WRITE(ILK_GDSR
, 0);
1513 static int gen6_do_reset(struct drm_device
*dev
)
1515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1518 /* Reset the chip */
1520 /* GEN6_GDRST is not in the gt power well, no need to check
1521 * for fifo space for the write or forcewake the chip for
1524 __raw_i915_write32(dev_priv
, GEN6_GDRST
, GEN6_GRDOM_FULL
);
1526 /* Spin waiting for the device to ack the reset request */
1527 ret
= wait_for((__raw_i915_read32(dev_priv
, GEN6_GDRST
) & GEN6_GRDOM_FULL
) == 0, 500);
1529 intel_uncore_forcewake_reset(dev
, true);
1534 static int wait_for_register(struct drm_i915_private
*dev_priv
,
1538 const unsigned long timeout_ms
)
1540 return wait_for((I915_READ(reg
) & mask
) == value
, timeout_ms
);
1543 static int gen8_do_reset(struct drm_device
*dev
)
1545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1546 struct intel_engine_cs
*engine
;
1549 for_each_ring(engine
, dev_priv
, i
) {
1550 I915_WRITE(RING_RESET_CTL(engine
->mmio_base
),
1551 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET
));
1553 if (wait_for_register(dev_priv
,
1554 RING_RESET_CTL(engine
->mmio_base
),
1555 RESET_CTL_READY_TO_RESET
,
1556 RESET_CTL_READY_TO_RESET
,
1558 DRM_ERROR("%s: reset request timeout\n", engine
->name
);
1563 return gen6_do_reset(dev
);
1566 for_each_ring(engine
, dev_priv
, i
)
1567 I915_WRITE(RING_RESET_CTL(engine
->mmio_base
),
1568 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET
));
1573 static int (*intel_get_gpu_reset(struct drm_device
*dev
))(struct drm_device
*)
1578 if (INTEL_INFO(dev
)->gen
>= 8)
1579 return gen8_do_reset
;
1580 else if (INTEL_INFO(dev
)->gen
>= 6)
1581 return gen6_do_reset
;
1582 else if (IS_GEN5(dev
))
1583 return ironlake_do_reset
;
1584 else if (IS_G4X(dev
))
1585 return g4x_do_reset
;
1586 else if (IS_G33(dev
))
1587 return g33_do_reset
;
1588 else if (INTEL_INFO(dev
)->gen
>= 3)
1589 return i915_do_reset
;
1594 int intel_gpu_reset(struct drm_device
*dev
)
1596 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1597 int (*reset
)(struct drm_device
*);
1600 reset
= intel_get_gpu_reset(dev
);
1604 /* If the power well sleeps during the reset, the reset
1605 * request may be dropped and never completes (causing -EIO).
1607 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1609 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1614 bool intel_has_gpu_reset(struct drm_device
*dev
)
1616 return intel_get_gpu_reset(dev
) != NULL
;
1619 bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
)
1621 return check_for_unclaimed_mmio(dev_priv
);
1625 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
)
1627 if (unlikely(i915
.mmio_debug
||
1628 dev_priv
->uncore
.unclaimed_mmio_check
<= 0))
1631 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv
))) {
1632 DRM_DEBUG("Unclaimed register detected, "
1633 "enabling oneshot unclaimed register reporting. "
1634 "Please use i915.mmio_debug=N for more information.\n");
1636 dev_priv
->uncore
.unclaimed_mmio_check
--;