drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26
  27 #include <linux/pm_runtime.h>
  28
  29 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  30
  31 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
  32 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
  33
  34 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
  35 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
  36
  37 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  38 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
  39
  40 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
  41 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
  42
  43 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  44
  45 static const char * const forcewake_domain_names[] = {
  46         "render",
  47         "blitter",
  48         "media",
  49 };
  50
  51 const char *
  52 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  53 {
  54         BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) !=
  55                      FW_DOMAIN_ID_COUNT);
  56
  57         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  58                 return forcewake_domain_names[id];
  59
  60         WARN_ON(id);
  61
  62         return "unknown";
  63 }
  64
  65 static void
  66 assert_device_not_suspended(struct drm_i915_private *dev_priv)
  67 {
  68         WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
  69                   "Device suspended\n");
  70 }
  71
  72 static inline void
  73 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  74 {
  75         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  76 }
  77
  78 static inline void
  79 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  80 {
  81         mod_timer_pinned(&d->timer, jiffies + 1);
  82 }
  83
  84 static inline void
  85 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  86 {
  87         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  88                              FORCEWAKE_KERNEL) == 0,
  89                             FORCEWAKE_ACK_TIMEOUT_MS))
  90                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  91                           intel_uncore_forcewake_domain_to_str(d->id));
  92 }
  93
  94 static inline void
  95 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  96 {
  97         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  98 }
  99
 100 static inline void
 101 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
 102 {
 103         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
 104                              FORCEWAKE_KERNEL),
 105                             FORCEWAKE_ACK_TIMEOUT_MS))
 106                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 107                           intel_uncore_forcewake_domain_to_str(d->id));
 108 }
 109
 110 static inline void
 111 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 112 {
 113         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 114 }
 115
 116 static inline void
 117 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 118 {
 119         /* something from same cacheline, but not from the set register */
 120         if (d->reg_post)
 121                 __raw_posting_read(d->i915, d->reg_post);
 122 }
 123
 124 static void
 125 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 126 {
 127         struct intel_uncore_forcewake_domain *d;
 128         enum forcewake_domain_id id;
 129
 130         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 131                 fw_domain_wait_ack_clear(d);
 132                 fw_domain_get(d);
 133                 fw_domain_posting_read(d);
 134                 fw_domain_wait_ack(d);
 135         }
 136 }
 137
 138 static void
 139 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 140 {
 141         struct intel_uncore_forcewake_domain *d;
 142         enum forcewake_domain_id id;
 143
 144         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 145                 fw_domain_put(d);
 146                 fw_domain_posting_read(d);
 147         }
 148 }
 149
 150 static void
 151 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 152 {
 153         struct intel_uncore_forcewake_domain *d;
 154         enum forcewake_domain_id id;
 155
 156         /* No need to do for all, just do for first found */
 157         for_each_fw_domain(d, dev_priv, id) {
 158                 fw_domain_posting_read(d);
 159                 break;
 160         }
 161 }
 162
 163 static void
 164 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 165 {
 166         struct intel_uncore_forcewake_domain *d;
 167         enum forcewake_domain_id id;
 168
 169         for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
 170                 fw_domain_reset(d);
 171
 172         fw_domains_posting_read(dev_priv);
 173 }
 174
 175 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 176 {
 177         /* w/a for a sporadic read returning 0 by waiting for the GT
 178          * thread to wake up.
 179          */
 180         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 181                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 182                 DRM_ERROR("GT thread status wait timed out\n");
 183 }
 184
 185 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 186                                               enum forcewake_domains fw_domains)
 187 {
 188         fw_domains_get(dev_priv, fw_domains);
 189
 190         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 191         __gen6_gt_wait_for_thread_c0(dev_priv);
 192 }
 193
 194 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 195 {
 196         u32 gtfifodbg;
 197
 198         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 199         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 200                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 201 }
 202
 203 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 204                                      enum forcewake_domains fw_domains)
 205 {
 206         fw_domains_put(dev_priv, fw_domains);
 207         gen6_gt_check_fifodbg(dev_priv);
 208 }
 209
 210 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 211 {
 212         int ret = 0;
 213
 214         /* On VLV, FIFO will be shared by both SW and HW.
 215          * So, we need to read the FREE_ENTRIES everytime */
 216         if (IS_VALLEYVIEW(dev_priv->dev))
 217                 dev_priv->uncore.fifo_count =
 218                         __raw_i915_read32(dev_priv, GTFIFOCTL) &
 219                                                 GT_FIFO_FREE_ENTRIES_MASK;
 220
 221         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 222                 int loop = 500;
 223                 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 224                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 225                         udelay(10);
 226                         fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 227                 }
 228                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 229                         ++ret;
 230                 dev_priv->uncore.fifo_count = fifo;
 231         }
 232         dev_priv->uncore.fifo_count--;
 233
 234         return ret;
 235 }
 236
 237 static void intel_uncore_fw_release_timer(unsigned long arg)
 238 {
 239         struct intel_uncore_forcewake_domain *domain = (void *)arg;
 240         unsigned long irqflags;
 241
 242         assert_device_not_suspended(domain->i915);
 243
 244         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 245         if (WARN_ON(domain->wake_count == 0))
 246                 domain->wake_count++;
 247
 248         if (--domain->wake_count == 0)
 249                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 250                                                           1 << domain->id);
 251
 252         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 253 }
 254
 255 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 256 {
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         unsigned long irqflags;
 259         struct intel_uncore_forcewake_domain *domain;
 260         int retry_count = 100;
 261         enum forcewake_domain_id id;
 262         enum forcewake_domains fw = 0, active_domains;
 263
 264         /* Hold uncore.lock across reset to prevent any register access
 265          * with forcewake not set correctly. Wait until all pending
 266          * timers are run before holding.
 267          */
 268         while (1) {
 269                 active_domains = 0;
 270
 271                 for_each_fw_domain(domain, dev_priv, id) {
 272                         if (del_timer_sync(&domain->timer) == 0)
 273                                 continue;
 274
 275                         intel_uncore_fw_release_timer((unsigned long)domain);
 276                 }
 277
 278                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 279
 280                 for_each_fw_domain(domain, dev_priv, id) {
 281                         if (timer_pending(&domain->timer))
 282                                 active_domains |= (1 << id);
 283                 }
 284
 285                 if (active_domains == 0)
 286                         break;
 287
 288                 if (--retry_count == 0) {
 289                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 290                         break;
 291                 }
 292
 293                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 294                 cond_resched();
 295         }
 296
 297         WARN_ON(active_domains);
 298
 299         for_each_fw_domain(domain, dev_priv, id)
 300                 if (domain->wake_count)
 301                         fw |= 1 << id;
 302
 303         if (fw)
 304                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 305
 306         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 307
 308         if (restore) { /* If reset with a user forcewake, try to restore */
 309                 if (fw)
 310                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 311
 312                 if (IS_GEN6(dev) || IS_GEN7(dev))
 313                         dev_priv->uncore.fifo_count =
 314                                 __raw_i915_read32(dev_priv, GTFIFOCTL) &
 315                                 GT_FIFO_FREE_ENTRIES_MASK;
 316         }
 317
 318         if (!restore)
 319                 assert_forcewakes_inactive(dev_priv);
 320
 321         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 322 }
 323
 324 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 325                                           bool restore_forcewake)
 326 {
 327         struct drm_i915_private *dev_priv = dev->dev_private;
 328
 329         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 330                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 331
 332         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
 333             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
 334                 /* The docs do not explain exactly how the calculation can be
 335                  * made. It is somewhat guessable, but for now, it's always
 336                  * 128MB.
 337                  * NB: We can't write IDICR yet because we do not have gt funcs
 338                  * set up */
 339                 dev_priv->ellc_size = 128;
 340                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 341         }
 342
 343         /* clear out old GT FIFO errors */
 344         if (IS_GEN6(dev) || IS_GEN7(dev))
 345                 __raw_i915_write32(dev_priv, GTFIFODBG,
 346                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 347
 348         intel_uncore_forcewake_reset(dev, restore_forcewake);
 349 }
 350
 351 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 352 {
 353         __intel_uncore_early_sanitize(dev, restore_forcewake);
 354         i915_check_and_clear_faults(dev);
 355 }
 356
 357 void intel_uncore_sanitize(struct drm_device *dev)
 358 {
 359         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 360         intel_disable_gt_powersave(dev);
 361 }
 362
 363 /**
 364  * intel_uncore_forcewake_get - grab forcewake domain references
 365  * @dev_priv: i915 device instance
 366  * @fw_domains: forcewake domains to get reference on
 367  *
 368  * This function can be used get GT's forcewake domain references.
 369  * Normal register access will handle the forcewake domains automatically.
 370  * However if some sequence requires the GT to not power down a particular
 371  * forcewake domains this function should be called at the beginning of the
 372  * sequence. And subsequently the reference should be dropped by symmetric
 373  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 374  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 375  */
 376 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 377                                 enum forcewake_domains fw_domains)
 378 {
 379         unsigned long irqflags;
 380         struct intel_uncore_forcewake_domain *domain;
 381         enum forcewake_domain_id id;
 382
 383         if (!dev_priv->uncore.funcs.force_wake_get)
 384                 return;
 385
 386         WARN_ON(dev_priv->pm.suspended);
 387
 388         fw_domains &= dev_priv->uncore.fw_domains;
 389
 390         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 391
 392         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 393                 if (domain->wake_count++)
 394                         fw_domains &= ~(1 << id);
 395         }
 396
 397         if (fw_domains)
 398                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 399
 400         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 401 }
 402
 403 /**
 404  * intel_uncore_forcewake_put - release a forcewake domain reference
 405  * @dev_priv: i915 device instance
 406  * @fw_domains: forcewake domains to put references
 407  *
 408  * This function drops the device-level forcewakes for specified
 409  * domains obtained by intel_uncore_forcewake_get().
 410  */
 411 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 412                                 enum forcewake_domains fw_domains)
 413 {
 414         unsigned long irqflags;
 415         struct intel_uncore_forcewake_domain *domain;
 416         enum forcewake_domain_id id;
 417
 418         if (!dev_priv->uncore.funcs.force_wake_put)
 419                 return;
 420
 421         fw_domains &= dev_priv->uncore.fw_domains;
 422
 423         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 424
 425         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 426                 if (WARN_ON(domain->wake_count == 0))
 427                         continue;
 428
 429                 if (--domain->wake_count)
 430                         continue;
 431
 432                 domain->wake_count++;
 433                 fw_domain_arm_timer(domain);
 434         }
 435
 436         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 437 }
 438
 439 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 440 {
 441         struct intel_uncore_forcewake_domain *domain;
 442         enum forcewake_domain_id id;
 443
 444         if (!dev_priv->uncore.funcs.force_wake_get)
 445                 return;
 446
 447         for_each_fw_domain(domain, dev_priv, id)
 448                 WARN_ON(domain->wake_count);
 449 }
 450
 451 /* We give fast paths for the really cool registers */
 452 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 453          ((reg) < 0x40000 && (reg) != FORCEWAKE)
 454
 455 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 456
 457 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 458         (REG_RANGE((reg), 0x2000, 0x4000) || \
 459          REG_RANGE((reg), 0x5000, 0x8000) || \
 460          REG_RANGE((reg), 0xB000, 0x12000) || \
 461          REG_RANGE((reg), 0x2E000, 0x30000))
 462
 463 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 464         (REG_RANGE((reg), 0x12000, 0x14000) || \
 465          REG_RANGE((reg), 0x22000, 0x24000) || \
 466          REG_RANGE((reg), 0x30000, 0x40000))
 467
 468 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 469         (REG_RANGE((reg), 0x2000, 0x4000) || \
 470          REG_RANGE((reg), 0x5200, 0x8000) || \
 471          REG_RANGE((reg), 0x8300, 0x8500) || \
 472          REG_RANGE((reg), 0xB000, 0xB480) || \
 473          REG_RANGE((reg), 0xE000, 0xE800))
 474
 475 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 476         (REG_RANGE((reg), 0x8800, 0x8900) || \
 477          REG_RANGE((reg), 0xD000, 0xD800) || \
 478          REG_RANGE((reg), 0x12000, 0x14000) || \
 479          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 480          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 481          REG_RANGE((reg), 0x30000, 0x38000))
 482
 483 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 484         (REG_RANGE((reg), 0x4000, 0x5000) || \
 485          REG_RANGE((reg), 0x8000, 0x8300) || \
 486          REG_RANGE((reg), 0x8500, 0x8600) || \
 487          REG_RANGE((reg), 0x9000, 0xB000) || \
 488          REG_RANGE((reg), 0xF000, 0x10000))
 489
 490 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 491         REG_RANGE((reg), 0xB00,  0x2000)
 492
 493 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 494         (REG_RANGE((reg), 0x2000, 0x2700) || \
 495          REG_RANGE((reg), 0x3000, 0x4000) || \
 496          REG_RANGE((reg), 0x5200, 0x8000) || \
 497          REG_RANGE((reg), 0x8140, 0x8160) || \
 498          REG_RANGE((reg), 0x8300, 0x8500) || \
 499          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 500          REG_RANGE((reg), 0xB000, 0xB480) || \
 501          REG_RANGE((reg), 0xE000, 0xE900) || \
 502          REG_RANGE((reg), 0x24400, 0x24800))
 503
 504 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 505         (REG_RANGE((reg), 0x8130, 0x8140) || \
 506          REG_RANGE((reg), 0x8800, 0x8A00) || \
 507          REG_RANGE((reg), 0xD000, 0xD800) || \
 508          REG_RANGE((reg), 0x12000, 0x14000) || \
 509          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 510          REG_RANGE((reg), 0x30000, 0x40000))
 511
 512 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 513         REG_RANGE((reg), 0x9400, 0x9800)
 514
 515 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 516         ((reg) < 0x40000 &&\
 517          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 518          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 519          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 520          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 521
 522 static void
 523 ilk_dummy_write(struct drm_i915_private *dev_priv)
 524 {
 525         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 526          * the chip from rc6 before touching it for real. MI_MODE is masked,
 527          * hence harmless to write 0 into. */
 528         __raw_i915_write32(dev_priv, MI_MODE, 0);
 529 }
 530
 531 static void
 532 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
 533                         bool before)
 534 {
 535         const char *op = read ? "reading" : "writing to";
 536         const char *when = before ? "before" : "after";
 537
 538         if (!i915.mmio_debug)
 539                 return;
 540
 541         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 542                 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 543                      when, op, reg);
 544                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 545         }
 546 }
 547
 548 static void
 549 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 550 {
 551         if (i915.mmio_debug)
 552                 return;
 553
 554         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 555                 DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
 556                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 557         }
 558 }
 559
 560 #define GEN2_READ_HEADER(x) \
 561         u##x val = 0; \
 562         assert_device_not_suspended(dev_priv);
 563
 564 #define GEN2_READ_FOOTER \
 565         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 566         return val
 567
 568 #define __gen2_read(x) \
 569 static u##x \
 570 gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 571         GEN2_READ_HEADER(x); \
 572         val = __raw_i915_read##x(dev_priv, reg); \
 573         GEN2_READ_FOOTER; \
 574 }
 575
 576 #define __gen5_read(x) \
 577 static u##x \
 578 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 579         GEN2_READ_HEADER(x); \
 580         ilk_dummy_write(dev_priv); \
 581         val = __raw_i915_read##x(dev_priv, reg); \
 582         GEN2_READ_FOOTER; \
 583 }
 584
 585 __gen5_read(8)
 586 __gen5_read(16)
 587 __gen5_read(32)
 588 __gen5_read(64)
 589 __gen2_read(8)
 590 __gen2_read(16)
 591 __gen2_read(32)
 592 __gen2_read(64)
 593
 594 #undef __gen5_read
 595 #undef __gen2_read
 596
 597 #undef GEN2_READ_FOOTER
 598 #undef GEN2_READ_HEADER
 599
 600 #define GEN6_READ_HEADER(x) \
 601         unsigned long irqflags; \
 602         u##x val = 0; \
 603         assert_device_not_suspended(dev_priv); \
 604         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 605
 606 #define GEN6_READ_FOOTER \
 607         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 608         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 609         return val
 610
 611 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
 612                                     enum forcewake_domains fw_domains)
 613 {
 614         struct intel_uncore_forcewake_domain *domain;
 615         enum forcewake_domain_id id;
 616
 617         if (WARN_ON(!fw_domains))
 618                 return;
 619
 620         /* Ideally GCC would be constant-fold and eliminate this loop */
 621         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 622                 if (domain->wake_count) {
 623                         fw_domains &= ~(1 << id);
 624                         continue;
 625                 }
 626
 627                 domain->wake_count++;
 628                 fw_domain_arm_timer(domain);
 629         }
 630
 631         if (fw_domains)
 632                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 633 }
 634
 635 #define __gen6_read(x) \
 636 static u##x \
 637 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 638         GEN6_READ_HEADER(x); \
 639         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 640         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
 641                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 642         val = __raw_i915_read##x(dev_priv, reg); \
 643         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 644         GEN6_READ_FOOTER; \
 645 }
 646
 647 #define __vlv_read(x) \
 648 static u##x \
 649 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 650         GEN6_READ_HEADER(x); \
 651         if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
 652                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 653         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \
 654                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 655         val = __raw_i915_read##x(dev_priv, reg); \
 656         GEN6_READ_FOOTER; \
 657 }
 658
 659 #define __chv_read(x) \
 660 static u##x \
 661 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 662         GEN6_READ_HEADER(x); \
 663         if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 664                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 665         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 666                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 667         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 668                 __force_wake_get(dev_priv, \
 669                                  FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 670         val = __raw_i915_read##x(dev_priv, reg); \
 671         GEN6_READ_FOOTER; \
 672 }
 673
 674 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)     \
 675          ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 676
 677 #define __gen9_read(x) \
 678 static u##x \
 679 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 680         enum forcewake_domains fw_engine; \
 681         GEN6_READ_HEADER(x); \
 682         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)))   \
 683                 fw_engine = 0; \
 684         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg))       \
 685                 fw_engine = FORCEWAKE_RENDER; \
 686         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 687                 fw_engine = FORCEWAKE_MEDIA; \
 688         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 689                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 690         else \
 691                 fw_engine = FORCEWAKE_BLITTER; \
 692         if (fw_engine) \
 693                 __force_wake_get(dev_priv, fw_engine); \
 694         val = __raw_i915_read##x(dev_priv, reg); \
 695         GEN6_READ_FOOTER; \
 696 }
 697
 698 __gen9_read(8)
 699 __gen9_read(16)
 700 __gen9_read(32)
 701 __gen9_read(64)
 702 __chv_read(8)
 703 __chv_read(16)
 704 __chv_read(32)
 705 __chv_read(64)
 706 __vlv_read(8)
 707 __vlv_read(16)
 708 __vlv_read(32)
 709 __vlv_read(64)
 710 __gen6_read(8)
 711 __gen6_read(16)
 712 __gen6_read(32)
 713 __gen6_read(64)
 714
 715 #undef __gen9_read
 716 #undef __chv_read
 717 #undef __vlv_read
 718 #undef __gen6_read
 719 #undef GEN6_READ_FOOTER
 720 #undef GEN6_READ_HEADER
 721
 722 #define GEN2_WRITE_HEADER \
 723         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 724         assert_device_not_suspended(dev_priv); \
 725
 726 #define GEN2_WRITE_FOOTER
 727
 728 #define __gen2_write(x) \
 729 static void \
 730 gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 731         GEN2_WRITE_HEADER; \
 732         __raw_i915_write##x(dev_priv, reg, val); \
 733         GEN2_WRITE_FOOTER; \
 734 }
 735
 736 #define __gen5_write(x) \
 737 static void \
 738 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 739         GEN2_WRITE_HEADER; \
 740         ilk_dummy_write(dev_priv); \
 741         __raw_i915_write##x(dev_priv, reg, val); \
 742         GEN2_WRITE_FOOTER; \
 743 }
 744
 745 __gen5_write(8)
 746 __gen5_write(16)
 747 __gen5_write(32)
 748 __gen5_write(64)
 749 __gen2_write(8)
 750 __gen2_write(16)
 751 __gen2_write(32)
 752 __gen2_write(64)
 753
 754 #undef __gen5_write
 755 #undef __gen2_write
 756
 757 #undef GEN2_WRITE_FOOTER
 758 #undef GEN2_WRITE_HEADER
 759
 760 #define GEN6_WRITE_HEADER \
 761         unsigned long irqflags; \
 762         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 763         assert_device_not_suspended(dev_priv); \
 764         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 765
 766 #define GEN6_WRITE_FOOTER \
 767         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 768
 769 #define __gen6_write(x) \
 770 static void \
 771 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 772         u32 __fifo_ret = 0; \
 773         GEN6_WRITE_HEADER; \
 774         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 775                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 776         } \
 777         __raw_i915_write##x(dev_priv, reg, val); \
 778         if (unlikely(__fifo_ret)) { \
 779                 gen6_gt_check_fifodbg(dev_priv); \
 780         } \
 781         GEN6_WRITE_FOOTER; \
 782 }
 783
 784 #define __hsw_write(x) \
 785 static void \
 786 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 787         u32 __fifo_ret = 0; \
 788         GEN6_WRITE_HEADER; \
 789         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 790                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 791         } \
 792         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 793         __raw_i915_write##x(dev_priv, reg, val); \
 794         if (unlikely(__fifo_ret)) { \
 795                 gen6_gt_check_fifodbg(dev_priv); \
 796         } \
 797         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 798         hsw_unclaimed_reg_detect(dev_priv); \
 799         GEN6_WRITE_FOOTER; \
 800 }
 801
 802 static const u32 gen8_shadowed_regs[] = {
 803         FORCEWAKE_MT,
 804         GEN6_RPNSWREQ,
 805         GEN6_RC_VIDEO_FREQ,
 806         RING_TAIL(RENDER_RING_BASE),
 807         RING_TAIL(GEN6_BSD_RING_BASE),
 808         RING_TAIL(VEBOX_RING_BASE),
 809         RING_TAIL(BLT_RING_BASE),
 810         /* TODO: Other registers are not yet used */
 811 };
 812
 813 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 814 {
 815         int i;
 816         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 817                 if (reg == gen8_shadowed_regs[i])
 818                         return true;
 819
 820         return false;
 821 }
 822
 823 #define __gen8_write(x) \
 824 static void \
 825 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 826         GEN6_WRITE_HEADER; \
 827         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 828         if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
 829                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 830         __raw_i915_write##x(dev_priv, reg, val); \
 831         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 832         hsw_unclaimed_reg_detect(dev_priv); \
 833         GEN6_WRITE_FOOTER; \
 834 }
 835
 836 #define __chv_write(x) \
 837 static void \
 838 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 839         bool shadowed = is_gen8_shadowed(dev_priv, reg); \
 840         GEN6_WRITE_HEADER; \
 841         if (!shadowed) { \
 842                 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 843                         __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 844                 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 845                         __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 846                 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 847                         __force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 848         } \
 849         __raw_i915_write##x(dev_priv, reg, val); \
 850         GEN6_WRITE_FOOTER; \
 851 }
 852
 853 static const u32 gen9_shadowed_regs[] = {
 854         RING_TAIL(RENDER_RING_BASE),
 855         RING_TAIL(GEN6_BSD_RING_BASE),
 856         RING_TAIL(VEBOX_RING_BASE),
 857         RING_TAIL(BLT_RING_BASE),
 858         FORCEWAKE_BLITTER_GEN9,
 859         FORCEWAKE_RENDER_GEN9,
 860         FORCEWAKE_MEDIA_GEN9,
 861         GEN6_RPNSWREQ,
 862         GEN6_RC_VIDEO_FREQ,
 863         /* TODO: Other registers are not yet used */
 864 };
 865
 866 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 867 {
 868         int i;
 869         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 870                 if (reg == gen9_shadowed_regs[i])
 871                         return true;
 872
 873         return false;
 874 }
 875
 876 #define __gen9_write(x) \
 877 static void \
 878 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
 879                 bool trace) { \
 880         enum forcewake_domains fw_engine; \
 881         GEN6_WRITE_HEADER; \
 882         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
 883             is_gen9_shadowed(dev_priv, reg)) \
 884                 fw_engine = 0; \
 885         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
 886                 fw_engine = FORCEWAKE_RENDER; \
 887         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 888                 fw_engine = FORCEWAKE_MEDIA; \
 889         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 890                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 891         else \
 892                 fw_engine = FORCEWAKE_BLITTER; \
 893         if (fw_engine) \
 894                 __force_wake_get(dev_priv, fw_engine); \
 895         __raw_i915_write##x(dev_priv, reg, val); \
 896         GEN6_WRITE_FOOTER; \
 897 }
 898
 899 __gen9_write(8)
 900 __gen9_write(16)
 901 __gen9_write(32)
 902 __gen9_write(64)
 903 __chv_write(8)
 904 __chv_write(16)
 905 __chv_write(32)
 906 __chv_write(64)
 907 __gen8_write(8)
 908 __gen8_write(16)
 909 __gen8_write(32)
 910 __gen8_write(64)
 911 __hsw_write(8)
 912 __hsw_write(16)
 913 __hsw_write(32)
 914 __hsw_write(64)
 915 __gen6_write(8)
 916 __gen6_write(16)
 917 __gen6_write(32)
 918 __gen6_write(64)
 919
 920 #undef __gen9_write
 921 #undef __chv_write
 922 #undef __gen8_write
 923 #undef __hsw_write
 924 #undef __gen6_write
 925 #undef GEN6_WRITE_FOOTER
 926 #undef GEN6_WRITE_HEADER
 927
 928 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
 929 do { \
 930         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
 931         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
 932         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
 933         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
 934 } while (0)
 935
 936 #define ASSIGN_READ_MMIO_VFUNCS(x) \
 937 do { \
 938         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
 939         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
 940         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
 941         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
 942 } while (0)
 943
 944
 945 static void fw_domain_init(struct drm_i915_private *dev_priv,
 946                            enum forcewake_domain_id domain_id,
 947                            u32 reg_set, u32 reg_ack)
 948 {
 949         struct intel_uncore_forcewake_domain *d;
 950
 951         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
 952                 return;
 953
 954         d = &dev_priv->uncore.fw_domain[domain_id];
 955
 956         WARN_ON(d->wake_count);
 957
 958         d->wake_count = 0;
 959         d->reg_set = reg_set;
 960         d->reg_ack = reg_ack;
 961
 962         if (IS_GEN6(dev_priv)) {
 963                 d->val_reset = 0;
 964                 d->val_set = FORCEWAKE_KERNEL;
 965                 d->val_clear = 0;
 966         } else {
 967                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
 968                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
 969                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
 970         }
 971
 972         if (IS_VALLEYVIEW(dev_priv))
 973                 d->reg_post = FORCEWAKE_ACK_VLV;
 974         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
 975                 d->reg_post = ECOBUS;
 976         else
 977                 d->reg_post = 0;
 978
 979         d->i915 = dev_priv;
 980         d->id = domain_id;
 981
 982         setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
 983
 984         dev_priv->uncore.fw_domains |= (1 << domain_id);
 985 }
 986
 987 void intel_uncore_init(struct drm_device *dev)
 988 {
 989         struct drm_i915_private *dev_priv = dev->dev_private;
 990
 991         __intel_uncore_early_sanitize(dev, false);
 992
 993         if (IS_GEN9(dev)) {
 994                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
 995                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
 996                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
 997                                FORCEWAKE_RENDER_GEN9,
 998                                FORCEWAKE_ACK_RENDER_GEN9);
 999                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1000                                FORCEWAKE_BLITTER_GEN9,
1001                                FORCEWAKE_ACK_BLITTER_GEN9);
1002                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1003                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1004         } else if (IS_VALLEYVIEW(dev)) {
1005                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1006                 if (!IS_CHERRYVIEW(dev))
1007                         dev_priv->uncore.funcs.force_wake_put =
1008                                 fw_domains_put_with_fifo;
1009                 else
1010                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1011                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1012                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1013                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1014                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1015         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1016                 dev_priv->uncore.funcs.force_wake_get =
1017                         fw_domains_get_with_thread_status;
1018                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1019                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1020                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1021         } else if (IS_IVYBRIDGE(dev)) {
1022                 u32 ecobus;
1023
1024                 /* IVB configs may use multi-threaded forcewake */
1025
1026                 /* A small trick here - if the bios hasn't configured
1027                  * MT forcewake, and if the device is in RC6, then
1028                  * force_wake_mt_get will not wake the device and the
1029                  * ECOBUS read will return zero. Which will be
1030                  * (correctly) interpreted by the test below as MT
1031                  * forcewake being disabled.
1032                  */
1033                 dev_priv->uncore.funcs.force_wake_get =
1034                         fw_domains_get_with_thread_status;
1035                 dev_priv->uncore.funcs.force_wake_put =
1036                         fw_domains_put_with_fifo;
1037
1038                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1039                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1040                 mutex_lock(&dev->struct_mutex);
1041                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1042                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1043                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1044                 mutex_unlock(&dev->struct_mutex);
1045
1046                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1047                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1048                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1049                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1050                                        FORCEWAKE, FORCEWAKE_ACK);
1051                 }
1052         } else if (IS_GEN6(dev)) {
1053                 dev_priv->uncore.funcs.force_wake_get =
1054                         fw_domains_get_with_thread_status;
1055                 dev_priv->uncore.funcs.force_wake_put =
1056                         fw_domains_put_with_fifo;
1057                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1058                                FORCEWAKE, FORCEWAKE_ACK);
1059         }
1060
1061         switch (INTEL_INFO(dev)->gen) {
1062         default:
1063                 MISSING_CASE(INTEL_INFO(dev)->gen);
1064                 return;
1065         case 9:
1066                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1067                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1068                 break;
1069         case 8:
1070                 if (IS_CHERRYVIEW(dev)) {
1071                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1072                         ASSIGN_READ_MMIO_VFUNCS(chv);
1073
1074                 } else {
1075                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1076                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1077                 }
1078                 break;
1079         case 7:
1080         case 6:
1081                 if (IS_HASWELL(dev)) {
1082                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1083                 } else {
1084                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1085                 }
1086
1087                 if (IS_VALLEYVIEW(dev)) {
1088                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1089                 } else {
1090                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1091                 }
1092                 break;
1093         case 5:
1094                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1095                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1096                 break;
1097         case 4:
1098         case 3:
1099         case 2:
1100                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1101                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1102                 break;
1103         }
1104
1105         i915_check_and_clear_faults(dev);
1106 }
1107 #undef ASSIGN_WRITE_MMIO_VFUNCS
1108 #undef ASSIGN_READ_MMIO_VFUNCS
1109
1110 void intel_uncore_fini(struct drm_device *dev)
1111 {
1112         /* Paranoia: make sure we have disabled everything before we exit. */
1113         intel_uncore_sanitize(dev);
1114         intel_uncore_forcewake_reset(dev, false);
1115 }
1116
1117 #define GEN_RANGE(l, h) GENMASK(h, l)
1118
1119 static const struct register_whitelist {
1120         uint64_t offset;
1121         uint32_t size;
1122         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1123         uint32_t gen_bitmask;
1124 } whitelist[] = {
1125         { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1126 };
1127
1128 int i915_reg_read_ioctl(struct drm_device *dev,
1129                         void *data, struct drm_file *file)
1130 {
1131         struct drm_i915_private *dev_priv = dev->dev_private;
1132         struct drm_i915_reg_read *reg = data;
1133         struct register_whitelist const *entry = whitelist;
1134         int i, ret = 0;
1135
1136         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1137                 if (entry->offset == reg->offset &&
1138                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1139                         break;
1140         }
1141
1142         if (i == ARRAY_SIZE(whitelist))
1143                 return -EINVAL;
1144
1145         intel_runtime_pm_get(dev_priv);
1146
1147         switch (entry->size) {
1148         case 8:
1149                 reg->val = I915_READ64(reg->offset);
1150                 break;
1151         case 4:
1152                 reg->val = I915_READ(reg->offset);
1153                 break;
1154         case 2:
1155                 reg->val = I915_READ16(reg->offset);
1156                 break;
1157         case 1:
1158                 reg->val = I915_READ8(reg->offset);
1159                 break;
1160         default:
1161                 MISSING_CASE(entry->size);
1162                 ret = -EINVAL;
1163                 goto out;
1164         }
1165
1166 out:
1167         intel_runtime_pm_put(dev_priv);
1168         return ret;
1169 }
1170
1171 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1172                                void *data, struct drm_file *file)
1173 {
1174         struct drm_i915_private *dev_priv = dev->dev_private;
1175         struct drm_i915_reset_stats *args = data;
1176         struct i915_ctx_hang_stats *hs;
1177         struct intel_context *ctx;
1178         int ret;
1179
1180         if (args->flags || args->pad)
1181                 return -EINVAL;
1182
1183         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1184                 return -EPERM;
1185
1186         ret = mutex_lock_interruptible(&dev->struct_mutex);
1187         if (ret)
1188                 return ret;
1189
1190         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1191         if (IS_ERR(ctx)) {
1192                 mutex_unlock(&dev->struct_mutex);
1193                 return PTR_ERR(ctx);
1194         }
1195         hs = &ctx->hang_stats;
1196
1197         if (capable(CAP_SYS_ADMIN))
1198                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1199         else
1200                 args->reset_count = 0;
1201
1202         args->batch_active = hs->batch_active;
1203         args->batch_pending = hs->batch_pending;
1204
1205         mutex_unlock(&dev->struct_mutex);
1206
1207         return 0;
1208 }
1209
1210 static int i915_reset_complete(struct drm_device *dev)
1211 {
1212         u8 gdrst;
1213         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1214         return (gdrst & GRDOM_RESET_STATUS) == 0;
1215 }
1216
1217 static int i915_do_reset(struct drm_device *dev)
1218 {
1219         /* assert reset for at least 20 usec */
1220         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1221         udelay(20);
1222         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1223
1224         return wait_for(i915_reset_complete(dev), 500);
1225 }
1226
1227 static int g4x_reset_complete(struct drm_device *dev)
1228 {
1229         u8 gdrst;
1230         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1231         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1232 }
1233
1234 static int g33_do_reset(struct drm_device *dev)
1235 {
1236         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1237         return wait_for(g4x_reset_complete(dev), 500);
1238 }
1239
1240 static int g4x_do_reset(struct drm_device *dev)
1241 {
1242         struct drm_i915_private *dev_priv = dev->dev_private;
1243         int ret;
1244
1245         pci_write_config_byte(dev->pdev, I915_GDRST,
1246                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1247         ret =  wait_for(g4x_reset_complete(dev), 500);
1248         if (ret)
1249                 return ret;
1250
1251         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1252         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1253         POSTING_READ(VDECCLK_GATE_D);
1254
1255         pci_write_config_byte(dev->pdev, I915_GDRST,
1256                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1257         ret =  wait_for(g4x_reset_complete(dev), 500);
1258         if (ret)
1259                 return ret;
1260
1261         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1262         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1263         POSTING_READ(VDECCLK_GATE_D);
1264
1265         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1266
1267         return 0;
1268 }
1269
1270 static int ironlake_do_reset(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         int ret;
1274
1275         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1276                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1277         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1278                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1279         if (ret)
1280                 return ret;
1281
1282         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1283                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1284         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1285                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1286         if (ret)
1287                 return ret;
1288
1289         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1290
1291         return 0;
1292 }
1293
1294 static int gen6_do_reset(struct drm_device *dev)
1295 {
1296         struct drm_i915_private *dev_priv = dev->dev_private;
1297         int     ret;
1298
1299         /* Reset the chip */
1300
1301         /* GEN6_GDRST is not in the gt power well, no need to check
1302          * for fifo space for the write or forcewake the chip for
1303          * the read
1304          */
1305         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1306
1307         /* Spin waiting for the device to ack the reset request */
1308         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1309
1310         intel_uncore_forcewake_reset(dev, true);
1311
1312         return ret;
1313 }
1314
1315 int intel_gpu_reset(struct drm_device *dev)
1316 {
1317         if (INTEL_INFO(dev)->gen >= 6)
1318                 return gen6_do_reset(dev);
1319         else if (IS_GEN5(dev))
1320                 return ironlake_do_reset(dev);
1321         else if (IS_G4X(dev))
1322                 return g4x_do_reset(dev);
1323         else if (IS_G33(dev))
1324                 return g33_do_reset(dev);
1325         else if (INTEL_INFO(dev)->gen >= 3)
1326                 return i915_do_reset(dev);
1327         else
1328                 return -ENODEV;
1329 }
1330
1331 void intel_uncore_check_errors(struct drm_device *dev)
1332 {
1333         struct drm_i915_private *dev_priv = dev->dev_private;
1334
1335         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1336             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1337                 DRM_ERROR("Unclaimed register before interrupt\n");
1338                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1339         }
1340 }