drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26
  27 #include <linux/pm_runtime.h>
  28
  29 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  30
  31 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
  32 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
  33
  34 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
  35 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
  36
  37 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  38 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
  39
  40 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
  41 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
  42
  43 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  44
  45 static void
  46 assert_device_not_suspended(struct drm_i915_private *dev_priv)
  47 {
  48         WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
  49                   "Device suspended\n");
  50 }
  51
  52 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
  53 {
  54         /* w/a for a sporadic read returning 0 by waiting for the GT
  55          * thread to wake up.
  56          */
  57         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
  58                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
  59                 DRM_ERROR("GT thread status wait timed out\n");
  60 }
  61
  62 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
  63 {
  64         __raw_i915_write32(dev_priv, FORCEWAKE, 0);
  65         /* something from same cacheline, but !FORCEWAKE */
  66         __raw_posting_read(dev_priv, ECOBUS);
  67 }
  68
  69 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
  70                                                         int fw_engine)
  71 {
  72         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
  73                             FORCEWAKE_ACK_TIMEOUT_MS))
  74                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
  75
  76         __raw_i915_write32(dev_priv, FORCEWAKE, 1);
  77         /* something from same cacheline, but !FORCEWAKE */
  78         __raw_posting_read(dev_priv, ECOBUS);
  79
  80         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
  81                             FORCEWAKE_ACK_TIMEOUT_MS))
  82                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
  83
  84         /* WaRsForcewakeWaitTC0:snb */
  85         __gen6_gt_wait_for_thread_c0(dev_priv);
  86 }
  87
  88 static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
  89 {
  90         __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
  91         /* something from same cacheline, but !FORCEWAKE_MT */
  92         __raw_posting_read(dev_priv, ECOBUS);
  93 }
  94
  95 static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
  96                                                         int fw_engine)
  97 {
  98         u32 forcewake_ack;
  99
 100         if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev))
 101                 forcewake_ack = FORCEWAKE_ACK_HSW;
 102         else
 103                 forcewake_ack = FORCEWAKE_MT_ACK;
 104
 105         if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
 106                             FORCEWAKE_ACK_TIMEOUT_MS))
 107                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
 108
 109         __raw_i915_write32(dev_priv, FORCEWAKE_MT,
 110                            _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 111         /* something from same cacheline, but !FORCEWAKE_MT */
 112         __raw_posting_read(dev_priv, ECOBUS);
 113
 114         if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
 115                             FORCEWAKE_ACK_TIMEOUT_MS))
 116                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
 117
 118         /* WaRsForcewakeWaitTC0:ivb,hsw */
 119         __gen6_gt_wait_for_thread_c0(dev_priv);
 120 }
 121
 122 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 123 {
 124         u32 gtfifodbg;
 125
 126         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 127         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 128                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 129 }
 130
 131 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
 132                                                         int fw_engine)
 133 {
 134         __raw_i915_write32(dev_priv, FORCEWAKE, 0);
 135         /* something from same cacheline, but !FORCEWAKE */
 136         __raw_posting_read(dev_priv, ECOBUS);
 137         gen6_gt_check_fifodbg(dev_priv);
 138 }
 139
 140 static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
 141                                                         int fw_engine)
 142 {
 143         __raw_i915_write32(dev_priv, FORCEWAKE_MT,
 144                            _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 145         /* something from same cacheline, but !FORCEWAKE_MT */
 146         __raw_posting_read(dev_priv, ECOBUS);
 147
 148         if (IS_GEN7(dev_priv->dev))
 149                 gen6_gt_check_fifodbg(dev_priv);
 150 }
 151
 152 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 153 {
 154         int ret = 0;
 155
 156         /* On VLV, FIFO will be shared by both SW and HW.
 157          * So, we need to read the FREE_ENTRIES everytime */
 158         if (IS_VALLEYVIEW(dev_priv->dev))
 159                 dev_priv->uncore.fifo_count =
 160                         __raw_i915_read32(dev_priv, GTFIFOCTL) &
 161                                                 GT_FIFO_FREE_ENTRIES_MASK;
 162
 163         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 164                 int loop = 500;
 165                 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 166                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 167                         udelay(10);
 168                         fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 169                 }
 170                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 171                         ++ret;
 172                 dev_priv->uncore.fifo_count = fifo;
 173         }
 174         dev_priv->uncore.fifo_count--;
 175
 176         return ret;
 177 }
 178
 179 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
 180 {
 181         __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 182                            _MASKED_BIT_DISABLE(0xffff));
 183         __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 184                            _MASKED_BIT_DISABLE(0xffff));
 185         /* something from same cacheline, but !FORCEWAKE_VLV */
 186         __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
 187 }
 188
 189 static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
 190                                                 int fw_engine)
 191 {
 192         /* Check for Render Engine */
 193         if (FORCEWAKE_RENDER & fw_engine) {
 194                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 195                                                 FORCEWAKE_ACK_VLV) &
 196                                                 FORCEWAKE_KERNEL) == 0,
 197                                         FORCEWAKE_ACK_TIMEOUT_MS))
 198                         DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
 199
 200                 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 201                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 202
 203                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 204                                                 FORCEWAKE_ACK_VLV) &
 205                                                 FORCEWAKE_KERNEL),
 206                                         FORCEWAKE_ACK_TIMEOUT_MS))
 207                         DRM_ERROR("Timed out: waiting for Render to ack.\n");
 208         }
 209
 210         /* Check for Media Engine */
 211         if (FORCEWAKE_MEDIA & fw_engine) {
 212                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 213                                                 FORCEWAKE_ACK_MEDIA_VLV) &
 214                                                 FORCEWAKE_KERNEL) == 0,
 215                                         FORCEWAKE_ACK_TIMEOUT_MS))
 216                         DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
 217
 218                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 219                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 220
 221                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 222                                                 FORCEWAKE_ACK_MEDIA_VLV) &
 223                                                 FORCEWAKE_KERNEL),
 224                                         FORCEWAKE_ACK_TIMEOUT_MS))
 225                         DRM_ERROR("Timed out: waiting for media to ack.\n");
 226         }
 227 }
 228
 229 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
 230                                         int fw_engine)
 231 {
 232
 233         /* Check for Render Engine */
 234         if (FORCEWAKE_RENDER & fw_engine)
 235                 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 236                                         _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 237
 238
 239         /* Check for Media Engine */
 240         if (FORCEWAKE_MEDIA & fw_engine)
 241                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 242                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 243
 244         /* something from same cacheline, but !FORCEWAKE_VLV */
 245         __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
 246         if (!IS_CHERRYVIEW(dev_priv->dev))
 247                 gen6_gt_check_fifodbg(dev_priv);
 248 }
 249
 250 static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 251 {
 252         if (fw_engine & FORCEWAKE_RENDER &&
 253             dev_priv->uncore.fw_rendercount++ != 0)
 254                 fw_engine &= ~FORCEWAKE_RENDER;
 255         if (fw_engine & FORCEWAKE_MEDIA &&
 256             dev_priv->uncore.fw_mediacount++ != 0)
 257                 fw_engine &= ~FORCEWAKE_MEDIA;
 258
 259         if (fw_engine)
 260                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
 261 }
 262
 263 static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 264 {
 265         if (fw_engine & FORCEWAKE_RENDER) {
 266                 WARN_ON(!dev_priv->uncore.fw_rendercount);
 267                 if (--dev_priv->uncore.fw_rendercount != 0)
 268                         fw_engine &= ~FORCEWAKE_RENDER;
 269         }
 270
 271         if (fw_engine & FORCEWAKE_MEDIA) {
 272                 WARN_ON(!dev_priv->uncore.fw_mediacount);
 273                 if (--dev_priv->uncore.fw_mediacount != 0)
 274                         fw_engine &= ~FORCEWAKE_MEDIA;
 275         }
 276
 277         if (fw_engine)
 278                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine);
 279 }
 280
 281 static void __gen9_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
 282 {
 283         __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
 284                         _MASKED_BIT_DISABLE(0xffff));
 285
 286         __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
 287                         _MASKED_BIT_DISABLE(0xffff));
 288
 289         __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
 290                         _MASKED_BIT_DISABLE(0xffff));
 291 }
 292
 293 static void
 294 __gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 295 {
 296         /* Check for Render Engine */
 297         if (FORCEWAKE_RENDER & fw_engine) {
 298                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 299                                                 FORCEWAKE_ACK_RENDER_GEN9) &
 300                                                 FORCEWAKE_KERNEL) == 0,
 301                                         FORCEWAKE_ACK_TIMEOUT_MS))
 302                         DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
 303
 304                 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
 305                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 306
 307                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 308                                                 FORCEWAKE_ACK_RENDER_GEN9) &
 309                                                 FORCEWAKE_KERNEL),
 310                                         FORCEWAKE_ACK_TIMEOUT_MS))
 311                         DRM_ERROR("Timed out: waiting for Render to ack.\n");
 312         }
 313
 314         /* Check for Media Engine */
 315         if (FORCEWAKE_MEDIA & fw_engine) {
 316                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 317                                                 FORCEWAKE_ACK_MEDIA_GEN9) &
 318                                                 FORCEWAKE_KERNEL) == 0,
 319                                         FORCEWAKE_ACK_TIMEOUT_MS))
 320                         DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
 321
 322                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
 323                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 324
 325                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 326                                                 FORCEWAKE_ACK_MEDIA_GEN9) &
 327                                                 FORCEWAKE_KERNEL),
 328                                         FORCEWAKE_ACK_TIMEOUT_MS))
 329                         DRM_ERROR("Timed out: waiting for Media to ack.\n");
 330         }
 331
 332         /* Check for Blitter Engine */
 333         if (FORCEWAKE_BLITTER & fw_engine) {
 334                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 335                                                 FORCEWAKE_ACK_BLITTER_GEN9) &
 336                                                 FORCEWAKE_KERNEL) == 0,
 337                                         FORCEWAKE_ACK_TIMEOUT_MS))
 338                         DRM_ERROR("Timed out: Blitter forcewake old ack to clear.\n");
 339
 340                 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
 341                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 342
 343                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 344                                                 FORCEWAKE_ACK_BLITTER_GEN9) &
 345                                                 FORCEWAKE_KERNEL),
 346                                         FORCEWAKE_ACK_TIMEOUT_MS))
 347                         DRM_ERROR("Timed out: waiting for Blitter to ack.\n");
 348         }
 349 }
 350
 351 static void
 352 __gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 353 {
 354         /* Check for Render Engine */
 355         if (FORCEWAKE_RENDER & fw_engine)
 356                 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
 357                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 358
 359         /* Check for Media Engine */
 360         if (FORCEWAKE_MEDIA & fw_engine)
 361                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
 362                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 363
 364         /* Check for Blitter Engine */
 365         if (FORCEWAKE_BLITTER & fw_engine)
 366                 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
 367                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 368 }
 369
 370 static void
 371 gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 372 {
 373         if (FORCEWAKE_RENDER & fw_engine) {
 374                 if (dev_priv->uncore.fw_rendercount++ == 0)
 375                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 376                                                         FORCEWAKE_RENDER);
 377         }
 378
 379         if (FORCEWAKE_MEDIA & fw_engine) {
 380                 if (dev_priv->uncore.fw_mediacount++ == 0)
 381                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 382                                                         FORCEWAKE_MEDIA);
 383         }
 384
 385         if (FORCEWAKE_BLITTER & fw_engine) {
 386                 if (dev_priv->uncore.fw_blittercount++ == 0)
 387                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 388                                                         FORCEWAKE_BLITTER);
 389         }
 390 }
 391
 392 static void
 393 gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 394 {
 395         if (FORCEWAKE_RENDER & fw_engine) {
 396                 WARN_ON(dev_priv->uncore.fw_rendercount == 0);
 397                 if (--dev_priv->uncore.fw_rendercount == 0)
 398                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 399                                                         FORCEWAKE_RENDER);
 400         }
 401
 402         if (FORCEWAKE_MEDIA & fw_engine) {
 403                 WARN_ON(dev_priv->uncore.fw_mediacount == 0);
 404                 if (--dev_priv->uncore.fw_mediacount == 0)
 405                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 406                                                         FORCEWAKE_MEDIA);
 407         }
 408
 409         if (FORCEWAKE_BLITTER & fw_engine) {
 410                 WARN_ON(dev_priv->uncore.fw_blittercount == 0);
 411                 if (--dev_priv->uncore.fw_blittercount == 0)
 412                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 413                                                         FORCEWAKE_BLITTER);
 414         }
 415 }
 416
 417 static void gen6_force_wake_timer(unsigned long arg)
 418 {
 419         struct drm_i915_private *dev_priv = (void *)arg;
 420         unsigned long irqflags;
 421
 422         assert_device_not_suspended(dev_priv);
 423
 424         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 425         WARN_ON(!dev_priv->uncore.forcewake_count);
 426
 427         if (--dev_priv->uncore.forcewake_count == 0)
 428                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
 429         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 430 }
 431
 432 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 433 {
 434         struct drm_i915_private *dev_priv = dev->dev_private;
 435         unsigned long irqflags;
 436
 437         if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
 438                 gen6_force_wake_timer((unsigned long)dev_priv);
 439
 440         /* Hold uncore.lock across reset to prevent any register access
 441          * with forcewake not set correctly
 442          */
 443         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 444
 445         if (IS_VALLEYVIEW(dev))
 446                 vlv_force_wake_reset(dev_priv);
 447         else if (IS_GEN6(dev) || IS_GEN7(dev))
 448                 __gen6_gt_force_wake_reset(dev_priv);
 449
 450         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
 451                 __gen7_gt_force_wake_mt_reset(dev_priv);
 452
 453         if (IS_GEN9(dev))
 454                 __gen9_gt_force_wake_mt_reset(dev_priv);
 455
 456         if (restore) { /* If reset with a user forcewake, try to restore */
 457                 unsigned fw = 0;
 458
 459                 if (IS_VALLEYVIEW(dev)) {
 460                         if (dev_priv->uncore.fw_rendercount)
 461                                 fw |= FORCEWAKE_RENDER;
 462
 463                         if (dev_priv->uncore.fw_mediacount)
 464                                 fw |= FORCEWAKE_MEDIA;
 465                 } else if (IS_GEN9(dev)) {
 466                         if (dev_priv->uncore.fw_rendercount)
 467                                 fw |= FORCEWAKE_RENDER;
 468
 469                         if (dev_priv->uncore.fw_mediacount)
 470                                 fw |= FORCEWAKE_MEDIA;
 471
 472                         if (dev_priv->uncore.fw_blittercount)
 473                                 fw |= FORCEWAKE_BLITTER;
 474                 } else {
 475                         if (dev_priv->uncore.forcewake_count)
 476                                 fw = FORCEWAKE_ALL;
 477                 }
 478
 479                 if (fw)
 480                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 481
 482                 if (IS_GEN6(dev) || IS_GEN7(dev))
 483                         dev_priv->uncore.fifo_count =
 484                                 __raw_i915_read32(dev_priv, GTFIFOCTL) &
 485                                 GT_FIFO_FREE_ENTRIES_MASK;
 486         }
 487
 488         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 489 }
 490
 491 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 492                                           bool restore_forcewake)
 493 {
 494         struct drm_i915_private *dev_priv = dev->dev_private;
 495
 496         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 497                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 498
 499         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
 500             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
 501                 /* The docs do not explain exactly how the calculation can be
 502                  * made. It is somewhat guessable, but for now, it's always
 503                  * 128MB.
 504                  * NB: We can't write IDICR yet because we do not have gt funcs
 505                  * set up */
 506                 dev_priv->ellc_size = 128;
 507                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 508         }
 509
 510         /* clear out old GT FIFO errors */
 511         if (IS_GEN6(dev) || IS_GEN7(dev))
 512                 __raw_i915_write32(dev_priv, GTFIFODBG,
 513                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 514
 515         intel_uncore_forcewake_reset(dev, restore_forcewake);
 516 }
 517
 518 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 519 {
 520         __intel_uncore_early_sanitize(dev, restore_forcewake);
 521         i915_check_and_clear_faults(dev);
 522 }
 523
 524 void intel_uncore_sanitize(struct drm_device *dev)
 525 {
 526         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 527         intel_disable_gt_powersave(dev);
 528 }
 529
 530 /*
 531  * Generally this is called implicitly by the register read function. However,
 532  * if some sequence requires the GT to not power down then this function should
 533  * be called at the beginning of the sequence followed by a call to
 534  * gen6_gt_force_wake_put() at the end of the sequence.
 535  */
 536 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 537 {
 538         unsigned long irqflags;
 539
 540         if (!dev_priv->uncore.funcs.force_wake_get)
 541                 return;
 542
 543         WARN_ON(dev_priv->pm.suspended);
 544
 545         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 546
 547         if (IS_GEN9(dev_priv->dev)) {
 548                 gen9_force_wake_get(dev_priv, fw_engine);
 549         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
 550                 vlv_force_wake_get(dev_priv, fw_engine);
 551         } else {
 552                 if (dev_priv->uncore.forcewake_count++ == 0)
 553                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 554                                                               FORCEWAKE_ALL);
 555         }
 556
 557         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 558 }
 559
 560 /*
 561  * see gen6_gt_force_wake_get()
 562  */
 563 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 564 {
 565         unsigned long irqflags;
 566
 567         if (!dev_priv->uncore.funcs.force_wake_put)
 568                 return;
 569
 570         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 571
 572         if (IS_GEN9(dev_priv->dev)) {
 573                 gen9_force_wake_put(dev_priv, fw_engine);
 574         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
 575                 vlv_force_wake_put(dev_priv, fw_engine);
 576         } else {
 577                 WARN_ON(!dev_priv->uncore.forcewake_count);
 578                 if (--dev_priv->uncore.forcewake_count == 0) {
 579                         dev_priv->uncore.forcewake_count++;
 580                         mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
 581                                          jiffies + 1);
 582                 }
 583         }
 584
 585         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 586 }
 587
 588 void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
 589 {
 590         if (!dev_priv->uncore.funcs.force_wake_get)
 591                 return;
 592
 593         WARN_ON(dev_priv->uncore.forcewake_count > 0);
 594 }
 595
 596 /* We give fast paths for the really cool registers */
 597 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 598          ((reg) < 0x40000 && (reg) != FORCEWAKE)
 599
 600 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 601
 602 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 603         (REG_RANGE((reg), 0x2000, 0x4000) || \
 604          REG_RANGE((reg), 0x5000, 0x8000) || \
 605          REG_RANGE((reg), 0xB000, 0x12000) || \
 606          REG_RANGE((reg), 0x2E000, 0x30000))
 607
 608 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 609         (REG_RANGE((reg), 0x12000, 0x14000) || \
 610          REG_RANGE((reg), 0x22000, 0x24000) || \
 611          REG_RANGE((reg), 0x30000, 0x40000))
 612
 613 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 614         (REG_RANGE((reg), 0x2000, 0x4000) || \
 615          REG_RANGE((reg), 0x5200, 0x8000) || \
 616          REG_RANGE((reg), 0x8300, 0x8500) || \
 617          REG_RANGE((reg), 0xB000, 0xB480) || \
 618          REG_RANGE((reg), 0xE000, 0xE800))
 619
 620 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 621         (REG_RANGE((reg), 0x8800, 0x8900) || \
 622          REG_RANGE((reg), 0xD000, 0xD800) || \
 623          REG_RANGE((reg), 0x12000, 0x14000) || \
 624          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 625          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 626          REG_RANGE((reg), 0x30000, 0x38000))
 627
 628 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 629         (REG_RANGE((reg), 0x4000, 0x5000) || \
 630          REG_RANGE((reg), 0x8000, 0x8300) || \
 631          REG_RANGE((reg), 0x8500, 0x8600) || \
 632          REG_RANGE((reg), 0x9000, 0xB000) || \
 633          REG_RANGE((reg), 0xF000, 0x10000))
 634
 635 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 636         REG_RANGE((reg), 0xB00,  0x2000)
 637
 638 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 639         (REG_RANGE((reg), 0x2000, 0x2700) || \
 640          REG_RANGE((reg), 0x3000, 0x4000) || \
 641          REG_RANGE((reg), 0x5200, 0x8000) || \
 642          REG_RANGE((reg), 0x8140, 0x8160) || \
 643          REG_RANGE((reg), 0x8300, 0x8500) || \
 644          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 645          REG_RANGE((reg), 0xB000, 0xB480) || \
 646          REG_RANGE((reg), 0xE000, 0xE900) || \
 647          REG_RANGE((reg), 0x24400, 0x24800))
 648
 649 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 650         (REG_RANGE((reg), 0x8130, 0x8140) || \
 651          REG_RANGE((reg), 0x8800, 0x8A00) || \
 652          REG_RANGE((reg), 0xD000, 0xD800) || \
 653          REG_RANGE((reg), 0x12000, 0x14000) || \
 654          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 655          REG_RANGE((reg), 0x30000, 0x40000))
 656
 657 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 658         REG_RANGE((reg), 0x9400, 0x9800)
 659
 660 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 661         ((reg) < 0x40000 &&\
 662          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 663          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 664          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 665          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 666
 667 static void
 668 ilk_dummy_write(struct drm_i915_private *dev_priv)
 669 {
 670         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 671          * the chip from rc6 before touching it for real. MI_MODE is masked,
 672          * hence harmless to write 0 into. */
 673         __raw_i915_write32(dev_priv, MI_MODE, 0);
 674 }
 675
 676 static void
 677 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
 678                         bool before)
 679 {
 680         const char *op = read ? "reading" : "writing to";
 681         const char *when = before ? "before" : "after";
 682
 683         if (!i915.mmio_debug)
 684                 return;
 685
 686         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 687                 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 688                      when, op, reg);
 689                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 690         }
 691 }
 692
 693 static void
 694 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 695 {
 696         if (i915.mmio_debug)
 697                 return;
 698
 699         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 700                 DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
 701                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 702         }
 703 }
 704
 705 #define GEN2_READ_HEADER(x) \
 706         u##x val = 0; \
 707         assert_device_not_suspended(dev_priv);
 708
 709 #define GEN2_READ_FOOTER \
 710         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 711         return val
 712
 713 #define __gen2_read(x) \
 714 static u##x \
 715 gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 716         GEN2_READ_HEADER(x); \
 717         val = __raw_i915_read##x(dev_priv, reg); \
 718         GEN2_READ_FOOTER; \
 719 }
 720
 721 #define __gen5_read(x) \
 722 static u##x \
 723 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 724         GEN2_READ_HEADER(x); \
 725         ilk_dummy_write(dev_priv); \
 726         val = __raw_i915_read##x(dev_priv, reg); \
 727         GEN2_READ_FOOTER; \
 728 }
 729
 730 __gen5_read(8)
 731 __gen5_read(16)
 732 __gen5_read(32)
 733 __gen5_read(64)
 734 __gen2_read(8)
 735 __gen2_read(16)
 736 __gen2_read(32)
 737 __gen2_read(64)
 738
 739 #undef __gen5_read
 740 #undef __gen2_read
 741
 742 #undef GEN2_READ_FOOTER
 743 #undef GEN2_READ_HEADER
 744
 745 #define GEN6_READ_HEADER(x) \
 746         unsigned long irqflags; \
 747         u##x val = 0; \
 748         assert_device_not_suspended(dev_priv); \
 749         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 750
 751 #define GEN6_READ_FOOTER \
 752         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 753         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 754         return val
 755
 756 #define __gen6_read(x) \
 757 static u##x \
 758 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 759         GEN6_READ_HEADER(x); \
 760         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 761         if (dev_priv->uncore.forcewake_count == 0 && \
 762             NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 763                 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
 764                                                       FORCEWAKE_ALL); \
 765                 dev_priv->uncore.forcewake_count++; \
 766                 mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \
 767                                  jiffies + 1); \
 768         } \
 769         val = __raw_i915_read##x(dev_priv, reg); \
 770         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 771         GEN6_READ_FOOTER; \
 772 }
 773
 774 #define __vlv_read(x) \
 775 static u##x \
 776 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 777         unsigned fwengine = 0; \
 778         GEN6_READ_HEADER(x); \
 779         if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
 780                 if (dev_priv->uncore.fw_rendercount == 0) \
 781                         fwengine = FORCEWAKE_RENDER; \
 782         } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
 783                 if (dev_priv->uncore.fw_mediacount == 0) \
 784                         fwengine = FORCEWAKE_MEDIA; \
 785         }  \
 786         if (fwengine) \
 787                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 788         val = __raw_i915_read##x(dev_priv, reg); \
 789         if (fwengine) \
 790                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 791         GEN6_READ_FOOTER; \
 792 }
 793
 794 #define __chv_read(x) \
 795 static u##x \
 796 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 797         unsigned fwengine = 0; \
 798         GEN6_READ_HEADER(x); \
 799         if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
 800                 if (dev_priv->uncore.fw_rendercount == 0) \
 801                         fwengine = FORCEWAKE_RENDER; \
 802         } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
 803                 if (dev_priv->uncore.fw_mediacount == 0) \
 804                         fwengine = FORCEWAKE_MEDIA; \
 805         } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
 806                 if (dev_priv->uncore.fw_rendercount == 0) \
 807                         fwengine |= FORCEWAKE_RENDER; \
 808                 if (dev_priv->uncore.fw_mediacount == 0) \
 809                         fwengine |= FORCEWAKE_MEDIA; \
 810         } \
 811         if (fwengine) \
 812                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 813         val = __raw_i915_read##x(dev_priv, reg); \
 814         if (fwengine) \
 815                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 816         GEN6_READ_FOOTER; \
 817 }
 818
 819 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)     \
 820          ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 821
 822 #define __gen9_read(x) \
 823 static u##x \
 824 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 825         GEN6_READ_HEADER(x); \
 826         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 827                 val = __raw_i915_read##x(dev_priv, reg); \
 828         } else { \
 829                 unsigned fwengine = 0; \
 830                 if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
 831                         if (dev_priv->uncore.fw_rendercount == 0) \
 832                                 fwengine = FORCEWAKE_RENDER; \
 833                 } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
 834                         if (dev_priv->uncore.fw_mediacount == 0) \
 835                                 fwengine = FORCEWAKE_MEDIA; \
 836                 } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
 837                         if (dev_priv->uncore.fw_rendercount == 0) \
 838                                 fwengine |= FORCEWAKE_RENDER; \
 839                         if (dev_priv->uncore.fw_mediacount == 0) \
 840                                 fwengine |= FORCEWAKE_MEDIA; \
 841                 } else { \
 842                         if (dev_priv->uncore.fw_blittercount == 0) \
 843                                 fwengine = FORCEWAKE_BLITTER; \
 844                 } \
 845                 if (fwengine) \
 846                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 847                 val = __raw_i915_read##x(dev_priv, reg); \
 848                 if (fwengine) \
 849                         dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 850         } \
 851         GEN6_READ_FOOTER; \
 852 }
 853
 854 __gen9_read(8)
 855 __gen9_read(16)
 856 __gen9_read(32)
 857 __gen9_read(64)
 858 __chv_read(8)
 859 __chv_read(16)
 860 __chv_read(32)
 861 __chv_read(64)
 862 __vlv_read(8)
 863 __vlv_read(16)
 864 __vlv_read(32)
 865 __vlv_read(64)
 866 __gen6_read(8)
 867 __gen6_read(16)
 868 __gen6_read(32)
 869 __gen6_read(64)
 870
 871 #undef __gen9_read
 872 #undef __chv_read
 873 #undef __vlv_read
 874 #undef __gen6_read
 875 #undef GEN6_READ_FOOTER
 876 #undef GEN6_READ_HEADER
 877
 878 #define GEN2_WRITE_HEADER \
 879         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 880         assert_device_not_suspended(dev_priv); \
 881
 882 #define GEN2_WRITE_FOOTER
 883
 884 #define __gen2_write(x) \
 885 static void \
 886 gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 887         GEN2_WRITE_HEADER; \
 888         __raw_i915_write##x(dev_priv, reg, val); \
 889         GEN2_WRITE_FOOTER; \
 890 }
 891
 892 #define __gen5_write(x) \
 893 static void \
 894 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 895         GEN2_WRITE_HEADER; \
 896         ilk_dummy_write(dev_priv); \
 897         __raw_i915_write##x(dev_priv, reg, val); \
 898         GEN2_WRITE_FOOTER; \
 899 }
 900
 901 __gen5_write(8)
 902 __gen5_write(16)
 903 __gen5_write(32)
 904 __gen5_write(64)
 905 __gen2_write(8)
 906 __gen2_write(16)
 907 __gen2_write(32)
 908 __gen2_write(64)
 909
 910 #undef __gen5_write
 911 #undef __gen2_write
 912
 913 #undef GEN2_WRITE_FOOTER
 914 #undef GEN2_WRITE_HEADER
 915
 916 #define GEN6_WRITE_HEADER \
 917         unsigned long irqflags; \
 918         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 919         assert_device_not_suspended(dev_priv); \
 920         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 921
 922 #define GEN6_WRITE_FOOTER \
 923         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 924
 925 #define __gen6_write(x) \
 926 static void \
 927 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 928         u32 __fifo_ret = 0; \
 929         GEN6_WRITE_HEADER; \
 930         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 931                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 932         } \
 933         __raw_i915_write##x(dev_priv, reg, val); \
 934         if (unlikely(__fifo_ret)) { \
 935                 gen6_gt_check_fifodbg(dev_priv); \
 936         } \
 937         GEN6_WRITE_FOOTER; \
 938 }
 939
 940 #define __hsw_write(x) \
 941 static void \
 942 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 943         u32 __fifo_ret = 0; \
 944         GEN6_WRITE_HEADER; \
 945         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 946                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 947         } \
 948         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 949         __raw_i915_write##x(dev_priv, reg, val); \
 950         if (unlikely(__fifo_ret)) { \
 951                 gen6_gt_check_fifodbg(dev_priv); \
 952         } \
 953         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 954         hsw_unclaimed_reg_detect(dev_priv); \
 955         GEN6_WRITE_FOOTER; \
 956 }
 957
 958 static const u32 gen8_shadowed_regs[] = {
 959         FORCEWAKE_MT,
 960         GEN6_RPNSWREQ,
 961         GEN6_RC_VIDEO_FREQ,
 962         RING_TAIL(RENDER_RING_BASE),
 963         RING_TAIL(GEN6_BSD_RING_BASE),
 964         RING_TAIL(VEBOX_RING_BASE),
 965         RING_TAIL(BLT_RING_BASE),
 966         /* TODO: Other registers are not yet used */
 967 };
 968
 969 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 970 {
 971         int i;
 972         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 973                 if (reg == gen8_shadowed_regs[i])
 974                         return true;
 975
 976         return false;
 977 }
 978
 979 #define __gen8_write(x) \
 980 static void \
 981 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 982         GEN6_WRITE_HEADER; \
 983         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 984         if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
 985                 if (dev_priv->uncore.forcewake_count == 0) \
 986                         dev_priv->uncore.funcs.force_wake_get(dev_priv, \
 987                                                               FORCEWAKE_ALL); \
 988                 __raw_i915_write##x(dev_priv, reg, val); \
 989                 if (dev_priv->uncore.forcewake_count == 0) \
 990                         dev_priv->uncore.funcs.force_wake_put(dev_priv, \
 991                                                               FORCEWAKE_ALL); \
 992         } else { \
 993                 __raw_i915_write##x(dev_priv, reg, val); \
 994         } \
 995         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 996         hsw_unclaimed_reg_detect(dev_priv); \
 997         GEN6_WRITE_FOOTER; \
 998 }
 999
1000 #define __chv_write(x) \
1001 static void \
1002 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
1003         unsigned fwengine = 0; \
1004         bool shadowed = is_gen8_shadowed(dev_priv, reg); \
1005         GEN6_WRITE_HEADER; \
1006         if (!shadowed) { \
1007                 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
1008                         if (dev_priv->uncore.fw_rendercount == 0) \
1009                                 fwengine = FORCEWAKE_RENDER; \
1010                 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
1011                         if (dev_priv->uncore.fw_mediacount == 0) \
1012                                 fwengine = FORCEWAKE_MEDIA; \
1013                 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
1014                         if (dev_priv->uncore.fw_rendercount == 0) \
1015                                 fwengine |= FORCEWAKE_RENDER; \
1016                         if (dev_priv->uncore.fw_mediacount == 0) \
1017                                 fwengine |= FORCEWAKE_MEDIA; \
1018                 } \
1019         } \
1020         if (fwengine) \
1021                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
1022         __raw_i915_write##x(dev_priv, reg, val); \
1023         if (fwengine) \
1024                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
1025         GEN6_WRITE_FOOTER; \
1026 }
1027
1028 static const u32 gen9_shadowed_regs[] = {
1029         RING_TAIL(RENDER_RING_BASE),
1030         RING_TAIL(GEN6_BSD_RING_BASE),
1031         RING_TAIL(VEBOX_RING_BASE),
1032         RING_TAIL(BLT_RING_BASE),
1033         FORCEWAKE_BLITTER_GEN9,
1034         FORCEWAKE_RENDER_GEN9,
1035         FORCEWAKE_MEDIA_GEN9,
1036         GEN6_RPNSWREQ,
1037         GEN6_RC_VIDEO_FREQ,
1038         /* TODO: Other registers are not yet used */
1039 };
1040
1041 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
1042 {
1043         int i;
1044         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
1045                 if (reg == gen9_shadowed_regs[i])
1046                         return true;
1047
1048         return false;
1049 }
1050
1051 #define __gen9_write(x) \
1052 static void \
1053 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
1054                 bool trace) { \
1055         GEN6_WRITE_HEADER; \
1056         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
1057                         is_gen9_shadowed(dev_priv, reg)) { \
1058                 __raw_i915_write##x(dev_priv, reg, val); \
1059         } else { \
1060                 unsigned fwengine = 0; \
1061                 if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
1062                         if (dev_priv->uncore.fw_rendercount == 0) \
1063                                 fwengine = FORCEWAKE_RENDER; \
1064                 } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
1065                         if (dev_priv->uncore.fw_mediacount == 0) \
1066                                 fwengine = FORCEWAKE_MEDIA; \
1067                 } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
1068                         if (dev_priv->uncore.fw_rendercount == 0) \
1069                                 fwengine |= FORCEWAKE_RENDER; \
1070                         if (dev_priv->uncore.fw_mediacount == 0) \
1071                                 fwengine |= FORCEWAKE_MEDIA; \
1072                 } else { \
1073                         if (dev_priv->uncore.fw_blittercount == 0) \
1074                                 fwengine = FORCEWAKE_BLITTER; \
1075                 } \
1076                 if (fwengine) \
1077                         dev_priv->uncore.funcs.force_wake_get(dev_priv, \
1078                                         fwengine); \
1079                 __raw_i915_write##x(dev_priv, reg, val); \
1080                 if (fwengine) \
1081                         dev_priv->uncore.funcs.force_wake_put(dev_priv, \
1082                                         fwengine); \
1083         } \
1084         GEN6_WRITE_FOOTER; \
1085 }
1086
1087 __gen9_write(8)
1088 __gen9_write(16)
1089 __gen9_write(32)
1090 __gen9_write(64)
1091 __chv_write(8)
1092 __chv_write(16)
1093 __chv_write(32)
1094 __chv_write(64)
1095 __gen8_write(8)
1096 __gen8_write(16)
1097 __gen8_write(32)
1098 __gen8_write(64)
1099 __hsw_write(8)
1100 __hsw_write(16)
1101 __hsw_write(32)
1102 __hsw_write(64)
1103 __gen6_write(8)
1104 __gen6_write(16)
1105 __gen6_write(32)
1106 __gen6_write(64)
1107
1108 #undef __gen9_write
1109 #undef __chv_write
1110 #undef __gen8_write
1111 #undef __hsw_write
1112 #undef __gen6_write
1113 #undef GEN6_WRITE_FOOTER
1114 #undef GEN6_WRITE_HEADER
1115
1116 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1117 do { \
1118         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1119         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1120         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1121         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1122 } while (0)
1123
1124 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1125 do { \
1126         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1127         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1128         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1129         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1130 } while (0)
1131
1132 void intel_uncore_init(struct drm_device *dev)
1133 {
1134         struct drm_i915_private *dev_priv = dev->dev_private;
1135
1136         setup_timer(&dev_priv->uncore.force_wake_timer,
1137                     gen6_force_wake_timer, (unsigned long)dev_priv);
1138
1139         __intel_uncore_early_sanitize(dev, false);
1140
1141         if (IS_GEN9(dev)) {
1142                 dev_priv->uncore.funcs.force_wake_get = __gen9_force_wake_get;
1143                 dev_priv->uncore.funcs.force_wake_put = __gen9_force_wake_put;
1144         } else if (IS_VALLEYVIEW(dev)) {
1145                 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
1146                 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
1147         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1148                 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
1149                 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
1150         } else if (IS_IVYBRIDGE(dev)) {
1151                 u32 ecobus;
1152
1153                 /* IVB configs may use multi-threaded forcewake */
1154
1155                 /* A small trick here - if the bios hasn't configured
1156                  * MT forcewake, and if the device is in RC6, then
1157                  * force_wake_mt_get will not wake the device and the
1158                  * ECOBUS read will return zero. Which will be
1159                  * (correctly) interpreted by the test below as MT
1160                  * forcewake being disabled.
1161                  */
1162                 mutex_lock(&dev->struct_mutex);
1163                 __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
1164                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1165                 __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
1166                 mutex_unlock(&dev->struct_mutex);
1167
1168                 if (ecobus & FORCEWAKE_MT_ENABLE) {
1169                         dev_priv->uncore.funcs.force_wake_get =
1170                                 __gen7_gt_force_wake_mt_get;
1171                         dev_priv->uncore.funcs.force_wake_put =
1172                                 __gen7_gt_force_wake_mt_put;
1173                 } else {
1174                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1175                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1176                         dev_priv->uncore.funcs.force_wake_get =
1177                                 __gen6_gt_force_wake_get;
1178                         dev_priv->uncore.funcs.force_wake_put =
1179                                 __gen6_gt_force_wake_put;
1180                 }
1181         } else if (IS_GEN6(dev)) {
1182                 dev_priv->uncore.funcs.force_wake_get =
1183                         __gen6_gt_force_wake_get;
1184                 dev_priv->uncore.funcs.force_wake_put =
1185                         __gen6_gt_force_wake_put;
1186         }
1187
1188         switch (INTEL_INFO(dev)->gen) {
1189         default:
1190                 MISSING_CASE(INTEL_INFO(dev)->gen);
1191                 return;
1192         case 9:
1193                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1194                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1195                 break;
1196         case 8:
1197                 if (IS_CHERRYVIEW(dev)) {
1198                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1199                         ASSIGN_READ_MMIO_VFUNCS(chv);
1200
1201                 } else {
1202                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1203                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1204                 }
1205                 break;
1206         case 7:
1207         case 6:
1208                 if (IS_HASWELL(dev)) {
1209                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1210                 } else {
1211                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1212                 }
1213
1214                 if (IS_VALLEYVIEW(dev)) {
1215                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1216                 } else {
1217                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1218                 }
1219                 break;
1220         case 5:
1221                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1222                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1223                 break;
1224         case 4:
1225         case 3:
1226         case 2:
1227                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1228                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1229                 break;
1230         }
1231
1232         i915_check_and_clear_faults(dev);
1233 }
1234 #undef ASSIGN_WRITE_MMIO_VFUNCS
1235 #undef ASSIGN_READ_MMIO_VFUNCS
1236
1237 void intel_uncore_fini(struct drm_device *dev)
1238 {
1239         /* Paranoia: make sure we have disabled everything before we exit. */
1240         intel_uncore_sanitize(dev);
1241         intel_uncore_forcewake_reset(dev, false);
1242 }
1243
1244 #define GEN_RANGE(l, h) GENMASK(h, l)
1245
1246 static const struct register_whitelist {
1247         uint64_t offset;
1248         uint32_t size;
1249         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1250         uint32_t gen_bitmask;
1251 } whitelist[] = {
1252         { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1253 };
1254
1255 int i915_reg_read_ioctl(struct drm_device *dev,
1256                         void *data, struct drm_file *file)
1257 {
1258         struct drm_i915_private *dev_priv = dev->dev_private;
1259         struct drm_i915_reg_read *reg = data;
1260         struct register_whitelist const *entry = whitelist;
1261         int i, ret = 0;
1262
1263         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1264                 if (entry->offset == reg->offset &&
1265                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1266                         break;
1267         }
1268
1269         if (i == ARRAY_SIZE(whitelist))
1270                 return -EINVAL;
1271
1272         intel_runtime_pm_get(dev_priv);
1273
1274         switch (entry->size) {
1275         case 8:
1276                 reg->val = I915_READ64(reg->offset);
1277                 break;
1278         case 4:
1279                 reg->val = I915_READ(reg->offset);
1280                 break;
1281         case 2:
1282                 reg->val = I915_READ16(reg->offset);
1283                 break;
1284         case 1:
1285                 reg->val = I915_READ8(reg->offset);
1286                 break;
1287         default:
1288                 MISSING_CASE(entry->size);
1289                 ret = -EINVAL;
1290                 goto out;
1291         }
1292
1293 out:
1294         intel_runtime_pm_put(dev_priv);
1295         return ret;
1296 }
1297
1298 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1299                                void *data, struct drm_file *file)
1300 {
1301         struct drm_i915_private *dev_priv = dev->dev_private;
1302         struct drm_i915_reset_stats *args = data;
1303         struct i915_ctx_hang_stats *hs;
1304         struct intel_context *ctx;
1305         int ret;
1306
1307         if (args->flags || args->pad)
1308                 return -EINVAL;
1309
1310         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1311                 return -EPERM;
1312
1313         ret = mutex_lock_interruptible(&dev->struct_mutex);
1314         if (ret)
1315                 return ret;
1316
1317         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1318         if (IS_ERR(ctx)) {
1319                 mutex_unlock(&dev->struct_mutex);
1320                 return PTR_ERR(ctx);
1321         }
1322         hs = &ctx->hang_stats;
1323
1324         if (capable(CAP_SYS_ADMIN))
1325                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1326         else
1327                 args->reset_count = 0;
1328
1329         args->batch_active = hs->batch_active;
1330         args->batch_pending = hs->batch_pending;
1331
1332         mutex_unlock(&dev->struct_mutex);
1333
1334         return 0;
1335 }
1336
1337 static int i915_reset_complete(struct drm_device *dev)
1338 {
1339         u8 gdrst;
1340         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1341         return (gdrst & GRDOM_RESET_STATUS) == 0;
1342 }
1343
1344 static int i915_do_reset(struct drm_device *dev)
1345 {
1346         /* assert reset for at least 20 usec */
1347         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1348         udelay(20);
1349         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1350
1351         return wait_for(i915_reset_complete(dev), 500);
1352 }
1353
1354 static int g4x_reset_complete(struct drm_device *dev)
1355 {
1356         u8 gdrst;
1357         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1358         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1359 }
1360
1361 static int g33_do_reset(struct drm_device *dev)
1362 {
1363         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1364         return wait_for(g4x_reset_complete(dev), 500);
1365 }
1366
1367 static int g4x_do_reset(struct drm_device *dev)
1368 {
1369         struct drm_i915_private *dev_priv = dev->dev_private;
1370         int ret;
1371
1372         pci_write_config_byte(dev->pdev, I915_GDRST,
1373                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1374         ret =  wait_for(g4x_reset_complete(dev), 500);
1375         if (ret)
1376                 return ret;
1377
1378         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1379         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1380         POSTING_READ(VDECCLK_GATE_D);
1381
1382         pci_write_config_byte(dev->pdev, I915_GDRST,
1383                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1384         ret =  wait_for(g4x_reset_complete(dev), 500);
1385         if (ret)
1386                 return ret;
1387
1388         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1389         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1390         POSTING_READ(VDECCLK_GATE_D);
1391
1392         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1393
1394         return 0;
1395 }
1396
1397 static int ironlake_do_reset(struct drm_device *dev)
1398 {
1399         struct drm_i915_private *dev_priv = dev->dev_private;
1400         int ret;
1401
1402         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1403                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1404         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1405                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1406         if (ret)
1407                 return ret;
1408
1409         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1410                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1411         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1412                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1413         if (ret)
1414                 return ret;
1415
1416         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1417
1418         return 0;
1419 }
1420
1421 static int gen6_do_reset(struct drm_device *dev)
1422 {
1423         struct drm_i915_private *dev_priv = dev->dev_private;
1424         int     ret;
1425
1426         /* Reset the chip */
1427
1428         /* GEN6_GDRST is not in the gt power well, no need to check
1429          * for fifo space for the write or forcewake the chip for
1430          * the read
1431          */
1432         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1433
1434         /* Spin waiting for the device to ack the reset request */
1435         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1436
1437         intel_uncore_forcewake_reset(dev, true);
1438
1439         return ret;
1440 }
1441
1442 int intel_gpu_reset(struct drm_device *dev)
1443 {
1444         if (INTEL_INFO(dev)->gen >= 6)
1445                 return gen6_do_reset(dev);
1446         else if (IS_GEN5(dev))
1447                 return ironlake_do_reset(dev);
1448         else if (IS_G4X(dev))
1449                 return g4x_do_reset(dev);
1450         else if (IS_G33(dev))
1451                 return g33_do_reset(dev);
1452         else if (INTEL_INFO(dev)->gen >= 3)
1453                 return i915_do_reset(dev);
1454         else
1455                 return -ENODEV;
1456 }
1457
1458 void intel_uncore_check_errors(struct drm_device *dev)
1459 {
1460         struct drm_i915_private *dev_priv = dev->dev_private;
1461
1462         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1463             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1464                 DRM_ERROR("Unclaimed register before interrupt\n");
1465                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1466         }
1467 }