drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <linux/pm_runtime.h>
  29
  30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  31
  32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
  33
  34 static const char * const forcewake_domain_names[] = {
  35         "render",
  36         "blitter",
  37         "media",
  38 };
  39
  40 const char *
  41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  42 {
  43         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  44
  45         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  46                 return forcewake_domain_names[id];
  47
  48         WARN_ON(id);
  49
  50         return "unknown";
  51 }
  52
  53 static inline void
  54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  55 {
  56         WARN_ON(!i915_mmio_reg_valid(d->reg_set));
  57         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  58 }
  59
  60 static inline void
  61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  62 {
  63         mod_timer_pinned(&d->timer, jiffies + 1);
  64 }
  65
  66 static inline void
  67 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  68 {
  69         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  70                              FORCEWAKE_KERNEL) == 0,
  71                             FORCEWAKE_ACK_TIMEOUT_MS))
  72                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  73                           intel_uncore_forcewake_domain_to_str(d->id));
  74 }
  75
  76 static inline void
  77 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  78 {
  79         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  80 }
  81
  82 static inline void
  83 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
  84 {
  85         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  86                              FORCEWAKE_KERNEL),
  87                             FORCEWAKE_ACK_TIMEOUT_MS))
  88                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
  89                           intel_uncore_forcewake_domain_to_str(d->id));
  90 }
  91
  92 static inline void
  93 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
  94 {
  95         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
  96 }
  97
  98 static inline void
  99 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 100 {
 101         /* something from same cacheline, but not from the set register */
 102         if (i915_mmio_reg_valid(d->reg_post))
 103                 __raw_posting_read(d->i915, d->reg_post);
 104 }
 105
 106 static void
 107 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 108 {
 109         struct intel_uncore_forcewake_domain *d;
 110         enum forcewake_domain_id id;
 111
 112         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 113                 fw_domain_wait_ack_clear(d);
 114                 fw_domain_get(d);
 115                 fw_domain_wait_ack(d);
 116         }
 117 }
 118
 119 static void
 120 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 121 {
 122         struct intel_uncore_forcewake_domain *d;
 123         enum forcewake_domain_id id;
 124
 125         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 126                 fw_domain_put(d);
 127                 fw_domain_posting_read(d);
 128         }
 129 }
 130
 131 static void
 132 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 133 {
 134         struct intel_uncore_forcewake_domain *d;
 135         enum forcewake_domain_id id;
 136
 137         /* No need to do for all, just do for first found */
 138         for_each_fw_domain(d, dev_priv, id) {
 139                 fw_domain_posting_read(d);
 140                 break;
 141         }
 142 }
 143
 144 static void
 145 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 146 {
 147         struct intel_uncore_forcewake_domain *d;
 148         enum forcewake_domain_id id;
 149
 150         if (dev_priv->uncore.fw_domains == 0)
 151                 return;
 152
 153         for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
 154                 fw_domain_reset(d);
 155
 156         fw_domains_posting_read(dev_priv);
 157 }
 158
 159 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 160 {
 161         /* w/a for a sporadic read returning 0 by waiting for the GT
 162          * thread to wake up.
 163          */
 164         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 165                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 166                 DRM_ERROR("GT thread status wait timed out\n");
 167 }
 168
 169 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 170                                               enum forcewake_domains fw_domains)
 171 {
 172         fw_domains_get(dev_priv, fw_domains);
 173
 174         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 175         __gen6_gt_wait_for_thread_c0(dev_priv);
 176 }
 177
 178 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 179 {
 180         u32 gtfifodbg;
 181
 182         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 183         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 184                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 185 }
 186
 187 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 188                                      enum forcewake_domains fw_domains)
 189 {
 190         fw_domains_put(dev_priv, fw_domains);
 191         gen6_gt_check_fifodbg(dev_priv);
 192 }
 193
 194 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
 195 {
 196         u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 197
 198         return count & GT_FIFO_FREE_ENTRIES_MASK;
 199 }
 200
 201 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 202 {
 203         int ret = 0;
 204
 205         /* On VLV, FIFO will be shared by both SW and HW.
 206          * So, we need to read the FREE_ENTRIES everytime */
 207         if (IS_VALLEYVIEW(dev_priv->dev))
 208                 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 209
 210         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 211                 int loop = 500;
 212                 u32 fifo = fifo_free_entries(dev_priv);
 213
 214                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 215                         udelay(10);
 216                         fifo = fifo_free_entries(dev_priv);
 217                 }
 218                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 219                         ++ret;
 220                 dev_priv->uncore.fifo_count = fifo;
 221         }
 222         dev_priv->uncore.fifo_count--;
 223
 224         return ret;
 225 }
 226
 227 static void intel_uncore_fw_release_timer(unsigned long arg)
 228 {
 229         struct intel_uncore_forcewake_domain *domain = (void *)arg;
 230         unsigned long irqflags;
 231
 232         assert_rpm_device_not_suspended(domain->i915);
 233
 234         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 235         if (WARN_ON(domain->wake_count == 0))
 236                 domain->wake_count++;
 237
 238         if (--domain->wake_count == 0)
 239                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 240                                                           1 << domain->id);
 241
 242         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 243 }
 244
 245 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 246 {
 247         struct drm_i915_private *dev_priv = dev->dev_private;
 248         unsigned long irqflags;
 249         struct intel_uncore_forcewake_domain *domain;
 250         int retry_count = 100;
 251         enum forcewake_domain_id id;
 252         enum forcewake_domains fw = 0, active_domains;
 253
 254         /* Hold uncore.lock across reset to prevent any register access
 255          * with forcewake not set correctly. Wait until all pending
 256          * timers are run before holding.
 257          */
 258         while (1) {
 259                 active_domains = 0;
 260
 261                 for_each_fw_domain(domain, dev_priv, id) {
 262                         if (del_timer_sync(&domain->timer) == 0)
 263                                 continue;
 264
 265                         intel_uncore_fw_release_timer((unsigned long)domain);
 266                 }
 267
 268                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 269
 270                 for_each_fw_domain(domain, dev_priv, id) {
 271                         if (timer_pending(&domain->timer))
 272                                 active_domains |= (1 << id);
 273                 }
 274
 275                 if (active_domains == 0)
 276                         break;
 277
 278                 if (--retry_count == 0) {
 279                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 280                         break;
 281                 }
 282
 283                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 284                 cond_resched();
 285         }
 286
 287         WARN_ON(active_domains);
 288
 289         for_each_fw_domain(domain, dev_priv, id)
 290                 if (domain->wake_count)
 291                         fw |= 1 << id;
 292
 293         if (fw)
 294                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 295
 296         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 297
 298         if (restore) { /* If reset with a user forcewake, try to restore */
 299                 if (fw)
 300                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 301
 302                 if (IS_GEN6(dev) || IS_GEN7(dev))
 303                         dev_priv->uncore.fifo_count =
 304                                 fifo_free_entries(dev_priv);
 305         }
 306
 307         if (!restore)
 308                 assert_forcewakes_inactive(dev_priv);
 309
 310         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 311 }
 312
 313 static void intel_uncore_ellc_detect(struct drm_device *dev)
 314 {
 315         struct drm_i915_private *dev_priv = dev->dev_private;
 316
 317         if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
 318              INTEL_INFO(dev)->gen >= 9) &&
 319             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
 320                 /* The docs do not explain exactly how the calculation can be
 321                  * made. It is somewhat guessable, but for now, it's always
 322                  * 128MB.
 323                  * NB: We can't write IDICR yet because we do not have gt funcs
 324                  * set up */
 325                 dev_priv->ellc_size = 128;
 326                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 327         }
 328 }
 329
 330 static bool
 331 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 332 {
 333         u32 dbg;
 334
 335         if (!HAS_FPGA_DBG_UNCLAIMED(dev_priv))
 336                 return false;
 337
 338         dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
 339         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 340                 return false;
 341
 342         __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 343
 344         return true;
 345 }
 346
 347 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 348                                           bool restore_forcewake)
 349 {
 350         struct drm_i915_private *dev_priv = dev->dev_private;
 351
 352         /* clear out unclaimed reg detection bit */
 353         if (check_for_unclaimed_mmio(dev_priv))
 354                 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
 355
 356         /* clear out old GT FIFO errors */
 357         if (IS_GEN6(dev) || IS_GEN7(dev))
 358                 __raw_i915_write32(dev_priv, GTFIFODBG,
 359                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 360
 361         /* WaDisableShadowRegForCpd:chv */
 362         if (IS_CHERRYVIEW(dev)) {
 363                 __raw_i915_write32(dev_priv, GTFIFOCTL,
 364                                    __raw_i915_read32(dev_priv, GTFIFOCTL) |
 365                                    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 366                                    GT_FIFO_CTL_RC6_POLICY_STALL);
 367         }
 368
 369         intel_uncore_forcewake_reset(dev, restore_forcewake);
 370 }
 371
 372 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 373 {
 374         __intel_uncore_early_sanitize(dev, restore_forcewake);
 375         i915_check_and_clear_faults(dev);
 376 }
 377
 378 void intel_uncore_sanitize(struct drm_device *dev)
 379 {
 380         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 381         intel_disable_gt_powersave(dev);
 382 }
 383
 384 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 385                                          enum forcewake_domains fw_domains)
 386 {
 387         struct intel_uncore_forcewake_domain *domain;
 388         enum forcewake_domain_id id;
 389
 390         if (!dev_priv->uncore.funcs.force_wake_get)
 391                 return;
 392
 393         fw_domains &= dev_priv->uncore.fw_domains;
 394
 395         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 396                 if (domain->wake_count++)
 397                         fw_domains &= ~(1 << id);
 398         }
 399
 400         if (fw_domains)
 401                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 402 }
 403
 404 /**
 405  * intel_uncore_forcewake_get - grab forcewake domain references
 406  * @dev_priv: i915 device instance
 407  * @fw_domains: forcewake domains to get reference on
 408  *
 409  * This function can be used get GT's forcewake domain references.
 410  * Normal register access will handle the forcewake domains automatically.
 411  * However if some sequence requires the GT to not power down a particular
 412  * forcewake domains this function should be called at the beginning of the
 413  * sequence. And subsequently the reference should be dropped by symmetric
 414  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 415  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 416  */
 417 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 418                                 enum forcewake_domains fw_domains)
 419 {
 420         unsigned long irqflags;
 421
 422         if (!dev_priv->uncore.funcs.force_wake_get)
 423                 return;
 424
 425         assert_rpm_wakelock_held(dev_priv);
 426
 427         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 428         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 429         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 430 }
 431
 432 /**
 433  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 434  * @dev_priv: i915 device instance
 435  * @fw_domains: forcewake domains to get reference on
 436  *
 437  * See intel_uncore_forcewake_get(). This variant places the onus
 438  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 439  */
 440 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 441                                         enum forcewake_domains fw_domains)
 442 {
 443         assert_spin_locked(&dev_priv->uncore.lock);
 444
 445         if (!dev_priv->uncore.funcs.force_wake_get)
 446                 return;
 447
 448         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 449 }
 450
 451 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 452                                          enum forcewake_domains fw_domains)
 453 {
 454         struct intel_uncore_forcewake_domain *domain;
 455         enum forcewake_domain_id id;
 456
 457         if (!dev_priv->uncore.funcs.force_wake_put)
 458                 return;
 459
 460         fw_domains &= dev_priv->uncore.fw_domains;
 461
 462         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 463                 if (WARN_ON(domain->wake_count == 0))
 464                         continue;
 465
 466                 if (--domain->wake_count)
 467                         continue;
 468
 469                 domain->wake_count++;
 470                 fw_domain_arm_timer(domain);
 471         }
 472 }
 473
 474 /**
 475  * intel_uncore_forcewake_put - release a forcewake domain reference
 476  * @dev_priv: i915 device instance
 477  * @fw_domains: forcewake domains to put references
 478  *
 479  * This function drops the device-level forcewakes for specified
 480  * domains obtained by intel_uncore_forcewake_get().
 481  */
 482 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 483                                 enum forcewake_domains fw_domains)
 484 {
 485         unsigned long irqflags;
 486
 487         if (!dev_priv->uncore.funcs.force_wake_put)
 488                 return;
 489
 490         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 491         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 492         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 493 }
 494
 495 /**
 496  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 497  * @dev_priv: i915 device instance
 498  * @fw_domains: forcewake domains to get reference on
 499  *
 500  * See intel_uncore_forcewake_put(). This variant places the onus
 501  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 502  */
 503 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 504                                         enum forcewake_domains fw_domains)
 505 {
 506         assert_spin_locked(&dev_priv->uncore.lock);
 507
 508         if (!dev_priv->uncore.funcs.force_wake_put)
 509                 return;
 510
 511         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 512 }
 513
 514 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 515 {
 516         struct intel_uncore_forcewake_domain *domain;
 517         enum forcewake_domain_id id;
 518
 519         if (!dev_priv->uncore.funcs.force_wake_get)
 520                 return;
 521
 522         for_each_fw_domain(domain, dev_priv, id)
 523                 WARN_ON(domain->wake_count);
 524 }
 525
 526 /* We give fast paths for the really cool registers */
 527 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 528
 529 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 530
 531 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 532         (REG_RANGE((reg), 0x2000, 0x4000) || \
 533          REG_RANGE((reg), 0x5000, 0x8000) || \
 534          REG_RANGE((reg), 0xB000, 0x12000) || \
 535          REG_RANGE((reg), 0x2E000, 0x30000))
 536
 537 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 538         (REG_RANGE((reg), 0x12000, 0x14000) || \
 539          REG_RANGE((reg), 0x22000, 0x24000) || \
 540          REG_RANGE((reg), 0x30000, 0x40000))
 541
 542 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 543         (REG_RANGE((reg), 0x2000, 0x4000) || \
 544          REG_RANGE((reg), 0x5200, 0x8000) || \
 545          REG_RANGE((reg), 0x8300, 0x8500) || \
 546          REG_RANGE((reg), 0xB000, 0xB480) || \
 547          REG_RANGE((reg), 0xE000, 0xE800))
 548
 549 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 550         (REG_RANGE((reg), 0x8800, 0x8900) || \
 551          REG_RANGE((reg), 0xD000, 0xD800) || \
 552          REG_RANGE((reg), 0x12000, 0x14000) || \
 553          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 554          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 555          REG_RANGE((reg), 0x30000, 0x38000))
 556
 557 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 558         (REG_RANGE((reg), 0x4000, 0x5000) || \
 559          REG_RANGE((reg), 0x8000, 0x8300) || \
 560          REG_RANGE((reg), 0x8500, 0x8600) || \
 561          REG_RANGE((reg), 0x9000, 0xB000) || \
 562          REG_RANGE((reg), 0xF000, 0x10000))
 563
 564 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 565         REG_RANGE((reg), 0xB00,  0x2000)
 566
 567 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 568         (REG_RANGE((reg), 0x2000, 0x2700) || \
 569          REG_RANGE((reg), 0x3000, 0x4000) || \
 570          REG_RANGE((reg), 0x5200, 0x8000) || \
 571          REG_RANGE((reg), 0x8140, 0x8160) || \
 572          REG_RANGE((reg), 0x8300, 0x8500) || \
 573          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 574          REG_RANGE((reg), 0xB000, 0xB480) || \
 575          REG_RANGE((reg), 0xE000, 0xE900) || \
 576          REG_RANGE((reg), 0x24400, 0x24800))
 577
 578 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 579         (REG_RANGE((reg), 0x8130, 0x8140) || \
 580          REG_RANGE((reg), 0x8800, 0x8A00) || \
 581          REG_RANGE((reg), 0xD000, 0xD800) || \
 582          REG_RANGE((reg), 0x12000, 0x14000) || \
 583          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 584          REG_RANGE((reg), 0x30000, 0x40000))
 585
 586 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 587         REG_RANGE((reg), 0x9400, 0x9800)
 588
 589 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 590         ((reg) < 0x40000 && \
 591          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 592          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 593          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 594          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 595
 596 static void
 597 ilk_dummy_write(struct drm_i915_private *dev_priv)
 598 {
 599         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 600          * the chip from rc6 before touching it for real. MI_MODE is masked,
 601          * hence harmless to write 0 into. */
 602         __raw_i915_write32(dev_priv, MI_MODE, 0);
 603 }
 604
 605 static void
 606 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 607                         i915_reg_t reg, bool read, bool before)
 608 {
 609         const char *op = read ? "reading" : "writing to";
 610         const char *when = before ? "before" : "after";
 611
 612         if (!i915.mmio_debug)
 613                 return;
 614
 615         if (check_for_unclaimed_mmio(dev_priv)) {
 616                 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 617                      when, op, i915_mmio_reg_offset(reg));
 618                 i915.mmio_debug--; /* Only report the first N failures */
 619         }
 620 }
 621
 622 static void
 623 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 624 {
 625         static bool mmio_debug_once = true;
 626
 627         if (i915.mmio_debug || !mmio_debug_once)
 628                 return;
 629
 630         if (check_for_unclaimed_mmio(dev_priv)) {
 631                 DRM_DEBUG("Unclaimed register detected, "
 632                           "enabling oneshot unclaimed register reporting. "
 633                           "Please use i915.mmio_debug=N for more information.\n");
 634                 i915.mmio_debug = mmio_debug_once--;
 635         }
 636 }
 637
 638 #define GEN2_READ_HEADER(x) \
 639         u##x val = 0; \
 640         assert_rpm_wakelock_held(dev_priv);
 641
 642 #define GEN2_READ_FOOTER \
 643         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 644         return val
 645
 646 #define __gen2_read(x) \
 647 static u##x \
 648 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 649         GEN2_READ_HEADER(x); \
 650         val = __raw_i915_read##x(dev_priv, reg); \
 651         GEN2_READ_FOOTER; \
 652 }
 653
 654 #define __gen5_read(x) \
 655 static u##x \
 656 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 657         GEN2_READ_HEADER(x); \
 658         ilk_dummy_write(dev_priv); \
 659         val = __raw_i915_read##x(dev_priv, reg); \
 660         GEN2_READ_FOOTER; \
 661 }
 662
 663 __gen5_read(8)
 664 __gen5_read(16)
 665 __gen5_read(32)
 666 __gen5_read(64)
 667 __gen2_read(8)
 668 __gen2_read(16)
 669 __gen2_read(32)
 670 __gen2_read(64)
 671
 672 #undef __gen5_read
 673 #undef __gen2_read
 674
 675 #undef GEN2_READ_FOOTER
 676 #undef GEN2_READ_HEADER
 677
 678 #define GEN6_READ_HEADER(x) \
 679         u32 offset = i915_mmio_reg_offset(reg); \
 680         unsigned long irqflags; \
 681         u##x val = 0; \
 682         assert_rpm_wakelock_held(dev_priv); \
 683         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 684
 685 #define GEN6_READ_FOOTER \
 686         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 687         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 688         return val
 689
 690 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
 691                                     enum forcewake_domains fw_domains)
 692 {
 693         struct intel_uncore_forcewake_domain *domain;
 694         enum forcewake_domain_id id;
 695
 696         if (WARN_ON(!fw_domains))
 697                 return;
 698
 699         /* Ideally GCC would be constant-fold and eliminate this loop */
 700         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 701                 if (domain->wake_count) {
 702                         fw_domains &= ~(1 << id);
 703                         continue;
 704                 }
 705
 706                 domain->wake_count++;
 707                 fw_domain_arm_timer(domain);
 708         }
 709
 710         if (fw_domains)
 711                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 712 }
 713
 714 #define __gen6_read(x) \
 715 static u##x \
 716 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 717         GEN6_READ_HEADER(x); \
 718         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 719         if (NEEDS_FORCE_WAKE(offset)) \
 720                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 721         val = __raw_i915_read##x(dev_priv, reg); \
 722         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 723         GEN6_READ_FOOTER; \
 724 }
 725
 726 #define __vlv_read(x) \
 727 static u##x \
 728 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 729         enum forcewake_domains fw_engine = 0; \
 730         GEN6_READ_HEADER(x); \
 731         if (!NEEDS_FORCE_WAKE(offset)) \
 732                 fw_engine = 0; \
 733         else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
 734                 fw_engine = FORCEWAKE_RENDER; \
 735         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
 736                 fw_engine = FORCEWAKE_MEDIA; \
 737         if (fw_engine) \
 738                 __force_wake_get(dev_priv, fw_engine); \
 739         val = __raw_i915_read##x(dev_priv, reg); \
 740         GEN6_READ_FOOTER; \
 741 }
 742
 743 #define __chv_read(x) \
 744 static u##x \
 745 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 746         enum forcewake_domains fw_engine = 0; \
 747         GEN6_READ_HEADER(x); \
 748         if (!NEEDS_FORCE_WAKE(offset)) \
 749                 fw_engine = 0; \
 750         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 751                 fw_engine = FORCEWAKE_RENDER; \
 752         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 753                 fw_engine = FORCEWAKE_MEDIA; \
 754         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 755                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 756         if (fw_engine) \
 757                 __force_wake_get(dev_priv, fw_engine); \
 758         val = __raw_i915_read##x(dev_priv, reg); \
 759         GEN6_READ_FOOTER; \
 760 }
 761
 762 #define SKL_NEEDS_FORCE_WAKE(reg) \
 763         ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 764
 765 #define __gen9_read(x) \
 766 static u##x \
 767 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 768         enum forcewake_domains fw_engine; \
 769         GEN6_READ_HEADER(x); \
 770         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 771         if (!SKL_NEEDS_FORCE_WAKE(offset)) \
 772                 fw_engine = 0; \
 773         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 774                 fw_engine = FORCEWAKE_RENDER; \
 775         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
 776                 fw_engine = FORCEWAKE_MEDIA; \
 777         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
 778                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 779         else \
 780                 fw_engine = FORCEWAKE_BLITTER; \
 781         if (fw_engine) \
 782                 __force_wake_get(dev_priv, fw_engine); \
 783         val = __raw_i915_read##x(dev_priv, reg); \
 784         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 785         GEN6_READ_FOOTER; \
 786 }
 787
 788 __gen9_read(8)
 789 __gen9_read(16)
 790 __gen9_read(32)
 791 __gen9_read(64)
 792 __chv_read(8)
 793 __chv_read(16)
 794 __chv_read(32)
 795 __chv_read(64)
 796 __vlv_read(8)
 797 __vlv_read(16)
 798 __vlv_read(32)
 799 __vlv_read(64)
 800 __gen6_read(8)
 801 __gen6_read(16)
 802 __gen6_read(32)
 803 __gen6_read(64)
 804
 805 #undef __gen9_read
 806 #undef __chv_read
 807 #undef __vlv_read
 808 #undef __gen6_read
 809 #undef GEN6_READ_FOOTER
 810 #undef GEN6_READ_HEADER
 811
 812 #define VGPU_READ_HEADER(x) \
 813         unsigned long irqflags; \
 814         u##x val = 0; \
 815         assert_rpm_device_not_suspended(dev_priv); \
 816         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 817
 818 #define VGPU_READ_FOOTER \
 819         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 820         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 821         return val
 822
 823 #define __vgpu_read(x) \
 824 static u##x \
 825 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 826         VGPU_READ_HEADER(x); \
 827         val = __raw_i915_read##x(dev_priv, reg); \
 828         VGPU_READ_FOOTER; \
 829 }
 830
 831 __vgpu_read(8)
 832 __vgpu_read(16)
 833 __vgpu_read(32)
 834 __vgpu_read(64)
 835
 836 #undef __vgpu_read
 837 #undef VGPU_READ_FOOTER
 838 #undef VGPU_READ_HEADER
 839
 840 #define GEN2_WRITE_HEADER \
 841         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 842         assert_rpm_wakelock_held(dev_priv); \
 843
 844 #define GEN2_WRITE_FOOTER
 845
 846 #define __gen2_write(x) \
 847 static void \
 848 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 849         GEN2_WRITE_HEADER; \
 850         __raw_i915_write##x(dev_priv, reg, val); \
 851         GEN2_WRITE_FOOTER; \
 852 }
 853
 854 #define __gen5_write(x) \
 855 static void \
 856 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 857         GEN2_WRITE_HEADER; \
 858         ilk_dummy_write(dev_priv); \
 859         __raw_i915_write##x(dev_priv, reg, val); \
 860         GEN2_WRITE_FOOTER; \
 861 }
 862
 863 __gen5_write(8)
 864 __gen5_write(16)
 865 __gen5_write(32)
 866 __gen5_write(64)
 867 __gen2_write(8)
 868 __gen2_write(16)
 869 __gen2_write(32)
 870 __gen2_write(64)
 871
 872 #undef __gen5_write
 873 #undef __gen2_write
 874
 875 #undef GEN2_WRITE_FOOTER
 876 #undef GEN2_WRITE_HEADER
 877
 878 #define GEN6_WRITE_HEADER \
 879         u32 offset = i915_mmio_reg_offset(reg); \
 880         unsigned long irqflags; \
 881         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 882         assert_rpm_wakelock_held(dev_priv); \
 883         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 884
 885 #define GEN6_WRITE_FOOTER \
 886         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 887
 888 #define __gen6_write(x) \
 889 static void \
 890 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 891         u32 __fifo_ret = 0; \
 892         GEN6_WRITE_HEADER; \
 893         if (NEEDS_FORCE_WAKE(offset)) { \
 894                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 895         } \
 896         __raw_i915_write##x(dev_priv, reg, val); \
 897         if (unlikely(__fifo_ret)) { \
 898                 gen6_gt_check_fifodbg(dev_priv); \
 899         } \
 900         GEN6_WRITE_FOOTER; \
 901 }
 902
 903 #define __hsw_write(x) \
 904 static void \
 905 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 906         u32 __fifo_ret = 0; \
 907         GEN6_WRITE_HEADER; \
 908         if (NEEDS_FORCE_WAKE(offset)) { \
 909                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 910         } \
 911         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 912         __raw_i915_write##x(dev_priv, reg, val); \
 913         if (unlikely(__fifo_ret)) { \
 914                 gen6_gt_check_fifodbg(dev_priv); \
 915         } \
 916         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 917         hsw_unclaimed_reg_detect(dev_priv); \
 918         GEN6_WRITE_FOOTER; \
 919 }
 920
 921 static const i915_reg_t gen8_shadowed_regs[] = {
 922         FORCEWAKE_MT,
 923         GEN6_RPNSWREQ,
 924         GEN6_RC_VIDEO_FREQ,
 925         RING_TAIL(RENDER_RING_BASE),
 926         RING_TAIL(GEN6_BSD_RING_BASE),
 927         RING_TAIL(VEBOX_RING_BASE),
 928         RING_TAIL(BLT_RING_BASE),
 929         /* TODO: Other registers are not yet used */
 930 };
 931
 932 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv,
 933                              i915_reg_t reg)
 934 {
 935         int i;
 936         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 937                 if (i915_mmio_reg_equal(reg, gen8_shadowed_regs[i]))
 938                         return true;
 939
 940         return false;
 941 }
 942
 943 #define __gen8_write(x) \
 944 static void \
 945 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 946         GEN6_WRITE_HEADER; \
 947         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 948         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(dev_priv, reg)) \
 949                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 950         __raw_i915_write##x(dev_priv, reg, val); \
 951         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 952         hsw_unclaimed_reg_detect(dev_priv); \
 953         GEN6_WRITE_FOOTER; \
 954 }
 955
 956 #define __chv_write(x) \
 957 static void \
 958 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 959         enum forcewake_domains fw_engine = 0; \
 960         GEN6_WRITE_HEADER; \
 961         if (!NEEDS_FORCE_WAKE(offset) || \
 962             is_gen8_shadowed(dev_priv, reg)) \
 963                 fw_engine = 0; \
 964         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 965                 fw_engine = FORCEWAKE_RENDER; \
 966         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 967                 fw_engine = FORCEWAKE_MEDIA; \
 968         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 969                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 970         if (fw_engine) \
 971                 __force_wake_get(dev_priv, fw_engine); \
 972         __raw_i915_write##x(dev_priv, reg, val); \
 973         GEN6_WRITE_FOOTER; \
 974 }
 975
 976 static const i915_reg_t gen9_shadowed_regs[] = {
 977         RING_TAIL(RENDER_RING_BASE),
 978         RING_TAIL(GEN6_BSD_RING_BASE),
 979         RING_TAIL(VEBOX_RING_BASE),
 980         RING_TAIL(BLT_RING_BASE),
 981         FORCEWAKE_BLITTER_GEN9,
 982         FORCEWAKE_RENDER_GEN9,
 983         FORCEWAKE_MEDIA_GEN9,
 984         GEN6_RPNSWREQ,
 985         GEN6_RC_VIDEO_FREQ,
 986         /* TODO: Other registers are not yet used */
 987 };
 988
 989 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv,
 990                              i915_reg_t reg)
 991 {
 992         int i;
 993         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 994                 if (i915_mmio_reg_equal(reg, gen9_shadowed_regs[i]))
 995                         return true;
 996
 997         return false;
 998 }
 999
1000 #define __gen9_write(x) \
1001 static void \
1002 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
1003                 bool trace) { \
1004         enum forcewake_domains fw_engine; \
1005         GEN6_WRITE_HEADER; \
1006         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
1007         if (!SKL_NEEDS_FORCE_WAKE(offset) || \
1008             is_gen9_shadowed(dev_priv, reg)) \
1009                 fw_engine = 0; \
1010         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
1011                 fw_engine = FORCEWAKE_RENDER; \
1012         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
1013                 fw_engine = FORCEWAKE_MEDIA; \
1014         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
1015                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
1016         else \
1017                 fw_engine = FORCEWAKE_BLITTER; \
1018         if (fw_engine) \
1019                 __force_wake_get(dev_priv, fw_engine); \
1020         __raw_i915_write##x(dev_priv, reg, val); \
1021         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
1022         hsw_unclaimed_reg_detect(dev_priv); \
1023         GEN6_WRITE_FOOTER; \
1024 }
1025
1026 __gen9_write(8)
1027 __gen9_write(16)
1028 __gen9_write(32)
1029 __gen9_write(64)
1030 __chv_write(8)
1031 __chv_write(16)
1032 __chv_write(32)
1033 __chv_write(64)
1034 __gen8_write(8)
1035 __gen8_write(16)
1036 __gen8_write(32)
1037 __gen8_write(64)
1038 __hsw_write(8)
1039 __hsw_write(16)
1040 __hsw_write(32)
1041 __hsw_write(64)
1042 __gen6_write(8)
1043 __gen6_write(16)
1044 __gen6_write(32)
1045 __gen6_write(64)
1046
1047 #undef __gen9_write
1048 #undef __chv_write
1049 #undef __gen8_write
1050 #undef __hsw_write
1051 #undef __gen6_write
1052 #undef GEN6_WRITE_FOOTER
1053 #undef GEN6_WRITE_HEADER
1054
1055 #define VGPU_WRITE_HEADER \
1056         unsigned long irqflags; \
1057         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1058         assert_rpm_device_not_suspended(dev_priv); \
1059         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1060
1061 #define VGPU_WRITE_FOOTER \
1062         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1063
1064 #define __vgpu_write(x) \
1065 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1066                           i915_reg_t reg, u##x val, bool trace) { \
1067         VGPU_WRITE_HEADER; \
1068         __raw_i915_write##x(dev_priv, reg, val); \
1069         VGPU_WRITE_FOOTER; \
1070 }
1071
1072 __vgpu_write(8)
1073 __vgpu_write(16)
1074 __vgpu_write(32)
1075 __vgpu_write(64)
1076
1077 #undef __vgpu_write
1078 #undef VGPU_WRITE_FOOTER
1079 #undef VGPU_WRITE_HEADER
1080
1081 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1082 do { \
1083         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1084         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1085         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1086         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1087 } while (0)
1088
1089 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1090 do { \
1091         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1092         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1093         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1094         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1095 } while (0)
1096
1097
1098 static void fw_domain_init(struct drm_i915_private *dev_priv,
1099                            enum forcewake_domain_id domain_id,
1100                            i915_reg_t reg_set,
1101                            i915_reg_t reg_ack)
1102 {
1103         struct intel_uncore_forcewake_domain *d;
1104
1105         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1106                 return;
1107
1108         d = &dev_priv->uncore.fw_domain[domain_id];
1109
1110         WARN_ON(d->wake_count);
1111
1112         d->wake_count = 0;
1113         d->reg_set = reg_set;
1114         d->reg_ack = reg_ack;
1115
1116         if (IS_GEN6(dev_priv)) {
1117                 d->val_reset = 0;
1118                 d->val_set = FORCEWAKE_KERNEL;
1119                 d->val_clear = 0;
1120         } else {
1121                 /* WaRsClearFWBitsAtReset:bdw,skl */
1122                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1123                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1124                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1125         }
1126
1127         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1128                 d->reg_post = FORCEWAKE_ACK_VLV;
1129         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1130                 d->reg_post = ECOBUS;
1131
1132         d->i915 = dev_priv;
1133         d->id = domain_id;
1134
1135         setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
1136
1137         dev_priv->uncore.fw_domains |= (1 << domain_id);
1138
1139         fw_domain_reset(d);
1140 }
1141
1142 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1143 {
1144         struct drm_i915_private *dev_priv = dev->dev_private;
1145
1146         if (INTEL_INFO(dev_priv->dev)->gen <= 5)
1147                 return;
1148
1149         if (IS_GEN9(dev)) {
1150                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1151                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1152                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1153                                FORCEWAKE_RENDER_GEN9,
1154                                FORCEWAKE_ACK_RENDER_GEN9);
1155                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1156                                FORCEWAKE_BLITTER_GEN9,
1157                                FORCEWAKE_ACK_BLITTER_GEN9);
1158                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1159                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1160         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1161                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1162                 if (!IS_CHERRYVIEW(dev))
1163                         dev_priv->uncore.funcs.force_wake_put =
1164                                 fw_domains_put_with_fifo;
1165                 else
1166                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1167                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1168                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1169                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1170                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1171         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1172                 dev_priv->uncore.funcs.force_wake_get =
1173                         fw_domains_get_with_thread_status;
1174                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1175                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1176                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1177         } else if (IS_IVYBRIDGE(dev)) {
1178                 u32 ecobus;
1179
1180                 /* IVB configs may use multi-threaded forcewake */
1181
1182                 /* A small trick here - if the bios hasn't configured
1183                  * MT forcewake, and if the device is in RC6, then
1184                  * force_wake_mt_get will not wake the device and the
1185                  * ECOBUS read will return zero. Which will be
1186                  * (correctly) interpreted by the test below as MT
1187                  * forcewake being disabled.
1188                  */
1189                 dev_priv->uncore.funcs.force_wake_get =
1190                         fw_domains_get_with_thread_status;
1191                 dev_priv->uncore.funcs.force_wake_put =
1192                         fw_domains_put_with_fifo;
1193
1194                 /* We need to init first for ECOBUS access and then
1195                  * determine later if we want to reinit, in case of MT access is
1196                  * not working. In this stage we don't know which flavour this
1197                  * ivb is, so it is better to reset also the gen6 fw registers
1198                  * before the ecobus check.
1199                  */
1200
1201                 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1202                 __raw_posting_read(dev_priv, ECOBUS);
1203
1204                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1205                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1206
1207                 mutex_lock(&dev->struct_mutex);
1208                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1209                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1210                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1211                 mutex_unlock(&dev->struct_mutex);
1212
1213                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1214                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1215                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1216                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1217                                        FORCEWAKE, FORCEWAKE_ACK);
1218                 }
1219         } else if (IS_GEN6(dev)) {
1220                 dev_priv->uncore.funcs.force_wake_get =
1221                         fw_domains_get_with_thread_status;
1222                 dev_priv->uncore.funcs.force_wake_put =
1223                         fw_domains_put_with_fifo;
1224                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1225                                FORCEWAKE, FORCEWAKE_ACK);
1226         }
1227
1228         /* All future platforms are expected to require complex power gating */
1229         WARN_ON(dev_priv->uncore.fw_domains == 0);
1230 }
1231
1232 void intel_uncore_init(struct drm_device *dev)
1233 {
1234         struct drm_i915_private *dev_priv = dev->dev_private;
1235
1236         i915_check_vgpu(dev);
1237
1238         intel_uncore_ellc_detect(dev);
1239         intel_uncore_fw_domains_init(dev);
1240         __intel_uncore_early_sanitize(dev, false);
1241
1242         switch (INTEL_INFO(dev)->gen) {
1243         default:
1244         case 9:
1245                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1246                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1247                 break;
1248         case 8:
1249                 if (IS_CHERRYVIEW(dev)) {
1250                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1251                         ASSIGN_READ_MMIO_VFUNCS(chv);
1252
1253                 } else {
1254                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1255                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1256                 }
1257                 break;
1258         case 7:
1259         case 6:
1260                 if (IS_HASWELL(dev)) {
1261                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1262                 } else {
1263                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1264                 }
1265
1266                 if (IS_VALLEYVIEW(dev)) {
1267                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1268                 } else {
1269                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1270                 }
1271                 break;
1272         case 5:
1273                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1274                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1275                 break;
1276         case 4:
1277         case 3:
1278         case 2:
1279                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1280                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1281                 break;
1282         }
1283
1284         if (intel_vgpu_active(dev)) {
1285                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1286                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1287         }
1288
1289         i915_check_and_clear_faults(dev);
1290 }
1291 #undef ASSIGN_WRITE_MMIO_VFUNCS
1292 #undef ASSIGN_READ_MMIO_VFUNCS
1293
1294 void intel_uncore_fini(struct drm_device *dev)
1295 {
1296         /* Paranoia: make sure we have disabled everything before we exit. */
1297         intel_uncore_sanitize(dev);
1298         intel_uncore_forcewake_reset(dev, false);
1299 }
1300
1301 #define GEN_RANGE(l, h) GENMASK(h, l)
1302
1303 static const struct register_whitelist {
1304         i915_reg_t offset_ldw, offset_udw;
1305         uint32_t size;
1306         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1307         uint32_t gen_bitmask;
1308 } whitelist[] = {
1309         { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1310           .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1311           .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1312 };
1313
1314 int i915_reg_read_ioctl(struct drm_device *dev,
1315                         void *data, struct drm_file *file)
1316 {
1317         struct drm_i915_private *dev_priv = dev->dev_private;
1318         struct drm_i915_reg_read *reg = data;
1319         struct register_whitelist const *entry = whitelist;
1320         unsigned size;
1321         i915_reg_t offset_ldw, offset_udw;
1322         int i, ret = 0;
1323
1324         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1325                 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1326                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1327                         break;
1328         }
1329
1330         if (i == ARRAY_SIZE(whitelist))
1331                 return -EINVAL;
1332
1333         /* We use the low bits to encode extra flags as the register should
1334          * be naturally aligned (and those that are not so aligned merely
1335          * limit the available flags for that register).
1336          */
1337         offset_ldw = entry->offset_ldw;
1338         offset_udw = entry->offset_udw;
1339         size = entry->size;
1340         size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1341
1342         intel_runtime_pm_get(dev_priv);
1343
1344         switch (size) {
1345         case 8 | 1:
1346                 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1347                 break;
1348         case 8:
1349                 reg->val = I915_READ64(offset_ldw);
1350                 break;
1351         case 4:
1352                 reg->val = I915_READ(offset_ldw);
1353                 break;
1354         case 2:
1355                 reg->val = I915_READ16(offset_ldw);
1356                 break;
1357         case 1:
1358                 reg->val = I915_READ8(offset_ldw);
1359                 break;
1360         default:
1361                 ret = -EINVAL;
1362                 goto out;
1363         }
1364
1365 out:
1366         intel_runtime_pm_put(dev_priv);
1367         return ret;
1368 }
1369
1370 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1371                                void *data, struct drm_file *file)
1372 {
1373         struct drm_i915_private *dev_priv = dev->dev_private;
1374         struct drm_i915_reset_stats *args = data;
1375         struct i915_ctx_hang_stats *hs;
1376         struct intel_context *ctx;
1377         int ret;
1378
1379         if (args->flags || args->pad)
1380                 return -EINVAL;
1381
1382         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1383                 return -EPERM;
1384
1385         ret = mutex_lock_interruptible(&dev->struct_mutex);
1386         if (ret)
1387                 return ret;
1388
1389         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1390         if (IS_ERR(ctx)) {
1391                 mutex_unlock(&dev->struct_mutex);
1392                 return PTR_ERR(ctx);
1393         }
1394         hs = &ctx->hang_stats;
1395
1396         if (capable(CAP_SYS_ADMIN))
1397                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1398         else
1399                 args->reset_count = 0;
1400
1401         args->batch_active = hs->batch_active;
1402         args->batch_pending = hs->batch_pending;
1403
1404         mutex_unlock(&dev->struct_mutex);
1405
1406         return 0;
1407 }
1408
1409 static int i915_reset_complete(struct drm_device *dev)
1410 {
1411         u8 gdrst;
1412         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1413         return (gdrst & GRDOM_RESET_STATUS) == 0;
1414 }
1415
1416 static int i915_do_reset(struct drm_device *dev)
1417 {
1418         /* assert reset for at least 20 usec */
1419         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1420         udelay(20);
1421         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1422
1423         return wait_for(i915_reset_complete(dev), 500);
1424 }
1425
1426 static int g4x_reset_complete(struct drm_device *dev)
1427 {
1428         u8 gdrst;
1429         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1430         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1431 }
1432
1433 static int g33_do_reset(struct drm_device *dev)
1434 {
1435         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1436         return wait_for(g4x_reset_complete(dev), 500);
1437 }
1438
1439 static int g4x_do_reset(struct drm_device *dev)
1440 {
1441         struct drm_i915_private *dev_priv = dev->dev_private;
1442         int ret;
1443
1444         pci_write_config_byte(dev->pdev, I915_GDRST,
1445                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1446         ret =  wait_for(g4x_reset_complete(dev), 500);
1447         if (ret)
1448                 return ret;
1449
1450         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1451         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1452         POSTING_READ(VDECCLK_GATE_D);
1453
1454         pci_write_config_byte(dev->pdev, I915_GDRST,
1455                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1456         ret =  wait_for(g4x_reset_complete(dev), 500);
1457         if (ret)
1458                 return ret;
1459
1460         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1461         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1462         POSTING_READ(VDECCLK_GATE_D);
1463
1464         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1465
1466         return 0;
1467 }
1468
1469 static int ironlake_do_reset(struct drm_device *dev)
1470 {
1471         struct drm_i915_private *dev_priv = dev->dev_private;
1472         int ret;
1473
1474         I915_WRITE(ILK_GDSR,
1475                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1476         ret = wait_for((I915_READ(ILK_GDSR) &
1477                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1478         if (ret)
1479                 return ret;
1480
1481         I915_WRITE(ILK_GDSR,
1482                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1483         ret = wait_for((I915_READ(ILK_GDSR) &
1484                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1485         if (ret)
1486                 return ret;
1487
1488         I915_WRITE(ILK_GDSR, 0);
1489
1490         return 0;
1491 }
1492
1493 static int gen6_do_reset(struct drm_device *dev)
1494 {
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         int     ret;
1497
1498         /* Reset the chip */
1499
1500         /* GEN6_GDRST is not in the gt power well, no need to check
1501          * for fifo space for the write or forcewake the chip for
1502          * the read
1503          */
1504         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1505
1506         /* Spin waiting for the device to ack the reset request */
1507         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1508
1509         intel_uncore_forcewake_reset(dev, true);
1510
1511         return ret;
1512 }
1513
1514 static int wait_for_register(struct drm_i915_private *dev_priv,
1515                              i915_reg_t reg,
1516                              const u32 mask,
1517                              const u32 value,
1518                              const unsigned long timeout_ms)
1519 {
1520         return wait_for((I915_READ(reg) & mask) == value, timeout_ms);
1521 }
1522
1523 static int gen8_do_reset(struct drm_device *dev)
1524 {
1525         struct drm_i915_private *dev_priv = dev->dev_private;
1526         struct intel_engine_cs *engine;
1527         int i;
1528
1529         for_each_ring(engine, dev_priv, i) {
1530                 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1531                            _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1532
1533                 if (wait_for_register(dev_priv,
1534                                       RING_RESET_CTL(engine->mmio_base),
1535                                       RESET_CTL_READY_TO_RESET,
1536                                       RESET_CTL_READY_TO_RESET,
1537                                       700)) {
1538                         DRM_ERROR("%s: reset request timeout\n", engine->name);
1539                         goto not_ready;
1540                 }
1541         }
1542
1543         return gen6_do_reset(dev);
1544
1545 not_ready:
1546         for_each_ring(engine, dev_priv, i)
1547                 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1548                            _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1549
1550         return -EIO;
1551 }
1552
1553 static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *)
1554 {
1555         if (!i915.reset)
1556                 return NULL;
1557
1558         if (INTEL_INFO(dev)->gen >= 8)
1559                 return gen8_do_reset;
1560         else if (INTEL_INFO(dev)->gen >= 6)
1561                 return gen6_do_reset;
1562         else if (IS_GEN5(dev))
1563                 return ironlake_do_reset;
1564         else if (IS_G4X(dev))
1565                 return g4x_do_reset;
1566         else if (IS_G33(dev))
1567                 return g33_do_reset;
1568         else if (INTEL_INFO(dev)->gen >= 3)
1569                 return i915_do_reset;
1570         else
1571                 return NULL;
1572 }
1573
1574 int intel_gpu_reset(struct drm_device *dev)
1575 {
1576         struct drm_i915_private *dev_priv = to_i915(dev);
1577         int (*reset)(struct drm_device *);
1578         int ret;
1579
1580         reset = intel_get_gpu_reset(dev);
1581         if (reset == NULL)
1582                 return -ENODEV;
1583
1584         /* If the power well sleeps during the reset, the reset
1585          * request may be dropped and never completes (causing -EIO).
1586          */
1587         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1588         ret = reset(dev);
1589         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1590
1591         return ret;
1592 }
1593
1594 bool intel_has_gpu_reset(struct drm_device *dev)
1595 {
1596         return intel_get_gpu_reset(dev) != NULL;
1597 }
1598
1599 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1600 {
1601         return check_for_unclaimed_mmio(dev_priv);
1602 }