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drm/i915: put runtime PM only when we actually release force_wake
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_uncore.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "i915_drv.h"
25 #include "intel_drv.h"
26
27 #define FORCEWAKE_ACK_TIMEOUT_MS 2
28
29 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
31
32 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
34
35 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
37
38 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
40
41 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
42
43
44 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
45 {
46 u32 gt_thread_status_mask;
47
48 if (IS_HASWELL(dev_priv->dev))
49 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
50 else
51 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
52
53 /* w/a for a sporadic read returning 0 by waiting for the GT
54 * thread to wake up.
55 */
56 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
57 DRM_ERROR("GT thread status wait timed out\n");
58 }
59
60 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
61 {
62 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
63 /* something from same cacheline, but !FORCEWAKE */
64 __raw_posting_read(dev_priv, ECOBUS);
65 }
66
67 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
68 int fw_engine)
69 {
70 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
71 FORCEWAKE_ACK_TIMEOUT_MS))
72 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
73
74 __raw_i915_write32(dev_priv, FORCEWAKE, 1);
75 /* something from same cacheline, but !FORCEWAKE */
76 __raw_posting_read(dev_priv, ECOBUS);
77
78 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
79 FORCEWAKE_ACK_TIMEOUT_MS))
80 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
81
82 /* WaRsForcewakeWaitTC0:snb */
83 __gen6_gt_wait_for_thread_c0(dev_priv);
84 }
85
86 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
87 {
88 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
89 /* something from same cacheline, but !FORCEWAKE_MT */
90 __raw_posting_read(dev_priv, ECOBUS);
91 }
92
93 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
94 int fw_engine)
95 {
96 u32 forcewake_ack;
97
98 if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
99 forcewake_ack = FORCEWAKE_ACK_HSW;
100 else
101 forcewake_ack = FORCEWAKE_MT_ACK;
102
103 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
104 FORCEWAKE_ACK_TIMEOUT_MS))
105 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
106
107 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
108 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
109 /* something from same cacheline, but !FORCEWAKE_MT */
110 __raw_posting_read(dev_priv, ECOBUS);
111
112 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
113 FORCEWAKE_ACK_TIMEOUT_MS))
114 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
115
116 /* WaRsForcewakeWaitTC0:ivb,hsw */
117 if (INTEL_INFO(dev_priv->dev)->gen < 8)
118 __gen6_gt_wait_for_thread_c0(dev_priv);
119 }
120
121 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
122 {
123 u32 gtfifodbg;
124
125 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
126 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
127 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
128 }
129
130 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
131 int fw_engine)
132 {
133 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
134 /* something from same cacheline, but !FORCEWAKE */
135 __raw_posting_read(dev_priv, ECOBUS);
136 gen6_gt_check_fifodbg(dev_priv);
137 }
138
139 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
140 int fw_engine)
141 {
142 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
143 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
144 /* something from same cacheline, but !FORCEWAKE_MT */
145 __raw_posting_read(dev_priv, ECOBUS);
146 gen6_gt_check_fifodbg(dev_priv);
147 }
148
149 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
150 {
151 int ret = 0;
152
153 /* On VLV, FIFO will be shared by both SW and HW.
154 * So, we need to read the FREE_ENTRIES everytime */
155 if (IS_VALLEYVIEW(dev_priv->dev))
156 dev_priv->uncore.fifo_count =
157 __raw_i915_read32(dev_priv, GTFIFOCTL) &
158 GT_FIFO_FREE_ENTRIES_MASK;
159
160 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
161 int loop = 500;
162 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
163 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
164 udelay(10);
165 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
166 }
167 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
168 ++ret;
169 dev_priv->uncore.fifo_count = fifo;
170 }
171 dev_priv->uncore.fifo_count--;
172
173 return ret;
174 }
175
176 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
177 {
178 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
179 _MASKED_BIT_DISABLE(0xffff));
180 /* something from same cacheline, but !FORCEWAKE_VLV */
181 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
182 }
183
184 static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
185 int fw_engine)
186 {
187 /* Check for Render Engine */
188 if (FORCEWAKE_RENDER & fw_engine) {
189 if (wait_for_atomic((__raw_i915_read32(dev_priv,
190 FORCEWAKE_ACK_VLV) &
191 FORCEWAKE_KERNEL) == 0,
192 FORCEWAKE_ACK_TIMEOUT_MS))
193 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
194
195 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
196 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
197
198 if (wait_for_atomic((__raw_i915_read32(dev_priv,
199 FORCEWAKE_ACK_VLV) &
200 FORCEWAKE_KERNEL),
201 FORCEWAKE_ACK_TIMEOUT_MS))
202 DRM_ERROR("Timed out: waiting for Render to ack.\n");
203 }
204
205 /* Check for Media Engine */
206 if (FORCEWAKE_MEDIA & fw_engine) {
207 if (wait_for_atomic((__raw_i915_read32(dev_priv,
208 FORCEWAKE_ACK_MEDIA_VLV) &
209 FORCEWAKE_KERNEL) == 0,
210 FORCEWAKE_ACK_TIMEOUT_MS))
211 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
212
213 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
214 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
215
216 if (wait_for_atomic((__raw_i915_read32(dev_priv,
217 FORCEWAKE_ACK_MEDIA_VLV) &
218 FORCEWAKE_KERNEL),
219 FORCEWAKE_ACK_TIMEOUT_MS))
220 DRM_ERROR("Timed out: waiting for media to ack.\n");
221 }
222
223 /* WaRsForcewakeWaitTC0:vlv */
224 __gen6_gt_wait_for_thread_c0(dev_priv);
225
226 }
227
228 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
229 int fw_engine)
230 {
231
232 /* Check for Render Engine */
233 if (FORCEWAKE_RENDER & fw_engine)
234 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
235 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
236
237
238 /* Check for Media Engine */
239 if (FORCEWAKE_MEDIA & fw_engine)
240 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
241 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
242
243 /* The below doubles as a POSTING_READ */
244 gen6_gt_check_fifodbg(dev_priv);
245
246 }
247
248 void vlv_force_wake_get(struct drm_i915_private *dev_priv,
249 int fw_engine)
250 {
251 unsigned long irqflags;
252
253 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
254 if (FORCEWAKE_RENDER & fw_engine) {
255 if (dev_priv->uncore.fw_rendercount++ == 0)
256 dev_priv->uncore.funcs.force_wake_get(dev_priv,
257 FORCEWAKE_RENDER);
258 }
259 if (FORCEWAKE_MEDIA & fw_engine) {
260 if (dev_priv->uncore.fw_mediacount++ == 0)
261 dev_priv->uncore.funcs.force_wake_get(dev_priv,
262 FORCEWAKE_MEDIA);
263 }
264
265 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
266 }
267
268 void vlv_force_wake_put(struct drm_i915_private *dev_priv,
269 int fw_engine)
270 {
271 unsigned long irqflags;
272
273 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
274
275 if (FORCEWAKE_RENDER & fw_engine) {
276 WARN_ON(dev_priv->uncore.fw_rendercount == 0);
277 if (--dev_priv->uncore.fw_rendercount == 0)
278 dev_priv->uncore.funcs.force_wake_put(dev_priv,
279 FORCEWAKE_RENDER);
280 }
281
282 if (FORCEWAKE_MEDIA & fw_engine) {
283 WARN_ON(dev_priv->uncore.fw_mediacount == 0);
284 if (--dev_priv->uncore.fw_mediacount == 0)
285 dev_priv->uncore.funcs.force_wake_put(dev_priv,
286 FORCEWAKE_MEDIA);
287 }
288
289 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
290 }
291
292 static void gen6_force_wake_timer(unsigned long arg)
293 {
294 struct drm_i915_private *dev_priv = (void *)arg;
295 unsigned long irqflags;
296
297 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
298 if (--dev_priv->uncore.forcewake_count == 0)
299 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
300 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
301
302 intel_runtime_pm_put(dev_priv);
303 }
304
305 static void intel_uncore_forcewake_reset(struct drm_device *dev)
306 {
307 struct drm_i915_private *dev_priv = dev->dev_private;
308
309 if (IS_VALLEYVIEW(dev)) {
310 vlv_force_wake_reset(dev_priv);
311 } else if (INTEL_INFO(dev)->gen >= 6) {
312 __gen6_gt_force_wake_reset(dev_priv);
313 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
314 __gen6_gt_force_wake_mt_reset(dev_priv);
315 }
316 }
317
318 void intel_uncore_early_sanitize(struct drm_device *dev)
319 {
320 struct drm_i915_private *dev_priv = dev->dev_private;
321
322 if (HAS_FPGA_DBG_UNCLAIMED(dev))
323 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
324
325 if (IS_HASWELL(dev) &&
326 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
327 /* The docs do not explain exactly how the calculation can be
328 * made. It is somewhat guessable, but for now, it's always
329 * 128MB.
330 * NB: We can't write IDICR yet because we do not have gt funcs
331 * set up */
332 dev_priv->ellc_size = 128;
333 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
334 }
335
336 /* clear out old GT FIFO errors */
337 if (IS_GEN6(dev) || IS_GEN7(dev))
338 __raw_i915_write32(dev_priv, GTFIFODBG,
339 __raw_i915_read32(dev_priv, GTFIFODBG));
340
341 intel_uncore_forcewake_reset(dev);
342 }
343
344 void intel_uncore_sanitize(struct drm_device *dev)
345 {
346 struct drm_i915_private *dev_priv = dev->dev_private;
347 u32 reg_val;
348
349 /* BIOS often leaves RC6 enabled, but disable it for hw init */
350 intel_disable_gt_powersave(dev);
351
352 /* Turn off power gate, require especially for the BIOS less system */
353 if (IS_VALLEYVIEW(dev)) {
354
355 mutex_lock(&dev_priv->rps.hw_lock);
356 reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
357
358 if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT))
359 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
360
361 mutex_unlock(&dev_priv->rps.hw_lock);
362
363 }
364 }
365
366 /*
367 * Generally this is called implicitly by the register read function. However,
368 * if some sequence requires the GT to not power down then this function should
369 * be called at the beginning of the sequence followed by a call to
370 * gen6_gt_force_wake_put() at the end of the sequence.
371 */
372 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
373 {
374 unsigned long irqflags;
375
376 if (!dev_priv->uncore.funcs.force_wake_get)
377 return;
378
379 intel_runtime_pm_get(dev_priv);
380
381 /* Redirect to VLV specific routine */
382 if (IS_VALLEYVIEW(dev_priv->dev))
383 return vlv_force_wake_get(dev_priv, fw_engine);
384
385 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
386 if (dev_priv->uncore.forcewake_count++ == 0)
387 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
388 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
389 }
390
391 /*
392 * see gen6_gt_force_wake_get()
393 */
394 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
395 {
396 unsigned long irqflags;
397 bool delayed = false;
398
399 if (!dev_priv->uncore.funcs.force_wake_put)
400 return;
401
402 /* Redirect to VLV specific routine */
403 if (IS_VALLEYVIEW(dev_priv->dev)) {
404 vlv_force_wake_put(dev_priv, fw_engine);
405 goto out;
406 }
407
408
409 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
410 if (--dev_priv->uncore.forcewake_count == 0) {
411 dev_priv->uncore.forcewake_count++;
412 delayed = true;
413 mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
414 jiffies + 1);
415 }
416 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
417
418 out:
419 if (!delayed)
420 intel_runtime_pm_put(dev_priv);
421 }
422
423 /* We give fast paths for the really cool registers */
424 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
425 ((reg) < 0x40000 && (reg) != FORCEWAKE)
426
427 static void
428 ilk_dummy_write(struct drm_i915_private *dev_priv)
429 {
430 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
431 * the chip from rc6 before touching it for real. MI_MODE is masked,
432 * hence harmless to write 0 into. */
433 __raw_i915_write32(dev_priv, MI_MODE, 0);
434 }
435
436 static void
437 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
438 {
439 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
440 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
441 reg);
442 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
443 }
444 }
445
446 static void
447 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
448 {
449 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
450 DRM_ERROR("Unclaimed write to %x\n", reg);
451 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
452 }
453 }
454
455 static void
456 assert_device_not_suspended(struct drm_i915_private *dev_priv)
457 {
458 WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
459 "Device suspended\n");
460 }
461
462 #define REG_READ_HEADER(x) \
463 unsigned long irqflags; \
464 u##x val = 0; \
465 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
466
467 #define REG_READ_FOOTER \
468 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
469 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
470 return val
471
472 #define __gen4_read(x) \
473 static u##x \
474 gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
475 REG_READ_HEADER(x); \
476 val = __raw_i915_read##x(dev_priv, reg); \
477 REG_READ_FOOTER; \
478 }
479
480 #define __gen5_read(x) \
481 static u##x \
482 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
483 REG_READ_HEADER(x); \
484 ilk_dummy_write(dev_priv); \
485 val = __raw_i915_read##x(dev_priv, reg); \
486 REG_READ_FOOTER; \
487 }
488
489 #define __gen6_read(x) \
490 static u##x \
491 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
492 REG_READ_HEADER(x); \
493 if (dev_priv->uncore.forcewake_count == 0 && \
494 NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
495 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
496 FORCEWAKE_ALL); \
497 dev_priv->uncore.forcewake_count++; \
498 mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \
499 jiffies + 1); \
500 } \
501 val = __raw_i915_read##x(dev_priv, reg); \
502 REG_READ_FOOTER; \
503 }
504
505 #define __vlv_read(x) \
506 static u##x \
507 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
508 unsigned fwengine = 0; \
509 unsigned *fwcount; \
510 REG_READ_HEADER(x); \
511 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
512 fwengine = FORCEWAKE_RENDER; \
513 fwcount = &dev_priv->uncore.fw_rendercount; \
514 } \
515 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
516 fwengine = FORCEWAKE_MEDIA; \
517 fwcount = &dev_priv->uncore.fw_mediacount; \
518 } \
519 if (fwengine != 0) { \
520 if ((*fwcount)++ == 0) \
521 (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
522 fwengine); \
523 val = __raw_i915_read##x(dev_priv, reg); \
524 if (--(*fwcount) == 0) \
525 (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
526 fwengine); \
527 } else { \
528 val = __raw_i915_read##x(dev_priv, reg); \
529 } \
530 REG_READ_FOOTER; \
531 }
532
533
534 __vlv_read(8)
535 __vlv_read(16)
536 __vlv_read(32)
537 __vlv_read(64)
538 __gen6_read(8)
539 __gen6_read(16)
540 __gen6_read(32)
541 __gen6_read(64)
542 __gen5_read(8)
543 __gen5_read(16)
544 __gen5_read(32)
545 __gen5_read(64)
546 __gen4_read(8)
547 __gen4_read(16)
548 __gen4_read(32)
549 __gen4_read(64)
550
551 #undef __vlv_read
552 #undef __gen6_read
553 #undef __gen5_read
554 #undef __gen4_read
555 #undef REG_READ_FOOTER
556 #undef REG_READ_HEADER
557
558 #define REG_WRITE_HEADER \
559 unsigned long irqflags; \
560 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
561 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
562
563 #define REG_WRITE_FOOTER \
564 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
565
566 #define __gen4_write(x) \
567 static void \
568 gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
569 REG_WRITE_HEADER; \
570 __raw_i915_write##x(dev_priv, reg, val); \
571 REG_WRITE_FOOTER; \
572 }
573
574 #define __gen5_write(x) \
575 static void \
576 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
577 REG_WRITE_HEADER; \
578 ilk_dummy_write(dev_priv); \
579 __raw_i915_write##x(dev_priv, reg, val); \
580 REG_WRITE_FOOTER; \
581 }
582
583 #define __gen6_write(x) \
584 static void \
585 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
586 u32 __fifo_ret = 0; \
587 REG_WRITE_HEADER; \
588 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
589 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
590 } \
591 assert_device_not_suspended(dev_priv); \
592 __raw_i915_write##x(dev_priv, reg, val); \
593 if (unlikely(__fifo_ret)) { \
594 gen6_gt_check_fifodbg(dev_priv); \
595 } \
596 REG_WRITE_FOOTER; \
597 }
598
599 #define __hsw_write(x) \
600 static void \
601 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
602 u32 __fifo_ret = 0; \
603 REG_WRITE_HEADER; \
604 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
605 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
606 } \
607 assert_device_not_suspended(dev_priv); \
608 hsw_unclaimed_reg_clear(dev_priv, reg); \
609 __raw_i915_write##x(dev_priv, reg, val); \
610 if (unlikely(__fifo_ret)) { \
611 gen6_gt_check_fifodbg(dev_priv); \
612 } \
613 hsw_unclaimed_reg_check(dev_priv, reg); \
614 REG_WRITE_FOOTER; \
615 }
616
617 static const u32 gen8_shadowed_regs[] = {
618 FORCEWAKE_MT,
619 GEN6_RPNSWREQ,
620 GEN6_RC_VIDEO_FREQ,
621 RING_TAIL(RENDER_RING_BASE),
622 RING_TAIL(GEN6_BSD_RING_BASE),
623 RING_TAIL(VEBOX_RING_BASE),
624 RING_TAIL(BLT_RING_BASE),
625 /* TODO: Other registers are not yet used */
626 };
627
628 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
629 {
630 int i;
631 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
632 if (reg == gen8_shadowed_regs[i])
633 return true;
634
635 return false;
636 }
637
638 #define __gen8_write(x) \
639 static void \
640 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
641 REG_WRITE_HEADER; \
642 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
643 if (dev_priv->uncore.forcewake_count == 0) \
644 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
645 FORCEWAKE_ALL); \
646 __raw_i915_write##x(dev_priv, reg, val); \
647 if (dev_priv->uncore.forcewake_count == 0) \
648 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
649 FORCEWAKE_ALL); \
650 } else { \
651 __raw_i915_write##x(dev_priv, reg, val); \
652 } \
653 REG_WRITE_FOOTER; \
654 }
655
656 __gen8_write(8)
657 __gen8_write(16)
658 __gen8_write(32)
659 __gen8_write(64)
660 __hsw_write(8)
661 __hsw_write(16)
662 __hsw_write(32)
663 __hsw_write(64)
664 __gen6_write(8)
665 __gen6_write(16)
666 __gen6_write(32)
667 __gen6_write(64)
668 __gen5_write(8)
669 __gen5_write(16)
670 __gen5_write(32)
671 __gen5_write(64)
672 __gen4_write(8)
673 __gen4_write(16)
674 __gen4_write(32)
675 __gen4_write(64)
676
677 #undef __gen8_write
678 #undef __hsw_write
679 #undef __gen6_write
680 #undef __gen5_write
681 #undef __gen4_write
682 #undef REG_WRITE_FOOTER
683 #undef REG_WRITE_HEADER
684
685 void intel_uncore_init(struct drm_device *dev)
686 {
687 struct drm_i915_private *dev_priv = dev->dev_private;
688
689 setup_timer(&dev_priv->uncore.force_wake_timer,
690 gen6_force_wake_timer, (unsigned long)dev_priv);
691
692 if (IS_VALLEYVIEW(dev)) {
693 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
694 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
695 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
696 dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get;
697 dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put;
698 } else if (IS_IVYBRIDGE(dev)) {
699 u32 ecobus;
700
701 /* IVB configs may use multi-threaded forcewake */
702
703 /* A small trick here - if the bios hasn't configured
704 * MT forcewake, and if the device is in RC6, then
705 * force_wake_mt_get will not wake the device and the
706 * ECOBUS read will return zero. Which will be
707 * (correctly) interpreted by the test below as MT
708 * forcewake being disabled.
709 */
710 mutex_lock(&dev->struct_mutex);
711 __gen6_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
712 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
713 __gen6_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
714 mutex_unlock(&dev->struct_mutex);
715
716 if (ecobus & FORCEWAKE_MT_ENABLE) {
717 dev_priv->uncore.funcs.force_wake_get =
718 __gen6_gt_force_wake_mt_get;
719 dev_priv->uncore.funcs.force_wake_put =
720 __gen6_gt_force_wake_mt_put;
721 } else {
722 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
723 DRM_INFO("when using vblank-synced partial screen updates.\n");
724 dev_priv->uncore.funcs.force_wake_get =
725 __gen6_gt_force_wake_get;
726 dev_priv->uncore.funcs.force_wake_put =
727 __gen6_gt_force_wake_put;
728 }
729 } else if (IS_GEN6(dev)) {
730 dev_priv->uncore.funcs.force_wake_get =
731 __gen6_gt_force_wake_get;
732 dev_priv->uncore.funcs.force_wake_put =
733 __gen6_gt_force_wake_put;
734 }
735
736 switch (INTEL_INFO(dev)->gen) {
737 default:
738 dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
739 dev_priv->uncore.funcs.mmio_writew = gen8_write16;
740 dev_priv->uncore.funcs.mmio_writel = gen8_write32;
741 dev_priv->uncore.funcs.mmio_writeq = gen8_write64;
742 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
743 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
744 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
745 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
746 break;
747 case 7:
748 case 6:
749 if (IS_HASWELL(dev)) {
750 dev_priv->uncore.funcs.mmio_writeb = hsw_write8;
751 dev_priv->uncore.funcs.mmio_writew = hsw_write16;
752 dev_priv->uncore.funcs.mmio_writel = hsw_write32;
753 dev_priv->uncore.funcs.mmio_writeq = hsw_write64;
754 } else {
755 dev_priv->uncore.funcs.mmio_writeb = gen6_write8;
756 dev_priv->uncore.funcs.mmio_writew = gen6_write16;
757 dev_priv->uncore.funcs.mmio_writel = gen6_write32;
758 dev_priv->uncore.funcs.mmio_writeq = gen6_write64;
759 }
760
761 if (IS_VALLEYVIEW(dev)) {
762 dev_priv->uncore.funcs.mmio_readb = vlv_read8;
763 dev_priv->uncore.funcs.mmio_readw = vlv_read16;
764 dev_priv->uncore.funcs.mmio_readl = vlv_read32;
765 dev_priv->uncore.funcs.mmio_readq = vlv_read64;
766 } else {
767 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
768 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
769 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
770 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
771 }
772 break;
773 case 5:
774 dev_priv->uncore.funcs.mmio_writeb = gen5_write8;
775 dev_priv->uncore.funcs.mmio_writew = gen5_write16;
776 dev_priv->uncore.funcs.mmio_writel = gen5_write32;
777 dev_priv->uncore.funcs.mmio_writeq = gen5_write64;
778 dev_priv->uncore.funcs.mmio_readb = gen5_read8;
779 dev_priv->uncore.funcs.mmio_readw = gen5_read16;
780 dev_priv->uncore.funcs.mmio_readl = gen5_read32;
781 dev_priv->uncore.funcs.mmio_readq = gen5_read64;
782 break;
783 case 4:
784 case 3:
785 case 2:
786 dev_priv->uncore.funcs.mmio_writeb = gen4_write8;
787 dev_priv->uncore.funcs.mmio_writew = gen4_write16;
788 dev_priv->uncore.funcs.mmio_writel = gen4_write32;
789 dev_priv->uncore.funcs.mmio_writeq = gen4_write64;
790 dev_priv->uncore.funcs.mmio_readb = gen4_read8;
791 dev_priv->uncore.funcs.mmio_readw = gen4_read16;
792 dev_priv->uncore.funcs.mmio_readl = gen4_read32;
793 dev_priv->uncore.funcs.mmio_readq = gen4_read64;
794 break;
795 }
796 }
797
798 void intel_uncore_fini(struct drm_device *dev)
799 {
800 struct drm_i915_private *dev_priv = dev->dev_private;
801
802 del_timer_sync(&dev_priv->uncore.force_wake_timer);
803
804 /* Paranoia: make sure we have disabled everything before we exit. */
805 intel_uncore_sanitize(dev);
806 intel_uncore_forcewake_reset(dev);
807 }
808
809 static const struct register_whitelist {
810 uint64_t offset;
811 uint32_t size;
812 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
813 } whitelist[] = {
814 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0x1F0 },
815 };
816
817 int i915_reg_read_ioctl(struct drm_device *dev,
818 void *data, struct drm_file *file)
819 {
820 struct drm_i915_private *dev_priv = dev->dev_private;
821 struct drm_i915_reg_read *reg = data;
822 struct register_whitelist const *entry = whitelist;
823 int i;
824
825 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
826 if (entry->offset == reg->offset &&
827 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
828 break;
829 }
830
831 if (i == ARRAY_SIZE(whitelist))
832 return -EINVAL;
833
834 switch (entry->size) {
835 case 8:
836 reg->val = I915_READ64(reg->offset);
837 break;
838 case 4:
839 reg->val = I915_READ(reg->offset);
840 break;
841 case 2:
842 reg->val = I915_READ16(reg->offset);
843 break;
844 case 1:
845 reg->val = I915_READ8(reg->offset);
846 break;
847 default:
848 WARN_ON(1);
849 return -EINVAL;
850 }
851
852 return 0;
853 }
854
855 int i915_get_reset_stats_ioctl(struct drm_device *dev,
856 void *data, struct drm_file *file)
857 {
858 struct drm_i915_private *dev_priv = dev->dev_private;
859 struct drm_i915_reset_stats *args = data;
860 struct i915_ctx_hang_stats *hs;
861 struct i915_hw_context *ctx;
862 int ret;
863
864 if (args->flags || args->pad)
865 return -EINVAL;
866
867 if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN))
868 return -EPERM;
869
870 ret = mutex_lock_interruptible(&dev->struct_mutex);
871 if (ret)
872 return ret;
873
874 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
875 if (IS_ERR(ctx)) {
876 mutex_unlock(&dev->struct_mutex);
877 return PTR_ERR(ctx);
878 }
879 hs = &ctx->hang_stats;
880
881 if (capable(CAP_SYS_ADMIN))
882 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
883 else
884 args->reset_count = 0;
885
886 args->batch_active = hs->batch_active;
887 args->batch_pending = hs->batch_pending;
888
889 mutex_unlock(&dev->struct_mutex);
890
891 return 0;
892 }
893
894 static int i965_reset_complete(struct drm_device *dev)
895 {
896 u8 gdrst;
897 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
898 return (gdrst & GRDOM_RESET_ENABLE) == 0;
899 }
900
901 static int i965_do_reset(struct drm_device *dev)
902 {
903 int ret;
904
905 /*
906 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
907 * well as the reset bit (GR/bit 0). Setting the GR bit
908 * triggers the reset; when done, the hardware will clear it.
909 */
910 pci_write_config_byte(dev->pdev, I965_GDRST,
911 GRDOM_RENDER | GRDOM_RESET_ENABLE);
912 ret = wait_for(i965_reset_complete(dev), 500);
913 if (ret)
914 return ret;
915
916 /* We can't reset render&media without also resetting display ... */
917 pci_write_config_byte(dev->pdev, I965_GDRST,
918 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
919
920 ret = wait_for(i965_reset_complete(dev), 500);
921 if (ret)
922 return ret;
923
924 pci_write_config_byte(dev->pdev, I965_GDRST, 0);
925
926 return 0;
927 }
928
929 static int ironlake_do_reset(struct drm_device *dev)
930 {
931 struct drm_i915_private *dev_priv = dev->dev_private;
932 u32 gdrst;
933 int ret;
934
935 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
936 gdrst &= ~GRDOM_MASK;
937 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
938 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
939 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
940 if (ret)
941 return ret;
942
943 /* We can't reset render&media without also resetting display ... */
944 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
945 gdrst &= ~GRDOM_MASK;
946 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
947 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
948 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
949 }
950
951 static int gen6_do_reset(struct drm_device *dev)
952 {
953 struct drm_i915_private *dev_priv = dev->dev_private;
954 int ret;
955 unsigned long irqflags;
956
957 /* Hold uncore.lock across reset to prevent any register access
958 * with forcewake not set correctly
959 */
960 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
961
962 /* Reset the chip */
963
964 /* GEN6_GDRST is not in the gt power well, no need to check
965 * for fifo space for the write or forcewake the chip for
966 * the read
967 */
968 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
969
970 /* Spin waiting for the device to ack the reset request */
971 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
972
973 intel_uncore_forcewake_reset(dev);
974
975 /* If reset with a user forcewake, try to restore, otherwise turn it off */
976 if (dev_priv->uncore.forcewake_count)
977 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
978 else
979 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
980
981 /* Restore fifo count */
982 dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
983
984 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
985 return ret;
986 }
987
988 int intel_gpu_reset(struct drm_device *dev)
989 {
990 switch (INTEL_INFO(dev)->gen) {
991 case 8:
992 case 7:
993 case 6: return gen6_do_reset(dev);
994 case 5: return ironlake_do_reset(dev);
995 case 4: return i965_do_reset(dev);
996 default: return -ENODEV;
997 }
998 }
999
1000 void intel_uncore_check_errors(struct drm_device *dev)
1001 {
1002 struct drm_i915_private *dev_priv = dev->dev_private;
1003
1004 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1005 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1006 DRM_ERROR("Unclaimed register before interrupt\n");
1007 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1008 }
1009 }
Linux kernel - Deliverables
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