drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26
  27 #include <linux/pm_runtime.h>
  28
  29 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  30
  31 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
  32 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
  33
  34 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
  35 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
  36
  37 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  38 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
  39
  40 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
  41 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
  42
  43 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  44
  45 static void
  46 assert_device_not_suspended(struct drm_i915_private *dev_priv)
  47 {
  48         WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
  49                   "Device suspended\n");
  50 }
  51
  52 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
  53 {
  54         /* w/a for a sporadic read returning 0 by waiting for the GT
  55          * thread to wake up.
  56          */
  57         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
  58                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
  59                 DRM_ERROR("GT thread status wait timed out\n");
  60 }
  61
  62 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
  63 {
  64         __raw_i915_write32(dev_priv, FORCEWAKE, 0);
  65         /* something from same cacheline, but !FORCEWAKE */
  66         __raw_posting_read(dev_priv, ECOBUS);
  67 }
  68
  69 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
  70                                                         int fw_engine)
  71 {
  72         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
  73                             FORCEWAKE_ACK_TIMEOUT_MS))
  74                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
  75
  76         __raw_i915_write32(dev_priv, FORCEWAKE, 1);
  77         /* something from same cacheline, but !FORCEWAKE */
  78         __raw_posting_read(dev_priv, ECOBUS);
  79
  80         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
  81                             FORCEWAKE_ACK_TIMEOUT_MS))
  82                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
  83
  84         /* WaRsForcewakeWaitTC0:snb */
  85         __gen6_gt_wait_for_thread_c0(dev_priv);
  86 }
  87
  88 static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
  89 {
  90         __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
  91         /* something from same cacheline, but !FORCEWAKE_MT */
  92         __raw_posting_read(dev_priv, ECOBUS);
  93 }
  94
  95 static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
  96                                                         int fw_engine)
  97 {
  98         u32 forcewake_ack;
  99
 100         if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev))
 101                 forcewake_ack = FORCEWAKE_ACK_HSW;
 102         else
 103                 forcewake_ack = FORCEWAKE_MT_ACK;
 104
 105         if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
 106                             FORCEWAKE_ACK_TIMEOUT_MS))
 107                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
 108
 109         __raw_i915_write32(dev_priv, FORCEWAKE_MT,
 110                            _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 111         /* something from same cacheline, but !FORCEWAKE_MT */
 112         __raw_posting_read(dev_priv, ECOBUS);
 113
 114         if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
 115                             FORCEWAKE_ACK_TIMEOUT_MS))
 116                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
 117
 118         /* WaRsForcewakeWaitTC0:ivb,hsw */
 119         __gen6_gt_wait_for_thread_c0(dev_priv);
 120 }
 121
 122 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 123 {
 124         u32 gtfifodbg;
 125
 126         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 127         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 128                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 129 }
 130
 131 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
 132                                                         int fw_engine)
 133 {
 134         __raw_i915_write32(dev_priv, FORCEWAKE, 0);
 135         /* something from same cacheline, but !FORCEWAKE */
 136         __raw_posting_read(dev_priv, ECOBUS);
 137         gen6_gt_check_fifodbg(dev_priv);
 138 }
 139
 140 static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
 141                                                         int fw_engine)
 142 {
 143         __raw_i915_write32(dev_priv, FORCEWAKE_MT,
 144                            _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 145         /* something from same cacheline, but !FORCEWAKE_MT */
 146         __raw_posting_read(dev_priv, ECOBUS);
 147
 148         if (IS_GEN7(dev_priv->dev))
 149                 gen6_gt_check_fifodbg(dev_priv);
 150 }
 151
 152 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 153 {
 154         int ret = 0;
 155
 156         /* On VLV, FIFO will be shared by both SW and HW.
 157          * So, we need to read the FREE_ENTRIES everytime */
 158         if (IS_VALLEYVIEW(dev_priv->dev))
 159                 dev_priv->uncore.fifo_count =
 160                         __raw_i915_read32(dev_priv, GTFIFOCTL) &
 161                                                 GT_FIFO_FREE_ENTRIES_MASK;
 162
 163         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 164                 int loop = 500;
 165                 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 166                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 167                         udelay(10);
 168                         fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 169                 }
 170                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 171                         ++ret;
 172                 dev_priv->uncore.fifo_count = fifo;
 173         }
 174         dev_priv->uncore.fifo_count--;
 175
 176         return ret;
 177 }
 178
 179 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
 180 {
 181         __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 182                            _MASKED_BIT_DISABLE(0xffff));
 183         __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 184                            _MASKED_BIT_DISABLE(0xffff));
 185         /* something from same cacheline, but !FORCEWAKE_VLV */
 186         __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
 187 }
 188
 189 static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
 190                                                 int fw_engine)
 191 {
 192         /* Check for Render Engine */
 193         if (FORCEWAKE_RENDER & fw_engine) {
 194                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 195                                                 FORCEWAKE_ACK_VLV) &
 196                                                 FORCEWAKE_KERNEL) == 0,
 197                                         FORCEWAKE_ACK_TIMEOUT_MS))
 198                         DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
 199
 200                 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 201                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 202
 203                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 204                                                 FORCEWAKE_ACK_VLV) &
 205                                                 FORCEWAKE_KERNEL),
 206                                         FORCEWAKE_ACK_TIMEOUT_MS))
 207                         DRM_ERROR("Timed out: waiting for Render to ack.\n");
 208         }
 209
 210         /* Check for Media Engine */
 211         if (FORCEWAKE_MEDIA & fw_engine) {
 212                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 213                                                 FORCEWAKE_ACK_MEDIA_VLV) &
 214                                                 FORCEWAKE_KERNEL) == 0,
 215                                         FORCEWAKE_ACK_TIMEOUT_MS))
 216                         DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
 217
 218                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 219                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 220
 221                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 222                                                 FORCEWAKE_ACK_MEDIA_VLV) &
 223                                                 FORCEWAKE_KERNEL),
 224                                         FORCEWAKE_ACK_TIMEOUT_MS))
 225                         DRM_ERROR("Timed out: waiting for media to ack.\n");
 226         }
 227 }
 228
 229 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
 230                                         int fw_engine)
 231 {
 232
 233         /* Check for Render Engine */
 234         if (FORCEWAKE_RENDER & fw_engine)
 235                 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 236                                         _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 237
 238
 239         /* Check for Media Engine */
 240         if (FORCEWAKE_MEDIA & fw_engine)
 241                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 242                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 243
 244         /* something from same cacheline, but !FORCEWAKE_VLV */
 245         __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
 246         if (!IS_CHERRYVIEW(dev_priv->dev))
 247                 gen6_gt_check_fifodbg(dev_priv);
 248 }
 249
 250 static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 251 {
 252         if (fw_engine & FORCEWAKE_RENDER &&
 253             dev_priv->uncore.fw_rendercount++ != 0)
 254                 fw_engine &= ~FORCEWAKE_RENDER;
 255         if (fw_engine & FORCEWAKE_MEDIA &&
 256             dev_priv->uncore.fw_mediacount++ != 0)
 257                 fw_engine &= ~FORCEWAKE_MEDIA;
 258
 259         if (fw_engine)
 260                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
 261 }
 262
 263 static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 264 {
 265         if (fw_engine & FORCEWAKE_RENDER) {
 266                 WARN_ON(!dev_priv->uncore.fw_rendercount);
 267                 if (--dev_priv->uncore.fw_rendercount != 0)
 268                         fw_engine &= ~FORCEWAKE_RENDER;
 269         }
 270
 271         if (fw_engine & FORCEWAKE_MEDIA) {
 272                 WARN_ON(!dev_priv->uncore.fw_mediacount);
 273                 if (--dev_priv->uncore.fw_mediacount != 0)
 274                         fw_engine &= ~FORCEWAKE_MEDIA;
 275         }
 276
 277         if (fw_engine)
 278                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine);
 279 }
 280
 281 static void __gen9_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
 282 {
 283         __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
 284                         _MASKED_BIT_DISABLE(0xffff));
 285
 286         __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
 287                         _MASKED_BIT_DISABLE(0xffff));
 288
 289         __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
 290                         _MASKED_BIT_DISABLE(0xffff));
 291 }
 292
 293 static void
 294 __gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 295 {
 296         /* Check for Render Engine */
 297         if (FORCEWAKE_RENDER & fw_engine) {
 298                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 299                                                 FORCEWAKE_ACK_RENDER_GEN9) &
 300                                                 FORCEWAKE_KERNEL) == 0,
 301                                         FORCEWAKE_ACK_TIMEOUT_MS))
 302                         DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
 303
 304                 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
 305                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 306
 307                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 308                                                 FORCEWAKE_ACK_RENDER_GEN9) &
 309                                                 FORCEWAKE_KERNEL),
 310                                         FORCEWAKE_ACK_TIMEOUT_MS))
 311                         DRM_ERROR("Timed out: waiting for Render to ack.\n");
 312         }
 313
 314         /* Check for Media Engine */
 315         if (FORCEWAKE_MEDIA & fw_engine) {
 316                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 317                                                 FORCEWAKE_ACK_MEDIA_GEN9) &
 318                                                 FORCEWAKE_KERNEL) == 0,
 319                                         FORCEWAKE_ACK_TIMEOUT_MS))
 320                         DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
 321
 322                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
 323                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 324
 325                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 326                                                 FORCEWAKE_ACK_MEDIA_GEN9) &
 327                                                 FORCEWAKE_KERNEL),
 328                                         FORCEWAKE_ACK_TIMEOUT_MS))
 329                         DRM_ERROR("Timed out: waiting for Media to ack.\n");
 330         }
 331
 332         /* Check for Blitter Engine */
 333         if (FORCEWAKE_BLITTER & fw_engine) {
 334                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 335                                                 FORCEWAKE_ACK_BLITTER_GEN9) &
 336                                                 FORCEWAKE_KERNEL) == 0,
 337                                         FORCEWAKE_ACK_TIMEOUT_MS))
 338                         DRM_ERROR("Timed out: Blitter forcewake old ack to clear.\n");
 339
 340                 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
 341                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 342
 343                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 344                                                 FORCEWAKE_ACK_BLITTER_GEN9) &
 345                                                 FORCEWAKE_KERNEL),
 346                                         FORCEWAKE_ACK_TIMEOUT_MS))
 347                         DRM_ERROR("Timed out: waiting for Blitter to ack.\n");
 348         }
 349 }
 350
 351 static void
 352 __gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 353 {
 354         /* Check for Render Engine */
 355         if (FORCEWAKE_RENDER & fw_engine)
 356                 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
 357                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 358
 359         /* Check for Media Engine */
 360         if (FORCEWAKE_MEDIA & fw_engine)
 361                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
 362                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 363
 364         /* Check for Blitter Engine */
 365         if (FORCEWAKE_BLITTER & fw_engine)
 366                 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
 367                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 368 }
 369
 370 static void
 371 gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 372 {
 373         if (FORCEWAKE_RENDER & fw_engine) {
 374                 if (dev_priv->uncore.fw_rendercount++ == 0)
 375                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 376                                                         FORCEWAKE_RENDER);
 377         }
 378
 379         if (FORCEWAKE_MEDIA & fw_engine) {
 380                 if (dev_priv->uncore.fw_mediacount++ == 0)
 381                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 382                                                         FORCEWAKE_MEDIA);
 383         }
 384
 385         if (FORCEWAKE_BLITTER & fw_engine) {
 386                 if (dev_priv->uncore.fw_blittercount++ == 0)
 387                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 388                                                         FORCEWAKE_BLITTER);
 389         }
 390 }
 391
 392 static void
 393 gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 394 {
 395         if (FORCEWAKE_RENDER & fw_engine) {
 396                 WARN_ON(dev_priv->uncore.fw_rendercount == 0);
 397                 if (--dev_priv->uncore.fw_rendercount == 0)
 398                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 399                                                         FORCEWAKE_RENDER);
 400         }
 401
 402         if (FORCEWAKE_MEDIA & fw_engine) {
 403                 WARN_ON(dev_priv->uncore.fw_mediacount == 0);
 404                 if (--dev_priv->uncore.fw_mediacount == 0)
 405                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 406                                                         FORCEWAKE_MEDIA);
 407         }
 408
 409         if (FORCEWAKE_BLITTER & fw_engine) {
 410                 WARN_ON(dev_priv->uncore.fw_blittercount == 0);
 411                 if (--dev_priv->uncore.fw_blittercount == 0)
 412                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 413                                                         FORCEWAKE_BLITTER);
 414         }
 415 }
 416
 417 static void gen6_force_wake_timer(unsigned long arg)
 418 {
 419         struct drm_i915_private *dev_priv = (void *)arg;
 420         unsigned long irqflags;
 421
 422         assert_device_not_suspended(dev_priv);
 423
 424         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 425         WARN_ON(!dev_priv->uncore.forcewake_count);
 426
 427         if (--dev_priv->uncore.forcewake_count == 0)
 428                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
 429         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 430 }
 431
 432 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 433 {
 434         struct drm_i915_private *dev_priv = dev->dev_private;
 435         unsigned long irqflags;
 436
 437         if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
 438                 gen6_force_wake_timer((unsigned long)dev_priv);
 439
 440         /* Hold uncore.lock across reset to prevent any register access
 441          * with forcewake not set correctly
 442          */
 443         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 444
 445         if (IS_VALLEYVIEW(dev))
 446                 vlv_force_wake_reset(dev_priv);
 447         else if (IS_GEN6(dev) || IS_GEN7(dev))
 448                 __gen6_gt_force_wake_reset(dev_priv);
 449
 450         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
 451                 __gen7_gt_force_wake_mt_reset(dev_priv);
 452
 453         if (IS_GEN9(dev))
 454                 __gen9_gt_force_wake_mt_reset(dev_priv);
 455
 456         if (restore) { /* If reset with a user forcewake, try to restore */
 457                 unsigned fw = 0;
 458
 459                 if (IS_VALLEYVIEW(dev)) {
 460                         if (dev_priv->uncore.fw_rendercount)
 461                                 fw |= FORCEWAKE_RENDER;
 462
 463                         if (dev_priv->uncore.fw_mediacount)
 464                                 fw |= FORCEWAKE_MEDIA;
 465                 } else if (IS_GEN9(dev)) {
 466                         if (dev_priv->uncore.fw_rendercount)
 467                                 fw |= FORCEWAKE_RENDER;
 468
 469                         if (dev_priv->uncore.fw_mediacount)
 470                                 fw |= FORCEWAKE_MEDIA;
 471
 472                         if (dev_priv->uncore.fw_blittercount)
 473                                 fw |= FORCEWAKE_BLITTER;
 474                 } else {
 475                         if (dev_priv->uncore.forcewake_count)
 476                                 fw = FORCEWAKE_ALL;
 477                 }
 478
 479                 if (fw)
 480                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 481
 482                 if (IS_GEN6(dev) || IS_GEN7(dev))
 483                         dev_priv->uncore.fifo_count =
 484                                 __raw_i915_read32(dev_priv, GTFIFOCTL) &
 485                                 GT_FIFO_FREE_ENTRIES_MASK;
 486         }
 487
 488         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 489 }
 490
 491 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 492                                           bool restore_forcewake)
 493 {
 494         struct drm_i915_private *dev_priv = dev->dev_private;
 495
 496         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 497                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 498
 499         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
 500             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
 501                 /* The docs do not explain exactly how the calculation can be
 502                  * made. It is somewhat guessable, but for now, it's always
 503                  * 128MB.
 504                  * NB: We can't write IDICR yet because we do not have gt funcs
 505                  * set up */
 506                 dev_priv->ellc_size = 128;
 507                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 508         }
 509
 510         /* clear out old GT FIFO errors */
 511         if (IS_GEN6(dev) || IS_GEN7(dev))
 512                 __raw_i915_write32(dev_priv, GTFIFODBG,
 513                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 514
 515         intel_uncore_forcewake_reset(dev, restore_forcewake);
 516 }
 517
 518 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 519 {
 520         __intel_uncore_early_sanitize(dev, restore_forcewake);
 521         i915_check_and_clear_faults(dev);
 522 }
 523
 524 void intel_uncore_sanitize(struct drm_device *dev)
 525 {
 526         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 527         intel_disable_gt_powersave(dev);
 528 }
 529
 530 /*
 531  * Generally this is called implicitly by the register read function. However,
 532  * if some sequence requires the GT to not power down then this function should
 533  * be called at the beginning of the sequence followed by a call to
 534  * gen6_gt_force_wake_put() at the end of the sequence.
 535  */
 536 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 537 {
 538         unsigned long irqflags;
 539
 540         if (!dev_priv->uncore.funcs.force_wake_get)
 541                 return;
 542
 543         WARN_ON(dev_priv->pm.suspended);
 544
 545         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 546
 547         if (IS_GEN9(dev_priv->dev)) {
 548                 gen9_force_wake_get(dev_priv, fw_engine);
 549         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
 550                 vlv_force_wake_get(dev_priv, fw_engine);
 551         } else {
 552                 if (dev_priv->uncore.forcewake_count++ == 0)
 553                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 554                                                               FORCEWAKE_ALL);
 555         }
 556
 557         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 558 }
 559
 560 /*
 561  * see gen6_gt_force_wake_get()
 562  */
 563 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 564 {
 565         unsigned long irqflags;
 566
 567         if (!dev_priv->uncore.funcs.force_wake_put)
 568                 return;
 569
 570         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 571
 572         if (IS_GEN9(dev_priv->dev)) {
 573                 gen9_force_wake_put(dev_priv, fw_engine);
 574         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
 575                 vlv_force_wake_put(dev_priv, fw_engine);
 576         } else {
 577                 WARN_ON(!dev_priv->uncore.forcewake_count);
 578                 if (--dev_priv->uncore.forcewake_count == 0) {
 579                         dev_priv->uncore.forcewake_count++;
 580                         mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
 581                                          jiffies + 1);
 582                 }
 583         }
 584
 585         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 586 }
 587
 588 void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
 589 {
 590         if (!dev_priv->uncore.funcs.force_wake_get)
 591                 return;
 592
 593         WARN_ON(dev_priv->uncore.forcewake_count > 0);
 594 }
 595
 596 /* We give fast paths for the really cool registers */
 597 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 598          ((reg) < 0x40000 && (reg) != FORCEWAKE)
 599
 600 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 601
 602 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 603         (REG_RANGE((reg), 0x2000, 0x4000) || \
 604          REG_RANGE((reg), 0x5000, 0x8000) || \
 605          REG_RANGE((reg), 0xB000, 0x12000) || \
 606          REG_RANGE((reg), 0x2E000, 0x30000))
 607
 608 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 609         (REG_RANGE((reg), 0x12000, 0x14000) || \
 610          REG_RANGE((reg), 0x22000, 0x24000) || \
 611          REG_RANGE((reg), 0x30000, 0x40000))
 612
 613 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 614         (REG_RANGE((reg), 0x2000, 0x4000) || \
 615          REG_RANGE((reg), 0x5200, 0x8000) || \
 616          REG_RANGE((reg), 0x8300, 0x8500) || \
 617          REG_RANGE((reg), 0xB000, 0xB480) || \
 618          REG_RANGE((reg), 0xE000, 0xE800))
 619
 620 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 621         (REG_RANGE((reg), 0x8800, 0x8900) || \
 622          REG_RANGE((reg), 0xD000, 0xD800) || \
 623          REG_RANGE((reg), 0x12000, 0x14000) || \
 624          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 625          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 626          REG_RANGE((reg), 0x30000, 0x38000))
 627
 628 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 629         (REG_RANGE((reg), 0x4000, 0x5000) || \
 630          REG_RANGE((reg), 0x8000, 0x8300) || \
 631          REG_RANGE((reg), 0x8500, 0x8600) || \
 632          REG_RANGE((reg), 0x9000, 0xB000) || \
 633          REG_RANGE((reg), 0xF000, 0x10000))
 634
 635 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 636         REG_RANGE((reg), 0xB00,  0x2000)
 637
 638 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 639         (REG_RANGE((reg), 0x2000, 0x2700) || \
 640          REG_RANGE((reg), 0x3000, 0x4000) || \
 641          REG_RANGE((reg), 0x5200, 0x8000) || \
 642          REG_RANGE((reg), 0x8140, 0x8160) || \
 643          REG_RANGE((reg), 0x8300, 0x8500) || \
 644          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 645          REG_RANGE((reg), 0xB000, 0xB480) || \
 646          REG_RANGE((reg), 0xE000, 0xE900) || \
 647          REG_RANGE((reg), 0x24400, 0x24800))
 648
 649 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 650         (REG_RANGE((reg), 0x8130, 0x8140) || \
 651          REG_RANGE((reg), 0x8800, 0x8A00) || \
 652          REG_RANGE((reg), 0xD000, 0xD800) || \
 653          REG_RANGE((reg), 0x12000, 0x14000) || \
 654          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 655          REG_RANGE((reg), 0x30000, 0x40000))
 656
 657 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 658         REG_RANGE((reg), 0x9400, 0x9800)
 659
 660 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 661         ((reg) < 0x40000 &&\
 662          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 663          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 664          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 665          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 666
 667 static void
 668 ilk_dummy_write(struct drm_i915_private *dev_priv)
 669 {
 670         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 671          * the chip from rc6 before touching it for real. MI_MODE is masked,
 672          * hence harmless to write 0 into. */
 673         __raw_i915_write32(dev_priv, MI_MODE, 0);
 674 }
 675
 676 static void
 677 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
 678                         bool before)
 679 {
 680         const char *op = read ? "reading" : "writing to";
 681         const char *when = before ? "before" : "after";
 682
 683         if (!i915.mmio_debug)
 684                 return;
 685
 686         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 687                 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 688                      when, op, reg);
 689                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 690         }
 691 }
 692
 693 static void
 694 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 695 {
 696         if (i915.mmio_debug)
 697                 return;
 698
 699         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 700                 DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
 701                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 702         }
 703 }
 704
 705 #define REG_READ_HEADER(x) \
 706         unsigned long irqflags; \
 707         u##x val = 0; \
 708         assert_device_not_suspended(dev_priv); \
 709         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 710
 711 #define REG_READ_FOOTER \
 712         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 713         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 714         return val
 715
 716 #define __gen4_read(x) \
 717 static u##x \
 718 gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 719         REG_READ_HEADER(x); \
 720         val = __raw_i915_read##x(dev_priv, reg); \
 721         REG_READ_FOOTER; \
 722 }
 723
 724 #define __gen5_read(x) \
 725 static u##x \
 726 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 727         REG_READ_HEADER(x); \
 728         ilk_dummy_write(dev_priv); \
 729         val = __raw_i915_read##x(dev_priv, reg); \
 730         REG_READ_FOOTER; \
 731 }
 732
 733 #define __gen6_read(x) \
 734 static u##x \
 735 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 736         REG_READ_HEADER(x); \
 737         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 738         if (dev_priv->uncore.forcewake_count == 0 && \
 739             NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 740                 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
 741                                                       FORCEWAKE_ALL); \
 742                 dev_priv->uncore.forcewake_count++; \
 743                 mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \
 744                                  jiffies + 1); \
 745         } \
 746         val = __raw_i915_read##x(dev_priv, reg); \
 747         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 748         REG_READ_FOOTER; \
 749 }
 750
 751 #define __vlv_read(x) \
 752 static u##x \
 753 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 754         unsigned fwengine = 0; \
 755         REG_READ_HEADER(x); \
 756         if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
 757                 if (dev_priv->uncore.fw_rendercount == 0) \
 758                         fwengine = FORCEWAKE_RENDER; \
 759         } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
 760                 if (dev_priv->uncore.fw_mediacount == 0) \
 761                         fwengine = FORCEWAKE_MEDIA; \
 762         }  \
 763         if (fwengine) \
 764                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 765         val = __raw_i915_read##x(dev_priv, reg); \
 766         if (fwengine) \
 767                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 768         REG_READ_FOOTER; \
 769 }
 770
 771 #define __chv_read(x) \
 772 static u##x \
 773 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 774         unsigned fwengine = 0; \
 775         REG_READ_HEADER(x); \
 776         if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
 777                 if (dev_priv->uncore.fw_rendercount == 0) \
 778                         fwengine = FORCEWAKE_RENDER; \
 779         } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
 780                 if (dev_priv->uncore.fw_mediacount == 0) \
 781                         fwengine = FORCEWAKE_MEDIA; \
 782         } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
 783                 if (dev_priv->uncore.fw_rendercount == 0) \
 784                         fwengine |= FORCEWAKE_RENDER; \
 785                 if (dev_priv->uncore.fw_mediacount == 0) \
 786                         fwengine |= FORCEWAKE_MEDIA; \
 787         } \
 788         if (fwengine) \
 789                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 790         val = __raw_i915_read##x(dev_priv, reg); \
 791         if (fwengine) \
 792                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 793         REG_READ_FOOTER; \
 794 }
 795
 796 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)     \
 797          ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 798
 799 #define __gen9_read(x) \
 800 static u##x \
 801 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 802         REG_READ_HEADER(x); \
 803         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 804                 val = __raw_i915_read##x(dev_priv, reg); \
 805         } else { \
 806                 unsigned fwengine = 0; \
 807                 if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
 808                         if (dev_priv->uncore.fw_rendercount == 0) \
 809                                 fwengine = FORCEWAKE_RENDER; \
 810                 } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
 811                         if (dev_priv->uncore.fw_mediacount == 0) \
 812                                 fwengine = FORCEWAKE_MEDIA; \
 813                 } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
 814                         if (dev_priv->uncore.fw_rendercount == 0) \
 815                                 fwengine |= FORCEWAKE_RENDER; \
 816                         if (dev_priv->uncore.fw_mediacount == 0) \
 817                                 fwengine |= FORCEWAKE_MEDIA; \
 818                 } else { \
 819                         if (dev_priv->uncore.fw_blittercount == 0) \
 820                                 fwengine = FORCEWAKE_BLITTER; \
 821                 } \
 822                 if (fwengine) \
 823                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 824                 val = __raw_i915_read##x(dev_priv, reg); \
 825                 if (fwengine) \
 826                         dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 827         } \
 828         REG_READ_FOOTER; \
 829 }
 830
 831 __gen9_read(8)
 832 __gen9_read(16)
 833 __gen9_read(32)
 834 __gen9_read(64)
 835 __chv_read(8)
 836 __chv_read(16)
 837 __chv_read(32)
 838 __chv_read(64)
 839 __vlv_read(8)
 840 __vlv_read(16)
 841 __vlv_read(32)
 842 __vlv_read(64)
 843 __gen6_read(8)
 844 __gen6_read(16)
 845 __gen6_read(32)
 846 __gen6_read(64)
 847 __gen5_read(8)
 848 __gen5_read(16)
 849 __gen5_read(32)
 850 __gen5_read(64)
 851 __gen4_read(8)
 852 __gen4_read(16)
 853 __gen4_read(32)
 854 __gen4_read(64)
 855
 856 #undef __gen9_read
 857 #undef __chv_read
 858 #undef __vlv_read
 859 #undef __gen6_read
 860 #undef __gen5_read
 861 #undef __gen4_read
 862 #undef REG_READ_FOOTER
 863 #undef REG_READ_HEADER
 864
 865 #define REG_WRITE_HEADER \
 866         unsigned long irqflags; \
 867         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 868         assert_device_not_suspended(dev_priv); \
 869         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 870
 871 #define REG_WRITE_FOOTER \
 872         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 873
 874 #define __gen4_write(x) \
 875 static void \
 876 gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 877         REG_WRITE_HEADER; \
 878         __raw_i915_write##x(dev_priv, reg, val); \
 879         REG_WRITE_FOOTER; \
 880 }
 881
 882 #define __gen5_write(x) \
 883 static void \
 884 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 885         REG_WRITE_HEADER; \
 886         ilk_dummy_write(dev_priv); \
 887         __raw_i915_write##x(dev_priv, reg, val); \
 888         REG_WRITE_FOOTER; \
 889 }
 890
 891 #define __gen6_write(x) \
 892 static void \
 893 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 894         u32 __fifo_ret = 0; \
 895         REG_WRITE_HEADER; \
 896         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 897                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 898         } \
 899         __raw_i915_write##x(dev_priv, reg, val); \
 900         if (unlikely(__fifo_ret)) { \
 901                 gen6_gt_check_fifodbg(dev_priv); \
 902         } \
 903         REG_WRITE_FOOTER; \
 904 }
 905
 906 #define __hsw_write(x) \
 907 static void \
 908 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 909         u32 __fifo_ret = 0; \
 910         REG_WRITE_HEADER; \
 911         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 912                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 913         } \
 914         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 915         __raw_i915_write##x(dev_priv, reg, val); \
 916         if (unlikely(__fifo_ret)) { \
 917                 gen6_gt_check_fifodbg(dev_priv); \
 918         } \
 919         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 920         hsw_unclaimed_reg_detect(dev_priv); \
 921         REG_WRITE_FOOTER; \
 922 }
 923
 924 static const u32 gen8_shadowed_regs[] = {
 925         FORCEWAKE_MT,
 926         GEN6_RPNSWREQ,
 927         GEN6_RC_VIDEO_FREQ,
 928         RING_TAIL(RENDER_RING_BASE),
 929         RING_TAIL(GEN6_BSD_RING_BASE),
 930         RING_TAIL(VEBOX_RING_BASE),
 931         RING_TAIL(BLT_RING_BASE),
 932         /* TODO: Other registers are not yet used */
 933 };
 934
 935 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 936 {
 937         int i;
 938         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 939                 if (reg == gen8_shadowed_regs[i])
 940                         return true;
 941
 942         return false;
 943 }
 944
 945 #define __gen8_write(x) \
 946 static void \
 947 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 948         REG_WRITE_HEADER; \
 949         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 950         if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
 951                 if (dev_priv->uncore.forcewake_count == 0) \
 952                         dev_priv->uncore.funcs.force_wake_get(dev_priv, \
 953                                                               FORCEWAKE_ALL); \
 954                 __raw_i915_write##x(dev_priv, reg, val); \
 955                 if (dev_priv->uncore.forcewake_count == 0) \
 956                         dev_priv->uncore.funcs.force_wake_put(dev_priv, \
 957                                                               FORCEWAKE_ALL); \
 958         } else { \
 959                 __raw_i915_write##x(dev_priv, reg, val); \
 960         } \
 961         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 962         hsw_unclaimed_reg_detect(dev_priv); \
 963         REG_WRITE_FOOTER; \
 964 }
 965
 966 #define __chv_write(x) \
 967 static void \
 968 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 969         unsigned fwengine = 0; \
 970         bool shadowed = is_gen8_shadowed(dev_priv, reg); \
 971         REG_WRITE_HEADER; \
 972         if (!shadowed) { \
 973                 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
 974                         if (dev_priv->uncore.fw_rendercount == 0) \
 975                                 fwengine = FORCEWAKE_RENDER; \
 976                 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
 977                         if (dev_priv->uncore.fw_mediacount == 0) \
 978                                 fwengine = FORCEWAKE_MEDIA; \
 979                 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
 980                         if (dev_priv->uncore.fw_rendercount == 0) \
 981                                 fwengine |= FORCEWAKE_RENDER; \
 982                         if (dev_priv->uncore.fw_mediacount == 0) \
 983                                 fwengine |= FORCEWAKE_MEDIA; \
 984                 } \
 985         } \
 986         if (fwengine) \
 987                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 988         __raw_i915_write##x(dev_priv, reg, val); \
 989         if (fwengine) \
 990                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 991         REG_WRITE_FOOTER; \
 992 }
 993
 994 static const u32 gen9_shadowed_regs[] = {
 995         RING_TAIL(RENDER_RING_BASE),
 996         RING_TAIL(GEN6_BSD_RING_BASE),
 997         RING_TAIL(VEBOX_RING_BASE),
 998         RING_TAIL(BLT_RING_BASE),
 999         FORCEWAKE_BLITTER_GEN9,
1000         FORCEWAKE_RENDER_GEN9,
1001         FORCEWAKE_MEDIA_GEN9,
1002         GEN6_RPNSWREQ,
1003         GEN6_RC_VIDEO_FREQ,
1004         /* TODO: Other registers are not yet used */
1005 };
1006
1007 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
1008 {
1009         int i;
1010         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
1011                 if (reg == gen9_shadowed_regs[i])
1012                         return true;
1013
1014         return false;
1015 }
1016
1017 #define __gen9_write(x) \
1018 static void \
1019 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
1020                 bool trace) { \
1021         REG_WRITE_HEADER; \
1022         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
1023                         is_gen9_shadowed(dev_priv, reg)) { \
1024                 __raw_i915_write##x(dev_priv, reg, val); \
1025         } else { \
1026                 unsigned fwengine = 0; \
1027                 if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
1028                         if (dev_priv->uncore.fw_rendercount == 0) \
1029                                 fwengine = FORCEWAKE_RENDER; \
1030                 } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
1031                         if (dev_priv->uncore.fw_mediacount == 0) \
1032                                 fwengine = FORCEWAKE_MEDIA; \
1033                 } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
1034                         if (dev_priv->uncore.fw_rendercount == 0) \
1035                                 fwengine |= FORCEWAKE_RENDER; \
1036                         if (dev_priv->uncore.fw_mediacount == 0) \
1037                                 fwengine |= FORCEWAKE_MEDIA; \
1038                 } else { \
1039                         if (dev_priv->uncore.fw_blittercount == 0) \
1040                                 fwengine = FORCEWAKE_BLITTER; \
1041                 } \
1042                 if (fwengine) \
1043                         dev_priv->uncore.funcs.force_wake_get(dev_priv, \
1044                                         fwengine); \
1045                 __raw_i915_write##x(dev_priv, reg, val); \
1046                 if (fwengine) \
1047                         dev_priv->uncore.funcs.force_wake_put(dev_priv, \
1048                                         fwengine); \
1049         } \
1050         REG_WRITE_FOOTER; \
1051 }
1052
1053 __gen9_write(8)
1054 __gen9_write(16)
1055 __gen9_write(32)
1056 __gen9_write(64)
1057 __chv_write(8)
1058 __chv_write(16)
1059 __chv_write(32)
1060 __chv_write(64)
1061 __gen8_write(8)
1062 __gen8_write(16)
1063 __gen8_write(32)
1064 __gen8_write(64)
1065 __hsw_write(8)
1066 __hsw_write(16)
1067 __hsw_write(32)
1068 __hsw_write(64)
1069 __gen6_write(8)
1070 __gen6_write(16)
1071 __gen6_write(32)
1072 __gen6_write(64)
1073 __gen5_write(8)
1074 __gen5_write(16)
1075 __gen5_write(32)
1076 __gen5_write(64)
1077 __gen4_write(8)
1078 __gen4_write(16)
1079 __gen4_write(32)
1080 __gen4_write(64)
1081
1082 #undef __gen9_write
1083 #undef __chv_write
1084 #undef __gen8_write
1085 #undef __hsw_write
1086 #undef __gen6_write
1087 #undef __gen5_write
1088 #undef __gen4_write
1089 #undef REG_WRITE_FOOTER
1090 #undef REG_WRITE_HEADER
1091
1092 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1093 do { \
1094         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1095         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1096         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1097         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1098 } while (0)
1099
1100 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1101 do { \
1102         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1103         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1104         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1105         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1106 } while (0)
1107
1108 void intel_uncore_init(struct drm_device *dev)
1109 {
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111
1112         setup_timer(&dev_priv->uncore.force_wake_timer,
1113                     gen6_force_wake_timer, (unsigned long)dev_priv);
1114
1115         __intel_uncore_early_sanitize(dev, false);
1116
1117         if (IS_GEN9(dev)) {
1118                 dev_priv->uncore.funcs.force_wake_get = __gen9_force_wake_get;
1119                 dev_priv->uncore.funcs.force_wake_put = __gen9_force_wake_put;
1120         } else if (IS_VALLEYVIEW(dev)) {
1121                 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
1122                 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
1123         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1124                 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
1125                 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
1126         } else if (IS_IVYBRIDGE(dev)) {
1127                 u32 ecobus;
1128
1129                 /* IVB configs may use multi-threaded forcewake */
1130
1131                 /* A small trick here - if the bios hasn't configured
1132                  * MT forcewake, and if the device is in RC6, then
1133                  * force_wake_mt_get will not wake the device and the
1134                  * ECOBUS read will return zero. Which will be
1135                  * (correctly) interpreted by the test below as MT
1136                  * forcewake being disabled.
1137                  */
1138                 mutex_lock(&dev->struct_mutex);
1139                 __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
1140                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1141                 __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
1142                 mutex_unlock(&dev->struct_mutex);
1143
1144                 if (ecobus & FORCEWAKE_MT_ENABLE) {
1145                         dev_priv->uncore.funcs.force_wake_get =
1146                                 __gen7_gt_force_wake_mt_get;
1147                         dev_priv->uncore.funcs.force_wake_put =
1148                                 __gen7_gt_force_wake_mt_put;
1149                 } else {
1150                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1151                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1152                         dev_priv->uncore.funcs.force_wake_get =
1153                                 __gen6_gt_force_wake_get;
1154                         dev_priv->uncore.funcs.force_wake_put =
1155                                 __gen6_gt_force_wake_put;
1156                 }
1157         } else if (IS_GEN6(dev)) {
1158                 dev_priv->uncore.funcs.force_wake_get =
1159                         __gen6_gt_force_wake_get;
1160                 dev_priv->uncore.funcs.force_wake_put =
1161                         __gen6_gt_force_wake_put;
1162         }
1163
1164         switch (INTEL_INFO(dev)->gen) {
1165         default:
1166                 MISSING_CASE(INTEL_INFO(dev)->gen);
1167                 return;
1168         case 9:
1169                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1170                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1171                 break;
1172         case 8:
1173                 if (IS_CHERRYVIEW(dev)) {
1174                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1175                         ASSIGN_READ_MMIO_VFUNCS(chv);
1176
1177                 } else {
1178                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1179                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1180                 }
1181                 break;
1182         case 7:
1183         case 6:
1184                 if (IS_HASWELL(dev)) {
1185                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1186                 } else {
1187                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1188                 }
1189
1190                 if (IS_VALLEYVIEW(dev)) {
1191                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1192                 } else {
1193                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1194                 }
1195                 break;
1196         case 5:
1197                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1198                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1199                 break;
1200         case 4:
1201         case 3:
1202         case 2:
1203                 ASSIGN_WRITE_MMIO_VFUNCS(gen4);
1204                 ASSIGN_READ_MMIO_VFUNCS(gen4);
1205                 break;
1206         }
1207
1208         i915_check_and_clear_faults(dev);
1209 }
1210 #undef ASSIGN_WRITE_MMIO_VFUNCS
1211 #undef ASSIGN_READ_MMIO_VFUNCS
1212
1213 void intel_uncore_fini(struct drm_device *dev)
1214 {
1215         /* Paranoia: make sure we have disabled everything before we exit. */
1216         intel_uncore_sanitize(dev);
1217         intel_uncore_forcewake_reset(dev, false);
1218 }
1219
1220 #define GEN_RANGE(l, h) GENMASK(h, l)
1221
1222 static const struct register_whitelist {
1223         uint64_t offset;
1224         uint32_t size;
1225         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1226         uint32_t gen_bitmask;
1227 } whitelist[] = {
1228         { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1229 };
1230
1231 int i915_reg_read_ioctl(struct drm_device *dev,
1232                         void *data, struct drm_file *file)
1233 {
1234         struct drm_i915_private *dev_priv = dev->dev_private;
1235         struct drm_i915_reg_read *reg = data;
1236         struct register_whitelist const *entry = whitelist;
1237         int i, ret = 0;
1238
1239         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1240                 if (entry->offset == reg->offset &&
1241                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1242                         break;
1243         }
1244
1245         if (i == ARRAY_SIZE(whitelist))
1246                 return -EINVAL;
1247
1248         intel_runtime_pm_get(dev_priv);
1249
1250         switch (entry->size) {
1251         case 8:
1252                 reg->val = I915_READ64(reg->offset);
1253                 break;
1254         case 4:
1255                 reg->val = I915_READ(reg->offset);
1256                 break;
1257         case 2:
1258                 reg->val = I915_READ16(reg->offset);
1259                 break;
1260         case 1:
1261                 reg->val = I915_READ8(reg->offset);
1262                 break;
1263         default:
1264                 MISSING_CASE(entry->size);
1265                 ret = -EINVAL;
1266                 goto out;
1267         }
1268
1269 out:
1270         intel_runtime_pm_put(dev_priv);
1271         return ret;
1272 }
1273
1274 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1275                                void *data, struct drm_file *file)
1276 {
1277         struct drm_i915_private *dev_priv = dev->dev_private;
1278         struct drm_i915_reset_stats *args = data;
1279         struct i915_ctx_hang_stats *hs;
1280         struct intel_context *ctx;
1281         int ret;
1282
1283         if (args->flags || args->pad)
1284                 return -EINVAL;
1285
1286         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1287                 return -EPERM;
1288
1289         ret = mutex_lock_interruptible(&dev->struct_mutex);
1290         if (ret)
1291                 return ret;
1292
1293         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1294         if (IS_ERR(ctx)) {
1295                 mutex_unlock(&dev->struct_mutex);
1296                 return PTR_ERR(ctx);
1297         }
1298         hs = &ctx->hang_stats;
1299
1300         if (capable(CAP_SYS_ADMIN))
1301                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1302         else
1303                 args->reset_count = 0;
1304
1305         args->batch_active = hs->batch_active;
1306         args->batch_pending = hs->batch_pending;
1307
1308         mutex_unlock(&dev->struct_mutex);
1309
1310         return 0;
1311 }
1312
1313 static int i915_reset_complete(struct drm_device *dev)
1314 {
1315         u8 gdrst;
1316         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1317         return (gdrst & GRDOM_RESET_STATUS) == 0;
1318 }
1319
1320 static int i915_do_reset(struct drm_device *dev)
1321 {
1322         /* assert reset for at least 20 usec */
1323         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1324         udelay(20);
1325         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1326
1327         return wait_for(i915_reset_complete(dev), 500);
1328 }
1329
1330 static int g4x_reset_complete(struct drm_device *dev)
1331 {
1332         u8 gdrst;
1333         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1334         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1335 }
1336
1337 static int g33_do_reset(struct drm_device *dev)
1338 {
1339         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1340         return wait_for(g4x_reset_complete(dev), 500);
1341 }
1342
1343 static int g4x_do_reset(struct drm_device *dev)
1344 {
1345         struct drm_i915_private *dev_priv = dev->dev_private;
1346         int ret;
1347
1348         pci_write_config_byte(dev->pdev, I915_GDRST,
1349                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1350         ret =  wait_for(g4x_reset_complete(dev), 500);
1351         if (ret)
1352                 return ret;
1353
1354         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1355         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1356         POSTING_READ(VDECCLK_GATE_D);
1357
1358         pci_write_config_byte(dev->pdev, I915_GDRST,
1359                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1360         ret =  wait_for(g4x_reset_complete(dev), 500);
1361         if (ret)
1362                 return ret;
1363
1364         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1365         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1366         POSTING_READ(VDECCLK_GATE_D);
1367
1368         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1369
1370         return 0;
1371 }
1372
1373 static int ironlake_do_reset(struct drm_device *dev)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         int ret;
1377
1378         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1379                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1380         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1381                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1382         if (ret)
1383                 return ret;
1384
1385         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1386                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1387         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1388                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1389         if (ret)
1390                 return ret;
1391
1392         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1393
1394         return 0;
1395 }
1396
1397 static int gen6_do_reset(struct drm_device *dev)
1398 {
1399         struct drm_i915_private *dev_priv = dev->dev_private;
1400         int     ret;
1401
1402         /* Reset the chip */
1403
1404         /* GEN6_GDRST is not in the gt power well, no need to check
1405          * for fifo space for the write or forcewake the chip for
1406          * the read
1407          */
1408         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1409
1410         /* Spin waiting for the device to ack the reset request */
1411         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1412
1413         intel_uncore_forcewake_reset(dev, true);
1414
1415         return ret;
1416 }
1417
1418 int intel_gpu_reset(struct drm_device *dev)
1419 {
1420         if (INTEL_INFO(dev)->gen >= 6)
1421                 return gen6_do_reset(dev);
1422         else if (IS_GEN5(dev))
1423                 return ironlake_do_reset(dev);
1424         else if (IS_G4X(dev))
1425                 return g4x_do_reset(dev);
1426         else if (IS_G33(dev))
1427                 return g33_do_reset(dev);
1428         else if (INTEL_INFO(dev)->gen >= 3)
1429                 return i915_do_reset(dev);
1430         else
1431                 return -ENODEV;
1432 }
1433
1434 void intel_uncore_check_errors(struct drm_device *dev)
1435 {
1436         struct drm_i915_private *dev_priv = dev->dev_private;
1437
1438         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1439             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1440                 DRM_ERROR("Unclaimed register before interrupt\n");
1441                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1442         }
1443 }