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drm/i915: assert we're not runtime suspended when accessing registers
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_uncore.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "i915_drv.h"
25 #include "intel_drv.h"
26
27 #define FORCEWAKE_ACK_TIMEOUT_MS 2
28
29 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
31
32 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
34
35 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
37
38 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
40
41 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
42
43 static void
44 assert_device_not_suspended(struct drm_i915_private *dev_priv)
45 {
46 WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
47 "Device suspended\n");
48 }
49
50 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
51 {
52 u32 gt_thread_status_mask;
53
54 if (IS_HASWELL(dev_priv->dev))
55 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
56 else
57 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
58
59 /* w/a for a sporadic read returning 0 by waiting for the GT
60 * thread to wake up.
61 */
62 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
63 DRM_ERROR("GT thread status wait timed out\n");
64 }
65
66 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
67 {
68 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
69 /* something from same cacheline, but !FORCEWAKE */
70 __raw_posting_read(dev_priv, ECOBUS);
71 }
72
73 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
74 int fw_engine)
75 {
76 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
77 FORCEWAKE_ACK_TIMEOUT_MS))
78 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
79
80 __raw_i915_write32(dev_priv, FORCEWAKE, 1);
81 /* something from same cacheline, but !FORCEWAKE */
82 __raw_posting_read(dev_priv, ECOBUS);
83
84 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
85 FORCEWAKE_ACK_TIMEOUT_MS))
86 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
87
88 /* WaRsForcewakeWaitTC0:snb */
89 __gen6_gt_wait_for_thread_c0(dev_priv);
90 }
91
92 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
93 {
94 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
95 /* something from same cacheline, but !FORCEWAKE_MT */
96 __raw_posting_read(dev_priv, ECOBUS);
97 }
98
99 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
100 int fw_engine)
101 {
102 u32 forcewake_ack;
103
104 if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
105 forcewake_ack = FORCEWAKE_ACK_HSW;
106 else
107 forcewake_ack = FORCEWAKE_MT_ACK;
108
109 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
110 FORCEWAKE_ACK_TIMEOUT_MS))
111 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
112
113 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
114 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
115 /* something from same cacheline, but !FORCEWAKE_MT */
116 __raw_posting_read(dev_priv, ECOBUS);
117
118 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
119 FORCEWAKE_ACK_TIMEOUT_MS))
120 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
121
122 /* WaRsForcewakeWaitTC0:ivb,hsw */
123 if (INTEL_INFO(dev_priv->dev)->gen < 8)
124 __gen6_gt_wait_for_thread_c0(dev_priv);
125 }
126
127 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
128 {
129 u32 gtfifodbg;
130
131 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
132 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
133 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
134 }
135
136 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
137 int fw_engine)
138 {
139 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
140 /* something from same cacheline, but !FORCEWAKE */
141 __raw_posting_read(dev_priv, ECOBUS);
142 gen6_gt_check_fifodbg(dev_priv);
143 }
144
145 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
146 int fw_engine)
147 {
148 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
149 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
150 /* something from same cacheline, but !FORCEWAKE_MT */
151 __raw_posting_read(dev_priv, ECOBUS);
152 gen6_gt_check_fifodbg(dev_priv);
153 }
154
155 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
156 {
157 int ret = 0;
158
159 /* On VLV, FIFO will be shared by both SW and HW.
160 * So, we need to read the FREE_ENTRIES everytime */
161 if (IS_VALLEYVIEW(dev_priv->dev))
162 dev_priv->uncore.fifo_count =
163 __raw_i915_read32(dev_priv, GTFIFOCTL) &
164 GT_FIFO_FREE_ENTRIES_MASK;
165
166 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
167 int loop = 500;
168 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
169 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
170 udelay(10);
171 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
172 }
173 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
174 ++ret;
175 dev_priv->uncore.fifo_count = fifo;
176 }
177 dev_priv->uncore.fifo_count--;
178
179 return ret;
180 }
181
182 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
183 {
184 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
185 _MASKED_BIT_DISABLE(0xffff));
186 /* something from same cacheline, but !FORCEWAKE_VLV */
187 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
188 }
189
190 static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
191 int fw_engine)
192 {
193 /* Check for Render Engine */
194 if (FORCEWAKE_RENDER & fw_engine) {
195 if (wait_for_atomic((__raw_i915_read32(dev_priv,
196 FORCEWAKE_ACK_VLV) &
197 FORCEWAKE_KERNEL) == 0,
198 FORCEWAKE_ACK_TIMEOUT_MS))
199 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
200
201 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
202 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
203
204 if (wait_for_atomic((__raw_i915_read32(dev_priv,
205 FORCEWAKE_ACK_VLV) &
206 FORCEWAKE_KERNEL),
207 FORCEWAKE_ACK_TIMEOUT_MS))
208 DRM_ERROR("Timed out: waiting for Render to ack.\n");
209 }
210
211 /* Check for Media Engine */
212 if (FORCEWAKE_MEDIA & fw_engine) {
213 if (wait_for_atomic((__raw_i915_read32(dev_priv,
214 FORCEWAKE_ACK_MEDIA_VLV) &
215 FORCEWAKE_KERNEL) == 0,
216 FORCEWAKE_ACK_TIMEOUT_MS))
217 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
218
219 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
220 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
221
222 if (wait_for_atomic((__raw_i915_read32(dev_priv,
223 FORCEWAKE_ACK_MEDIA_VLV) &
224 FORCEWAKE_KERNEL),
225 FORCEWAKE_ACK_TIMEOUT_MS))
226 DRM_ERROR("Timed out: waiting for media to ack.\n");
227 }
228
229 /* WaRsForcewakeWaitTC0:vlv */
230 __gen6_gt_wait_for_thread_c0(dev_priv);
231
232 }
233
234 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
235 int fw_engine)
236 {
237
238 /* Check for Render Engine */
239 if (FORCEWAKE_RENDER & fw_engine)
240 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
241 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
242
243
244 /* Check for Media Engine */
245 if (FORCEWAKE_MEDIA & fw_engine)
246 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
247 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
248
249 /* The below doubles as a POSTING_READ */
250 gen6_gt_check_fifodbg(dev_priv);
251
252 }
253
254 void vlv_force_wake_get(struct drm_i915_private *dev_priv,
255 int fw_engine)
256 {
257 unsigned long irqflags;
258
259 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
260 if (FORCEWAKE_RENDER & fw_engine) {
261 if (dev_priv->uncore.fw_rendercount++ == 0)
262 dev_priv->uncore.funcs.force_wake_get(dev_priv,
263 FORCEWAKE_RENDER);
264 }
265 if (FORCEWAKE_MEDIA & fw_engine) {
266 if (dev_priv->uncore.fw_mediacount++ == 0)
267 dev_priv->uncore.funcs.force_wake_get(dev_priv,
268 FORCEWAKE_MEDIA);
269 }
270
271 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
272 }
273
274 void vlv_force_wake_put(struct drm_i915_private *dev_priv,
275 int fw_engine)
276 {
277 unsigned long irqflags;
278
279 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
280
281 if (FORCEWAKE_RENDER & fw_engine) {
282 WARN_ON(dev_priv->uncore.fw_rendercount == 0);
283 if (--dev_priv->uncore.fw_rendercount == 0)
284 dev_priv->uncore.funcs.force_wake_put(dev_priv,
285 FORCEWAKE_RENDER);
286 }
287
288 if (FORCEWAKE_MEDIA & fw_engine) {
289 WARN_ON(dev_priv->uncore.fw_mediacount == 0);
290 if (--dev_priv->uncore.fw_mediacount == 0)
291 dev_priv->uncore.funcs.force_wake_put(dev_priv,
292 FORCEWAKE_MEDIA);
293 }
294
295 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
296 }
297
298 static void gen6_force_wake_timer(unsigned long arg)
299 {
300 struct drm_i915_private *dev_priv = (void *)arg;
301 unsigned long irqflags;
302
303 assert_device_not_suspended(dev_priv);
304
305 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
306 if (--dev_priv->uncore.forcewake_count == 0)
307 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
308 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
309
310 intel_runtime_pm_put(dev_priv);
311 }
312
313 static void intel_uncore_forcewake_reset(struct drm_device *dev)
314 {
315 struct drm_i915_private *dev_priv = dev->dev_private;
316
317 if (IS_VALLEYVIEW(dev)) {
318 vlv_force_wake_reset(dev_priv);
319 } else if (INTEL_INFO(dev)->gen >= 6) {
320 __gen6_gt_force_wake_reset(dev_priv);
321 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
322 __gen6_gt_force_wake_mt_reset(dev_priv);
323 }
324 }
325
326 void intel_uncore_early_sanitize(struct drm_device *dev)
327 {
328 struct drm_i915_private *dev_priv = dev->dev_private;
329
330 if (HAS_FPGA_DBG_UNCLAIMED(dev))
331 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
332
333 if (IS_HASWELL(dev) &&
334 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
335 /* The docs do not explain exactly how the calculation can be
336 * made. It is somewhat guessable, but for now, it's always
337 * 128MB.
338 * NB: We can't write IDICR yet because we do not have gt funcs
339 * set up */
340 dev_priv->ellc_size = 128;
341 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
342 }
343
344 /* clear out old GT FIFO errors */
345 if (IS_GEN6(dev) || IS_GEN7(dev))
346 __raw_i915_write32(dev_priv, GTFIFODBG,
347 __raw_i915_read32(dev_priv, GTFIFODBG));
348
349 intel_uncore_forcewake_reset(dev);
350 }
351
352 void intel_uncore_sanitize(struct drm_device *dev)
353 {
354 struct drm_i915_private *dev_priv = dev->dev_private;
355 u32 reg_val;
356
357 /* BIOS often leaves RC6 enabled, but disable it for hw init */
358 intel_disable_gt_powersave(dev);
359
360 /* Turn off power gate, require especially for the BIOS less system */
361 if (IS_VALLEYVIEW(dev)) {
362
363 mutex_lock(&dev_priv->rps.hw_lock);
364 reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
365
366 if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT))
367 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
368
369 mutex_unlock(&dev_priv->rps.hw_lock);
370
371 }
372 }
373
374 /*
375 * Generally this is called implicitly by the register read function. However,
376 * if some sequence requires the GT to not power down then this function should
377 * be called at the beginning of the sequence followed by a call to
378 * gen6_gt_force_wake_put() at the end of the sequence.
379 */
380 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
381 {
382 unsigned long irqflags;
383
384 if (!dev_priv->uncore.funcs.force_wake_get)
385 return;
386
387 intel_runtime_pm_get(dev_priv);
388
389 /* Redirect to VLV specific routine */
390 if (IS_VALLEYVIEW(dev_priv->dev))
391 return vlv_force_wake_get(dev_priv, fw_engine);
392
393 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
394 if (dev_priv->uncore.forcewake_count++ == 0)
395 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
396 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
397 }
398
399 /*
400 * see gen6_gt_force_wake_get()
401 */
402 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
403 {
404 unsigned long irqflags;
405 bool delayed = false;
406
407 if (!dev_priv->uncore.funcs.force_wake_put)
408 return;
409
410 /* Redirect to VLV specific routine */
411 if (IS_VALLEYVIEW(dev_priv->dev)) {
412 vlv_force_wake_put(dev_priv, fw_engine);
413 goto out;
414 }
415
416
417 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
418 if (--dev_priv->uncore.forcewake_count == 0) {
419 dev_priv->uncore.forcewake_count++;
420 delayed = true;
421 mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
422 jiffies + 1);
423 }
424 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
425
426 out:
427 if (!delayed)
428 intel_runtime_pm_put(dev_priv);
429 }
430
431 void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
432 {
433 if (!dev_priv->uncore.funcs.force_wake_get)
434 return;
435
436 WARN_ON(dev_priv->uncore.forcewake_count > 0);
437 }
438
439 /* We give fast paths for the really cool registers */
440 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
441 ((reg) < 0x40000 && (reg) != FORCEWAKE)
442
443 static void
444 ilk_dummy_write(struct drm_i915_private *dev_priv)
445 {
446 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
447 * the chip from rc6 before touching it for real. MI_MODE is masked,
448 * hence harmless to write 0 into. */
449 __raw_i915_write32(dev_priv, MI_MODE, 0);
450 }
451
452 static void
453 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
454 {
455 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
456 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
457 reg);
458 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
459 }
460 }
461
462 static void
463 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
464 {
465 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
466 DRM_ERROR("Unclaimed write to %x\n", reg);
467 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
468 }
469 }
470
471 #define REG_READ_HEADER(x) \
472 unsigned long irqflags; \
473 u##x val = 0; \
474 assert_device_not_suspended(dev_priv); \
475 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
476
477 #define REG_READ_FOOTER \
478 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
479 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
480 return val
481
482 #define __gen4_read(x) \
483 static u##x \
484 gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
485 REG_READ_HEADER(x); \
486 val = __raw_i915_read##x(dev_priv, reg); \
487 REG_READ_FOOTER; \
488 }
489
490 #define __gen5_read(x) \
491 static u##x \
492 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
493 REG_READ_HEADER(x); \
494 ilk_dummy_write(dev_priv); \
495 val = __raw_i915_read##x(dev_priv, reg); \
496 REG_READ_FOOTER; \
497 }
498
499 #define __gen6_read(x) \
500 static u##x \
501 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
502 REG_READ_HEADER(x); \
503 if (dev_priv->uncore.forcewake_count == 0 && \
504 NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
505 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
506 FORCEWAKE_ALL); \
507 dev_priv->uncore.forcewake_count++; \
508 mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \
509 jiffies + 1); \
510 } \
511 val = __raw_i915_read##x(dev_priv, reg); \
512 REG_READ_FOOTER; \
513 }
514
515 #define __vlv_read(x) \
516 static u##x \
517 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
518 unsigned fwengine = 0; \
519 unsigned *fwcount; \
520 REG_READ_HEADER(x); \
521 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
522 fwengine = FORCEWAKE_RENDER; \
523 fwcount = &dev_priv->uncore.fw_rendercount; \
524 } \
525 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
526 fwengine = FORCEWAKE_MEDIA; \
527 fwcount = &dev_priv->uncore.fw_mediacount; \
528 } \
529 if (fwengine != 0) { \
530 if ((*fwcount)++ == 0) \
531 (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
532 fwengine); \
533 val = __raw_i915_read##x(dev_priv, reg); \
534 if (--(*fwcount) == 0) \
535 (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
536 fwengine); \
537 } else { \
538 val = __raw_i915_read##x(dev_priv, reg); \
539 } \
540 REG_READ_FOOTER; \
541 }
542
543
544 __vlv_read(8)
545 __vlv_read(16)
546 __vlv_read(32)
547 __vlv_read(64)
548 __gen6_read(8)
549 __gen6_read(16)
550 __gen6_read(32)
551 __gen6_read(64)
552 __gen5_read(8)
553 __gen5_read(16)
554 __gen5_read(32)
555 __gen5_read(64)
556 __gen4_read(8)
557 __gen4_read(16)
558 __gen4_read(32)
559 __gen4_read(64)
560
561 #undef __vlv_read
562 #undef __gen6_read
563 #undef __gen5_read
564 #undef __gen4_read
565 #undef REG_READ_FOOTER
566 #undef REG_READ_HEADER
567
568 #define REG_WRITE_HEADER \
569 unsigned long irqflags; \
570 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
571 assert_device_not_suspended(dev_priv); \
572 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
573
574 #define REG_WRITE_FOOTER \
575 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
576
577 #define __gen4_write(x) \
578 static void \
579 gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
580 REG_WRITE_HEADER; \
581 __raw_i915_write##x(dev_priv, reg, val); \
582 REG_WRITE_FOOTER; \
583 }
584
585 #define __gen5_write(x) \
586 static void \
587 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
588 REG_WRITE_HEADER; \
589 ilk_dummy_write(dev_priv); \
590 __raw_i915_write##x(dev_priv, reg, val); \
591 REG_WRITE_FOOTER; \
592 }
593
594 #define __gen6_write(x) \
595 static void \
596 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
597 u32 __fifo_ret = 0; \
598 REG_WRITE_HEADER; \
599 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
600 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
601 } \
602 __raw_i915_write##x(dev_priv, reg, val); \
603 if (unlikely(__fifo_ret)) { \
604 gen6_gt_check_fifodbg(dev_priv); \
605 } \
606 REG_WRITE_FOOTER; \
607 }
608
609 #define __hsw_write(x) \
610 static void \
611 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
612 u32 __fifo_ret = 0; \
613 REG_WRITE_HEADER; \
614 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
615 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
616 } \
617 hsw_unclaimed_reg_clear(dev_priv, reg); \
618 __raw_i915_write##x(dev_priv, reg, val); \
619 if (unlikely(__fifo_ret)) { \
620 gen6_gt_check_fifodbg(dev_priv); \
621 } \
622 hsw_unclaimed_reg_check(dev_priv, reg); \
623 REG_WRITE_FOOTER; \
624 }
625
626 static const u32 gen8_shadowed_regs[] = {
627 FORCEWAKE_MT,
628 GEN6_RPNSWREQ,
629 GEN6_RC_VIDEO_FREQ,
630 RING_TAIL(RENDER_RING_BASE),
631 RING_TAIL(GEN6_BSD_RING_BASE),
632 RING_TAIL(VEBOX_RING_BASE),
633 RING_TAIL(BLT_RING_BASE),
634 /* TODO: Other registers are not yet used */
635 };
636
637 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
638 {
639 int i;
640 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
641 if (reg == gen8_shadowed_regs[i])
642 return true;
643
644 return false;
645 }
646
647 #define __gen8_write(x) \
648 static void \
649 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
650 REG_WRITE_HEADER; \
651 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
652 if (dev_priv->uncore.forcewake_count == 0) \
653 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
654 FORCEWAKE_ALL); \
655 __raw_i915_write##x(dev_priv, reg, val); \
656 if (dev_priv->uncore.forcewake_count == 0) \
657 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
658 FORCEWAKE_ALL); \
659 } else { \
660 __raw_i915_write##x(dev_priv, reg, val); \
661 } \
662 REG_WRITE_FOOTER; \
663 }
664
665 __gen8_write(8)
666 __gen8_write(16)
667 __gen8_write(32)
668 __gen8_write(64)
669 __hsw_write(8)
670 __hsw_write(16)
671 __hsw_write(32)
672 __hsw_write(64)
673 __gen6_write(8)
674 __gen6_write(16)
675 __gen6_write(32)
676 __gen6_write(64)
677 __gen5_write(8)
678 __gen5_write(16)
679 __gen5_write(32)
680 __gen5_write(64)
681 __gen4_write(8)
682 __gen4_write(16)
683 __gen4_write(32)
684 __gen4_write(64)
685
686 #undef __gen8_write
687 #undef __hsw_write
688 #undef __gen6_write
689 #undef __gen5_write
690 #undef __gen4_write
691 #undef REG_WRITE_FOOTER
692 #undef REG_WRITE_HEADER
693
694 void intel_uncore_init(struct drm_device *dev)
695 {
696 struct drm_i915_private *dev_priv = dev->dev_private;
697
698 setup_timer(&dev_priv->uncore.force_wake_timer,
699 gen6_force_wake_timer, (unsigned long)dev_priv);
700
701 if (IS_VALLEYVIEW(dev)) {
702 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
703 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
704 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
705 dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get;
706 dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put;
707 } else if (IS_IVYBRIDGE(dev)) {
708 u32 ecobus;
709
710 /* IVB configs may use multi-threaded forcewake */
711
712 /* A small trick here - if the bios hasn't configured
713 * MT forcewake, and if the device is in RC6, then
714 * force_wake_mt_get will not wake the device and the
715 * ECOBUS read will return zero. Which will be
716 * (correctly) interpreted by the test below as MT
717 * forcewake being disabled.
718 */
719 mutex_lock(&dev->struct_mutex);
720 __gen6_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
721 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
722 __gen6_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
723 mutex_unlock(&dev->struct_mutex);
724
725 if (ecobus & FORCEWAKE_MT_ENABLE) {
726 dev_priv->uncore.funcs.force_wake_get =
727 __gen6_gt_force_wake_mt_get;
728 dev_priv->uncore.funcs.force_wake_put =
729 __gen6_gt_force_wake_mt_put;
730 } else {
731 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
732 DRM_INFO("when using vblank-synced partial screen updates.\n");
733 dev_priv->uncore.funcs.force_wake_get =
734 __gen6_gt_force_wake_get;
735 dev_priv->uncore.funcs.force_wake_put =
736 __gen6_gt_force_wake_put;
737 }
738 } else if (IS_GEN6(dev)) {
739 dev_priv->uncore.funcs.force_wake_get =
740 __gen6_gt_force_wake_get;
741 dev_priv->uncore.funcs.force_wake_put =
742 __gen6_gt_force_wake_put;
743 }
744
745 switch (INTEL_INFO(dev)->gen) {
746 default:
747 dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
748 dev_priv->uncore.funcs.mmio_writew = gen8_write16;
749 dev_priv->uncore.funcs.mmio_writel = gen8_write32;
750 dev_priv->uncore.funcs.mmio_writeq = gen8_write64;
751 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
752 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
753 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
754 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
755 break;
756 case 7:
757 case 6:
758 if (IS_HASWELL(dev)) {
759 dev_priv->uncore.funcs.mmio_writeb = hsw_write8;
760 dev_priv->uncore.funcs.mmio_writew = hsw_write16;
761 dev_priv->uncore.funcs.mmio_writel = hsw_write32;
762 dev_priv->uncore.funcs.mmio_writeq = hsw_write64;
763 } else {
764 dev_priv->uncore.funcs.mmio_writeb = gen6_write8;
765 dev_priv->uncore.funcs.mmio_writew = gen6_write16;
766 dev_priv->uncore.funcs.mmio_writel = gen6_write32;
767 dev_priv->uncore.funcs.mmio_writeq = gen6_write64;
768 }
769
770 if (IS_VALLEYVIEW(dev)) {
771 dev_priv->uncore.funcs.mmio_readb = vlv_read8;
772 dev_priv->uncore.funcs.mmio_readw = vlv_read16;
773 dev_priv->uncore.funcs.mmio_readl = vlv_read32;
774 dev_priv->uncore.funcs.mmio_readq = vlv_read64;
775 } else {
776 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
777 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
778 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
779 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
780 }
781 break;
782 case 5:
783 dev_priv->uncore.funcs.mmio_writeb = gen5_write8;
784 dev_priv->uncore.funcs.mmio_writew = gen5_write16;
785 dev_priv->uncore.funcs.mmio_writel = gen5_write32;
786 dev_priv->uncore.funcs.mmio_writeq = gen5_write64;
787 dev_priv->uncore.funcs.mmio_readb = gen5_read8;
788 dev_priv->uncore.funcs.mmio_readw = gen5_read16;
789 dev_priv->uncore.funcs.mmio_readl = gen5_read32;
790 dev_priv->uncore.funcs.mmio_readq = gen5_read64;
791 break;
792 case 4:
793 case 3:
794 case 2:
795 dev_priv->uncore.funcs.mmio_writeb = gen4_write8;
796 dev_priv->uncore.funcs.mmio_writew = gen4_write16;
797 dev_priv->uncore.funcs.mmio_writel = gen4_write32;
798 dev_priv->uncore.funcs.mmio_writeq = gen4_write64;
799 dev_priv->uncore.funcs.mmio_readb = gen4_read8;
800 dev_priv->uncore.funcs.mmio_readw = gen4_read16;
801 dev_priv->uncore.funcs.mmio_readl = gen4_read32;
802 dev_priv->uncore.funcs.mmio_readq = gen4_read64;
803 break;
804 }
805 }
806
807 void intel_uncore_fini(struct drm_device *dev)
808 {
809 struct drm_i915_private *dev_priv = dev->dev_private;
810
811 del_timer_sync(&dev_priv->uncore.force_wake_timer);
812
813 /* Paranoia: make sure we have disabled everything before we exit. */
814 intel_uncore_sanitize(dev);
815 intel_uncore_forcewake_reset(dev);
816 }
817
818 static const struct register_whitelist {
819 uint64_t offset;
820 uint32_t size;
821 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
822 } whitelist[] = {
823 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0x1F0 },
824 };
825
826 int i915_reg_read_ioctl(struct drm_device *dev,
827 void *data, struct drm_file *file)
828 {
829 struct drm_i915_private *dev_priv = dev->dev_private;
830 struct drm_i915_reg_read *reg = data;
831 struct register_whitelist const *entry = whitelist;
832 int i;
833
834 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
835 if (entry->offset == reg->offset &&
836 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
837 break;
838 }
839
840 if (i == ARRAY_SIZE(whitelist))
841 return -EINVAL;
842
843 switch (entry->size) {
844 case 8:
845 reg->val = I915_READ64(reg->offset);
846 break;
847 case 4:
848 reg->val = I915_READ(reg->offset);
849 break;
850 case 2:
851 reg->val = I915_READ16(reg->offset);
852 break;
853 case 1:
854 reg->val = I915_READ8(reg->offset);
855 break;
856 default:
857 WARN_ON(1);
858 return -EINVAL;
859 }
860
861 return 0;
862 }
863
864 int i915_get_reset_stats_ioctl(struct drm_device *dev,
865 void *data, struct drm_file *file)
866 {
867 struct drm_i915_private *dev_priv = dev->dev_private;
868 struct drm_i915_reset_stats *args = data;
869 struct i915_ctx_hang_stats *hs;
870 struct i915_hw_context *ctx;
871 int ret;
872
873 if (args->flags || args->pad)
874 return -EINVAL;
875
876 if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN))
877 return -EPERM;
878
879 ret = mutex_lock_interruptible(&dev->struct_mutex);
880 if (ret)
881 return ret;
882
883 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
884 if (IS_ERR(ctx)) {
885 mutex_unlock(&dev->struct_mutex);
886 return PTR_ERR(ctx);
887 }
888 hs = &ctx->hang_stats;
889
890 if (capable(CAP_SYS_ADMIN))
891 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
892 else
893 args->reset_count = 0;
894
895 args->batch_active = hs->batch_active;
896 args->batch_pending = hs->batch_pending;
897
898 mutex_unlock(&dev->struct_mutex);
899
900 return 0;
901 }
902
903 static int i965_reset_complete(struct drm_device *dev)
904 {
905 u8 gdrst;
906 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
907 return (gdrst & GRDOM_RESET_ENABLE) == 0;
908 }
909
910 static int i965_do_reset(struct drm_device *dev)
911 {
912 int ret;
913
914 /*
915 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
916 * well as the reset bit (GR/bit 0). Setting the GR bit
917 * triggers the reset; when done, the hardware will clear it.
918 */
919 pci_write_config_byte(dev->pdev, I965_GDRST,
920 GRDOM_RENDER | GRDOM_RESET_ENABLE);
921 ret = wait_for(i965_reset_complete(dev), 500);
922 if (ret)
923 return ret;
924
925 /* We can't reset render&media without also resetting display ... */
926 pci_write_config_byte(dev->pdev, I965_GDRST,
927 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
928
929 ret = wait_for(i965_reset_complete(dev), 500);
930 if (ret)
931 return ret;
932
933 pci_write_config_byte(dev->pdev, I965_GDRST, 0);
934
935 return 0;
936 }
937
938 static int ironlake_do_reset(struct drm_device *dev)
939 {
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 u32 gdrst;
942 int ret;
943
944 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
945 gdrst &= ~GRDOM_MASK;
946 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
947 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
948 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
949 if (ret)
950 return ret;
951
952 /* We can't reset render&media without also resetting display ... */
953 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
954 gdrst &= ~GRDOM_MASK;
955 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
956 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
957 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
958 }
959
960 static int gen6_do_reset(struct drm_device *dev)
961 {
962 struct drm_i915_private *dev_priv = dev->dev_private;
963 int ret;
964 unsigned long irqflags;
965
966 /* Hold uncore.lock across reset to prevent any register access
967 * with forcewake not set correctly
968 */
969 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
970
971 /* Reset the chip */
972
973 /* GEN6_GDRST is not in the gt power well, no need to check
974 * for fifo space for the write or forcewake the chip for
975 * the read
976 */
977 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
978
979 /* Spin waiting for the device to ack the reset request */
980 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
981
982 intel_uncore_forcewake_reset(dev);
983
984 /* If reset with a user forcewake, try to restore, otherwise turn it off */
985 if (dev_priv->uncore.forcewake_count)
986 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
987 else
988 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
989
990 /* Restore fifo count */
991 dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
992
993 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
994 return ret;
995 }
996
997 int intel_gpu_reset(struct drm_device *dev)
998 {
999 switch (INTEL_INFO(dev)->gen) {
1000 case 8:
1001 case 7:
1002 case 6: return gen6_do_reset(dev);
1003 case 5: return ironlake_do_reset(dev);
1004 case 4: return i965_do_reset(dev);
1005 default: return -ENODEV;
1006 }
1007 }
1008
1009 void intel_uncore_check_errors(struct drm_device *dev)
1010 {
1011 struct drm_i915_private *dev_priv = dev->dev_private;
1012
1013 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1014 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1015 DRM_ERROR("Unclaimed register before interrupt\n");
1016 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1017 }
1018 }
Linux kernel - Deliverables
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