drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26
  27 #include <linux/pm_runtime.h>
  28
  29 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  30
  31 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
  32 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
  33
  34 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
  35 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
  36
  37 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  38 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
  39
  40 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
  41 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
  42
  43 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  44
  45 static const char * const forcewake_domain_names[] = {
  46         "render",
  47         "blitter",
  48         "media",
  49 };
  50
  51 const char *
  52 intel_uncore_forcewake_domain_to_str(const int id)
  53 {
  54         BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) !=
  55                      FW_DOMAIN_ID_COUNT);
  56
  57         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  58                 return forcewake_domain_names[id];
  59
  60         WARN_ON(id);
  61
  62         return "unknown";
  63 }
  64
  65 static void
  66 assert_device_not_suspended(struct drm_i915_private *dev_priv)
  67 {
  68         WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
  69                   "Device suspended\n");
  70 }
  71
  72 static inline void
  73 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  74 {
  75         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  76 }
  77
  78 static inline void
  79 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  80 {
  81         mod_timer_pinned(&d->timer, jiffies + 1);
  82 }
  83
  84 static inline void
  85 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  86 {
  87         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  88                              FORCEWAKE_KERNEL) == 0,
  89                             FORCEWAKE_ACK_TIMEOUT_MS))
  90                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  91                           intel_uncore_forcewake_domain_to_str(d->id));
  92 }
  93
  94 static inline void
  95 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  96 {
  97         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  98 }
  99
 100 static inline void
 101 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
 102 {
 103         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
 104                              FORCEWAKE_KERNEL),
 105                             FORCEWAKE_ACK_TIMEOUT_MS))
 106                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 107                           intel_uncore_forcewake_domain_to_str(d->id));
 108 }
 109
 110 static inline void
 111 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 112 {
 113         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 114 }
 115
 116 static inline void
 117 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 118 {
 119         /* something from same cacheline, but not from the set register */
 120         if (d->reg_post)
 121                 __raw_posting_read(d->i915, d->reg_post);
 122 }
 123
 124 static void
 125 fw_domains_get(struct drm_i915_private *dev_priv, int fw_domains)
 126 {
 127         struct intel_uncore_forcewake_domain *d;
 128         int id;
 129
 130         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 131                 fw_domain_wait_ack_clear(d);
 132                 fw_domain_get(d);
 133                 fw_domain_posting_read(d);
 134                 fw_domain_wait_ack(d);
 135         }
 136 }
 137
 138 static void
 139 fw_domains_put(struct drm_i915_private *dev_priv, int fw_domains)
 140 {
 141         struct intel_uncore_forcewake_domain *d;
 142         int id;
 143
 144         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 145                 fw_domain_put(d);
 146                 fw_domain_posting_read(d);
 147         }
 148 }
 149
 150 static void
 151 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 152 {
 153         struct intel_uncore_forcewake_domain *d;
 154         int id;
 155
 156         /* No need to do for all, just do for first found */
 157         for_each_fw_domain(d, dev_priv, id) {
 158                 fw_domain_posting_read(d);
 159                 break;
 160         }
 161 }
 162
 163 static void
 164 fw_domains_reset(struct drm_i915_private *dev_priv, const unsigned fw_domains)
 165 {
 166         struct intel_uncore_forcewake_domain *d;
 167         int id;
 168
 169         for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
 170                 fw_domain_reset(d);
 171
 172         fw_domains_posting_read(dev_priv);
 173 }
 174
 175 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 176 {
 177         /* w/a for a sporadic read returning 0 by waiting for the GT
 178          * thread to wake up.
 179          */
 180         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 181                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 182                 DRM_ERROR("GT thread status wait timed out\n");
 183 }
 184
 185 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 186                                               int fw_domains)
 187 {
 188         fw_domains_get(dev_priv, fw_domains);
 189
 190         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 191         __gen6_gt_wait_for_thread_c0(dev_priv);
 192 }
 193
 194 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 195 {
 196         u32 gtfifodbg;
 197
 198         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 199         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 200                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 201 }
 202
 203 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 204                                      int fw_domains)
 205 {
 206         fw_domains_put(dev_priv, fw_domains);
 207         gen6_gt_check_fifodbg(dev_priv);
 208 }
 209
 210 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 211 {
 212         int ret = 0;
 213
 214         /* On VLV, FIFO will be shared by both SW and HW.
 215          * So, we need to read the FREE_ENTRIES everytime */
 216         if (IS_VALLEYVIEW(dev_priv->dev))
 217                 dev_priv->uncore.fifo_count =
 218                         __raw_i915_read32(dev_priv, GTFIFOCTL) &
 219                                                 GT_FIFO_FREE_ENTRIES_MASK;
 220
 221         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 222                 int loop = 500;
 223                 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 224                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 225                         udelay(10);
 226                         fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 227                 }
 228                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 229                         ++ret;
 230                 dev_priv->uncore.fifo_count = fifo;
 231         }
 232         dev_priv->uncore.fifo_count--;
 233
 234         return ret;
 235 }
 236
 237 static void gen6_force_wake_timer(unsigned long arg)
 238 {
 239         struct intel_uncore_forcewake_domain *domain = (void *)arg;
 240         unsigned long irqflags;
 241
 242         assert_device_not_suspended(domain->i915);
 243
 244         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 245         if (WARN_ON(domain->wake_count == 0))
 246                 domain->wake_count++;
 247
 248         if (--domain->wake_count == 0)
 249                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 250                                                           1 << domain->id);
 251
 252         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 253 }
 254
 255 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 256 {
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         unsigned long irqflags, fw = 0;
 259         struct intel_uncore_forcewake_domain *domain;
 260         int id, active_domains, retry_count = 100;
 261
 262         /* Hold uncore.lock across reset to prevent any register access
 263          * with forcewake not set correctly. Wait until all pending
 264          * timers are run before holding.
 265          */
 266         while (1) {
 267                 active_domains = 0;
 268
 269                 for_each_fw_domain(domain, dev_priv, id) {
 270                         if (del_timer_sync(&domain->timer) == 0)
 271                                 continue;
 272
 273                         gen6_force_wake_timer((unsigned long)domain);
 274                 }
 275
 276                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 277
 278                 for_each_fw_domain(domain, dev_priv, id) {
 279                         if (timer_pending(&domain->timer))
 280                                 active_domains |= (1 << id);
 281                 }
 282
 283                 if (active_domains == 0)
 284                         break;
 285
 286                 if (--retry_count == 0) {
 287                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 288                         break;
 289                 }
 290
 291                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 292                 cond_resched();
 293         }
 294
 295         WARN_ON(active_domains);
 296
 297         for_each_fw_domain(domain, dev_priv, id)
 298                 if (domain->wake_count)
 299                         fw |= 1 << id;
 300
 301         if (fw)
 302                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 303
 304         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 305
 306         if (restore) { /* If reset with a user forcewake, try to restore */
 307                 if (fw)
 308                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 309
 310                 if (IS_GEN6(dev) || IS_GEN7(dev))
 311                         dev_priv->uncore.fifo_count =
 312                                 __raw_i915_read32(dev_priv, GTFIFOCTL) &
 313                                 GT_FIFO_FREE_ENTRIES_MASK;
 314         }
 315
 316         if (!restore)
 317                 assert_force_wake_inactive(dev_priv);
 318
 319         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 320 }
 321
 322 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 323                                           bool restore_forcewake)
 324 {
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326
 327         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 328                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 329
 330         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
 331             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
 332                 /* The docs do not explain exactly how the calculation can be
 333                  * made. It is somewhat guessable, but for now, it's always
 334                  * 128MB.
 335                  * NB: We can't write IDICR yet because we do not have gt funcs
 336                  * set up */
 337                 dev_priv->ellc_size = 128;
 338                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 339         }
 340
 341         /* clear out old GT FIFO errors */
 342         if (IS_GEN6(dev) || IS_GEN7(dev))
 343                 __raw_i915_write32(dev_priv, GTFIFODBG,
 344                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 345
 346         intel_uncore_forcewake_reset(dev, restore_forcewake);
 347 }
 348
 349 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 350 {
 351         __intel_uncore_early_sanitize(dev, restore_forcewake);
 352         i915_check_and_clear_faults(dev);
 353 }
 354
 355 void intel_uncore_sanitize(struct drm_device *dev)
 356 {
 357         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 358         intel_disable_gt_powersave(dev);
 359 }
 360
 361 /*
 362  * Generally this is called implicitly by the register read function. However,
 363  * if some sequence requires the GT to not power down then this function should
 364  * be called at the beginning of the sequence followed by a call to
 365  * gen6_gt_force_wake_put() at the end of the sequence.
 366  */
 367 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
 368                             unsigned fw_domains)
 369 {
 370         unsigned long irqflags;
 371         struct intel_uncore_forcewake_domain *domain;
 372         int id;
 373
 374         if (!dev_priv->uncore.funcs.force_wake_get)
 375                 return;
 376
 377         WARN_ON(dev_priv->pm.suspended);
 378
 379         fw_domains &= dev_priv->uncore.fw_domains;
 380
 381         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 382
 383         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 384                 if (domain->wake_count++)
 385                         fw_domains &= ~(1 << id);
 386         }
 387
 388         if (fw_domains)
 389                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 390
 391         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 392 }
 393
 394 /*
 395  * see gen6_gt_force_wake_get()
 396  */
 397 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
 398                             unsigned fw_domains)
 399 {
 400         unsigned long irqflags;
 401         struct intel_uncore_forcewake_domain *domain;
 402         int id;
 403
 404         if (!dev_priv->uncore.funcs.force_wake_put)
 405                 return;
 406
 407         fw_domains &= dev_priv->uncore.fw_domains;
 408
 409         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 410
 411         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 412                 if (WARN_ON(domain->wake_count == 0))
 413                         continue;
 414
 415                 if (--domain->wake_count)
 416                         continue;
 417
 418                 domain->wake_count++;
 419                 fw_domain_arm_timer(domain);
 420         }
 421
 422         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 423 }
 424
 425 void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
 426 {
 427         struct intel_uncore_forcewake_domain *domain;
 428         int id;
 429
 430         if (!dev_priv->uncore.funcs.force_wake_get)
 431                 return;
 432
 433         for_each_fw_domain(domain, dev_priv, id)
 434                 WARN_ON(domain->wake_count);
 435 }
 436
 437 /* We give fast paths for the really cool registers */
 438 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 439          ((reg) < 0x40000 && (reg) != FORCEWAKE)
 440
 441 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 442
 443 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 444         (REG_RANGE((reg), 0x2000, 0x4000) || \
 445          REG_RANGE((reg), 0x5000, 0x8000) || \
 446          REG_RANGE((reg), 0xB000, 0x12000) || \
 447          REG_RANGE((reg), 0x2E000, 0x30000))
 448
 449 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 450         (REG_RANGE((reg), 0x12000, 0x14000) || \
 451          REG_RANGE((reg), 0x22000, 0x24000) || \
 452          REG_RANGE((reg), 0x30000, 0x40000))
 453
 454 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 455         (REG_RANGE((reg), 0x2000, 0x4000) || \
 456          REG_RANGE((reg), 0x5200, 0x8000) || \
 457          REG_RANGE((reg), 0x8300, 0x8500) || \
 458          REG_RANGE((reg), 0xB000, 0xB480) || \
 459          REG_RANGE((reg), 0xE000, 0xE800))
 460
 461 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 462         (REG_RANGE((reg), 0x8800, 0x8900) || \
 463          REG_RANGE((reg), 0xD000, 0xD800) || \
 464          REG_RANGE((reg), 0x12000, 0x14000) || \
 465          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 466          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 467          REG_RANGE((reg), 0x30000, 0x38000))
 468
 469 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 470         (REG_RANGE((reg), 0x4000, 0x5000) || \
 471          REG_RANGE((reg), 0x8000, 0x8300) || \
 472          REG_RANGE((reg), 0x8500, 0x8600) || \
 473          REG_RANGE((reg), 0x9000, 0xB000) || \
 474          REG_RANGE((reg), 0xF000, 0x10000))
 475
 476 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 477         REG_RANGE((reg), 0xB00,  0x2000)
 478
 479 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 480         (REG_RANGE((reg), 0x2000, 0x2700) || \
 481          REG_RANGE((reg), 0x3000, 0x4000) || \
 482          REG_RANGE((reg), 0x5200, 0x8000) || \
 483          REG_RANGE((reg), 0x8140, 0x8160) || \
 484          REG_RANGE((reg), 0x8300, 0x8500) || \
 485          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 486          REG_RANGE((reg), 0xB000, 0xB480) || \
 487          REG_RANGE((reg), 0xE000, 0xE900) || \
 488          REG_RANGE((reg), 0x24400, 0x24800))
 489
 490 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 491         (REG_RANGE((reg), 0x8130, 0x8140) || \
 492          REG_RANGE((reg), 0x8800, 0x8A00) || \
 493          REG_RANGE((reg), 0xD000, 0xD800) || \
 494          REG_RANGE((reg), 0x12000, 0x14000) || \
 495          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 496          REG_RANGE((reg), 0x30000, 0x40000))
 497
 498 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 499         REG_RANGE((reg), 0x9400, 0x9800)
 500
 501 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 502         ((reg) < 0x40000 &&\
 503          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 504          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 505          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 506          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 507
 508 static void
 509 ilk_dummy_write(struct drm_i915_private *dev_priv)
 510 {
 511         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 512          * the chip from rc6 before touching it for real. MI_MODE is masked,
 513          * hence harmless to write 0 into. */
 514         __raw_i915_write32(dev_priv, MI_MODE, 0);
 515 }
 516
 517 static void
 518 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
 519                         bool before)
 520 {
 521         const char *op = read ? "reading" : "writing to";
 522         const char *when = before ? "before" : "after";
 523
 524         if (!i915.mmio_debug)
 525                 return;
 526
 527         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 528                 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 529                      when, op, reg);
 530                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 531         }
 532 }
 533
 534 static void
 535 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 536 {
 537         if (i915.mmio_debug)
 538                 return;
 539
 540         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 541                 DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
 542                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 543         }
 544 }
 545
 546 #define GEN2_READ_HEADER(x) \
 547         u##x val = 0; \
 548         assert_device_not_suspended(dev_priv);
 549
 550 #define GEN2_READ_FOOTER \
 551         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 552         return val
 553
 554 #define __gen2_read(x) \
 555 static u##x \
 556 gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 557         GEN2_READ_HEADER(x); \
 558         val = __raw_i915_read##x(dev_priv, reg); \
 559         GEN2_READ_FOOTER; \
 560 }
 561
 562 #define __gen5_read(x) \
 563 static u##x \
 564 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 565         GEN2_READ_HEADER(x); \
 566         ilk_dummy_write(dev_priv); \
 567         val = __raw_i915_read##x(dev_priv, reg); \
 568         GEN2_READ_FOOTER; \
 569 }
 570
 571 __gen5_read(8)
 572 __gen5_read(16)
 573 __gen5_read(32)
 574 __gen5_read(64)
 575 __gen2_read(8)
 576 __gen2_read(16)
 577 __gen2_read(32)
 578 __gen2_read(64)
 579
 580 #undef __gen5_read
 581 #undef __gen2_read
 582
 583 #undef GEN2_READ_FOOTER
 584 #undef GEN2_READ_HEADER
 585
 586 #define GEN6_READ_HEADER(x) \
 587         unsigned long irqflags; \
 588         u##x val = 0; \
 589         assert_device_not_suspended(dev_priv); \
 590         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 591
 592 #define GEN6_READ_FOOTER \
 593         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 594         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 595         return val
 596
 597 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
 598                                     unsigned fw_domains)
 599 {
 600         struct intel_uncore_forcewake_domain *domain;
 601         int id;
 602
 603         if (WARN_ON(!fw_domains))
 604                 return;
 605
 606         /* Ideally GCC would be constant-fold and eliminate this loop */
 607         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 608                 if (domain->wake_count) {
 609                         fw_domains &= ~(1 << id);
 610                         continue;
 611                 }
 612
 613                 domain->wake_count++;
 614                 fw_domain_arm_timer(domain);
 615         }
 616
 617         if (fw_domains)
 618                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 619 }
 620
 621 #define __gen6_read(x) \
 622 static u##x \
 623 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 624         GEN6_READ_HEADER(x); \
 625         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 626         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
 627                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 628         val = __raw_i915_read##x(dev_priv, reg); \
 629         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 630         GEN6_READ_FOOTER; \
 631 }
 632
 633 #define __vlv_read(x) \
 634 static u##x \
 635 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 636         GEN6_READ_HEADER(x); \
 637         if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
 638                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 639         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \
 640                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 641         val = __raw_i915_read##x(dev_priv, reg); \
 642         GEN6_READ_FOOTER; \
 643 }
 644
 645 #define __chv_read(x) \
 646 static u##x \
 647 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 648         GEN6_READ_HEADER(x); \
 649         if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 650                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 651         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 652                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 653         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 654                 __force_wake_get(dev_priv, \
 655                                  FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 656         val = __raw_i915_read##x(dev_priv, reg); \
 657         GEN6_READ_FOOTER; \
 658 }
 659
 660 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)     \
 661          ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 662
 663 #define __gen9_read(x) \
 664 static u##x \
 665 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 666         unsigned fw_engine; \
 667         GEN6_READ_HEADER(x); \
 668         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)))   \
 669                 fw_engine = 0; \
 670         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg))       \
 671                 fw_engine = FORCEWAKE_RENDER; \
 672         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 673                 fw_engine = FORCEWAKE_MEDIA; \
 674         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 675                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 676         else \
 677                 fw_engine = FORCEWAKE_BLITTER; \
 678         if (fw_engine) \
 679                 __force_wake_get(dev_priv, fw_engine); \
 680         val = __raw_i915_read##x(dev_priv, reg); \
 681         GEN6_READ_FOOTER; \
 682 }
 683
 684 __gen9_read(8)
 685 __gen9_read(16)
 686 __gen9_read(32)
 687 __gen9_read(64)
 688 __chv_read(8)
 689 __chv_read(16)
 690 __chv_read(32)
 691 __chv_read(64)
 692 __vlv_read(8)
 693 __vlv_read(16)
 694 __vlv_read(32)
 695 __vlv_read(64)
 696 __gen6_read(8)
 697 __gen6_read(16)
 698 __gen6_read(32)
 699 __gen6_read(64)
 700
 701 #undef __gen9_read
 702 #undef __chv_read
 703 #undef __vlv_read
 704 #undef __gen6_read
 705 #undef GEN6_READ_FOOTER
 706 #undef GEN6_READ_HEADER
 707
 708 #define GEN2_WRITE_HEADER \
 709         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 710         assert_device_not_suspended(dev_priv); \
 711
 712 #define GEN2_WRITE_FOOTER
 713
 714 #define __gen2_write(x) \
 715 static void \
 716 gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 717         GEN2_WRITE_HEADER; \
 718         __raw_i915_write##x(dev_priv, reg, val); \
 719         GEN2_WRITE_FOOTER; \
 720 }
 721
 722 #define __gen5_write(x) \
 723 static void \
 724 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 725         GEN2_WRITE_HEADER; \
 726         ilk_dummy_write(dev_priv); \
 727         __raw_i915_write##x(dev_priv, reg, val); \
 728         GEN2_WRITE_FOOTER; \
 729 }
 730
 731 __gen5_write(8)
 732 __gen5_write(16)
 733 __gen5_write(32)
 734 __gen5_write(64)
 735 __gen2_write(8)
 736 __gen2_write(16)
 737 __gen2_write(32)
 738 __gen2_write(64)
 739
 740 #undef __gen5_write
 741 #undef __gen2_write
 742
 743 #undef GEN2_WRITE_FOOTER
 744 #undef GEN2_WRITE_HEADER
 745
 746 #define GEN6_WRITE_HEADER \
 747         unsigned long irqflags; \
 748         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 749         assert_device_not_suspended(dev_priv); \
 750         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 751
 752 #define GEN6_WRITE_FOOTER \
 753         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 754
 755 #define __gen6_write(x) \
 756 static void \
 757 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 758         u32 __fifo_ret = 0; \
 759         GEN6_WRITE_HEADER; \
 760         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 761                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 762         } \
 763         __raw_i915_write##x(dev_priv, reg, val); \
 764         if (unlikely(__fifo_ret)) { \
 765                 gen6_gt_check_fifodbg(dev_priv); \
 766         } \
 767         GEN6_WRITE_FOOTER; \
 768 }
 769
 770 #define __hsw_write(x) \
 771 static void \
 772 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 773         u32 __fifo_ret = 0; \
 774         GEN6_WRITE_HEADER; \
 775         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 776                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 777         } \
 778         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 779         __raw_i915_write##x(dev_priv, reg, val); \
 780         if (unlikely(__fifo_ret)) { \
 781                 gen6_gt_check_fifodbg(dev_priv); \
 782         } \
 783         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 784         hsw_unclaimed_reg_detect(dev_priv); \
 785         GEN6_WRITE_FOOTER; \
 786 }
 787
 788 static const u32 gen8_shadowed_regs[] = {
 789         FORCEWAKE_MT,
 790         GEN6_RPNSWREQ,
 791         GEN6_RC_VIDEO_FREQ,
 792         RING_TAIL(RENDER_RING_BASE),
 793         RING_TAIL(GEN6_BSD_RING_BASE),
 794         RING_TAIL(VEBOX_RING_BASE),
 795         RING_TAIL(BLT_RING_BASE),
 796         /* TODO: Other registers are not yet used */
 797 };
 798
 799 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 800 {
 801         int i;
 802         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 803                 if (reg == gen8_shadowed_regs[i])
 804                         return true;
 805
 806         return false;
 807 }
 808
 809 #define __gen8_write(x) \
 810 static void \
 811 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 812         GEN6_WRITE_HEADER; \
 813         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 814         if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
 815                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 816         __raw_i915_write##x(dev_priv, reg, val); \
 817         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 818         hsw_unclaimed_reg_detect(dev_priv); \
 819         GEN6_WRITE_FOOTER; \
 820 }
 821
 822 #define __chv_write(x) \
 823 static void \
 824 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 825         bool shadowed = is_gen8_shadowed(dev_priv, reg); \
 826         GEN6_WRITE_HEADER; \
 827         if (!shadowed) { \
 828                 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 829                         __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 830                 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 831                         __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 832                 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 833                         __force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 834         } \
 835         __raw_i915_write##x(dev_priv, reg, val); \
 836         GEN6_WRITE_FOOTER; \
 837 }
 838
 839 static const u32 gen9_shadowed_regs[] = {
 840         RING_TAIL(RENDER_RING_BASE),
 841         RING_TAIL(GEN6_BSD_RING_BASE),
 842         RING_TAIL(VEBOX_RING_BASE),
 843         RING_TAIL(BLT_RING_BASE),
 844         FORCEWAKE_BLITTER_GEN9,
 845         FORCEWAKE_RENDER_GEN9,
 846         FORCEWAKE_MEDIA_GEN9,
 847         GEN6_RPNSWREQ,
 848         GEN6_RC_VIDEO_FREQ,
 849         /* TODO: Other registers are not yet used */
 850 };
 851
 852 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 853 {
 854         int i;
 855         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 856                 if (reg == gen9_shadowed_regs[i])
 857                         return true;
 858
 859         return false;
 860 }
 861
 862 #define __gen9_write(x) \
 863 static void \
 864 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
 865                 bool trace) { \
 866         unsigned fw_engine; \
 867         GEN6_WRITE_HEADER; \
 868         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
 869             is_gen9_shadowed(dev_priv, reg)) \
 870                 fw_engine = 0; \
 871         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
 872                 fw_engine = FORCEWAKE_RENDER; \
 873         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 874                 fw_engine = FORCEWAKE_MEDIA; \
 875         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 876                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 877         else \
 878                 fw_engine = FORCEWAKE_BLITTER; \
 879         if (fw_engine) \
 880                 __force_wake_get(dev_priv, fw_engine); \
 881         __raw_i915_write##x(dev_priv, reg, val); \
 882         GEN6_WRITE_FOOTER; \
 883 }
 884
 885 __gen9_write(8)
 886 __gen9_write(16)
 887 __gen9_write(32)
 888 __gen9_write(64)
 889 __chv_write(8)
 890 __chv_write(16)
 891 __chv_write(32)
 892 __chv_write(64)
 893 __gen8_write(8)
 894 __gen8_write(16)
 895 __gen8_write(32)
 896 __gen8_write(64)
 897 __hsw_write(8)
 898 __hsw_write(16)
 899 __hsw_write(32)
 900 __hsw_write(64)
 901 __gen6_write(8)
 902 __gen6_write(16)
 903 __gen6_write(32)
 904 __gen6_write(64)
 905
 906 #undef __gen9_write
 907 #undef __chv_write
 908 #undef __gen8_write
 909 #undef __hsw_write
 910 #undef __gen6_write
 911 #undef GEN6_WRITE_FOOTER
 912 #undef GEN6_WRITE_HEADER
 913
 914 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
 915 do { \
 916         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
 917         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
 918         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
 919         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
 920 } while (0)
 921
 922 #define ASSIGN_READ_MMIO_VFUNCS(x) \
 923 do { \
 924         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
 925         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
 926         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
 927         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
 928 } while (0)
 929
 930
 931 static void fw_domain_init(struct drm_i915_private *dev_priv,
 932                            u32 domain_id, u32 reg_set, u32 reg_ack)
 933 {
 934         struct intel_uncore_forcewake_domain *d;
 935
 936         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
 937                 return;
 938
 939         d = &dev_priv->uncore.fw_domain[domain_id];
 940
 941         WARN_ON(d->wake_count);
 942
 943         d->wake_count = 0;
 944         d->reg_set = reg_set;
 945         d->reg_ack = reg_ack;
 946
 947         if (IS_GEN6(dev_priv)) {
 948                 d->val_reset = 0;
 949                 d->val_set = FORCEWAKE_KERNEL;
 950                 d->val_clear = 0;
 951         } else {
 952                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
 953                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
 954                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
 955         }
 956
 957         if (IS_VALLEYVIEW(dev_priv))
 958                 d->reg_post = FORCEWAKE_ACK_VLV;
 959         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
 960                 d->reg_post = ECOBUS;
 961         else
 962                 d->reg_post = 0;
 963
 964         d->i915 = dev_priv;
 965         d->id = domain_id;
 966
 967         setup_timer(&d->timer, gen6_force_wake_timer, (unsigned long)d);
 968
 969         dev_priv->uncore.fw_domains |= (1 << domain_id);
 970 }
 971
 972 void intel_uncore_init(struct drm_device *dev)
 973 {
 974         struct drm_i915_private *dev_priv = dev->dev_private;
 975
 976         __intel_uncore_early_sanitize(dev, false);
 977
 978         if (IS_GEN9(dev)) {
 979                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
 980                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
 981                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
 982                                FORCEWAKE_RENDER_GEN9,
 983                                FORCEWAKE_ACK_RENDER_GEN9);
 984                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
 985                                FORCEWAKE_BLITTER_GEN9,
 986                                FORCEWAKE_ACK_BLITTER_GEN9);
 987                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
 988                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
 989         } else if (IS_VALLEYVIEW(dev)) {
 990                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
 991                 if (!IS_CHERRYVIEW(dev))
 992                         dev_priv->uncore.funcs.force_wake_put =
 993                                 fw_domains_put_with_fifo;
 994                 else
 995                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
 996                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
 997                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
 998                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
 999                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1000         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1001                 dev_priv->uncore.funcs.force_wake_get =
1002                         fw_domains_get_with_thread_status;
1003                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1004                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1005                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1006         } else if (IS_IVYBRIDGE(dev)) {
1007                 u32 ecobus;
1008
1009                 /* IVB configs may use multi-threaded forcewake */
1010
1011                 /* A small trick here - if the bios hasn't configured
1012                  * MT forcewake, and if the device is in RC6, then
1013                  * force_wake_mt_get will not wake the device and the
1014                  * ECOBUS read will return zero. Which will be
1015                  * (correctly) interpreted by the test below as MT
1016                  * forcewake being disabled.
1017                  */
1018                 dev_priv->uncore.funcs.force_wake_get =
1019                         fw_domains_get_with_thread_status;
1020                 dev_priv->uncore.funcs.force_wake_put =
1021                         fw_domains_put_with_fifo;
1022
1023                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1024                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1025                 mutex_lock(&dev->struct_mutex);
1026                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1027                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1028                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1029                 mutex_unlock(&dev->struct_mutex);
1030
1031                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1032                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1033                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1034                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1035                                        FORCEWAKE, FORCEWAKE_ACK);
1036                 }
1037         } else if (IS_GEN6(dev)) {
1038                 dev_priv->uncore.funcs.force_wake_get =
1039                         fw_domains_get_with_thread_status;
1040                 dev_priv->uncore.funcs.force_wake_put =
1041                         fw_domains_put_with_fifo;
1042                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1043                                FORCEWAKE, FORCEWAKE_ACK);
1044         }
1045
1046         switch (INTEL_INFO(dev)->gen) {
1047         default:
1048                 MISSING_CASE(INTEL_INFO(dev)->gen);
1049                 return;
1050         case 9:
1051                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1052                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1053                 break;
1054         case 8:
1055                 if (IS_CHERRYVIEW(dev)) {
1056                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1057                         ASSIGN_READ_MMIO_VFUNCS(chv);
1058
1059                 } else {
1060                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1061                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1062                 }
1063                 break;
1064         case 7:
1065         case 6:
1066                 if (IS_HASWELL(dev)) {
1067                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1068                 } else {
1069                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1070                 }
1071
1072                 if (IS_VALLEYVIEW(dev)) {
1073                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1074                 } else {
1075                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1076                 }
1077                 break;
1078         case 5:
1079                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1080                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1081                 break;
1082         case 4:
1083         case 3:
1084         case 2:
1085                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1086                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1087                 break;
1088         }
1089
1090         i915_check_and_clear_faults(dev);
1091 }
1092 #undef ASSIGN_WRITE_MMIO_VFUNCS
1093 #undef ASSIGN_READ_MMIO_VFUNCS
1094
1095 void intel_uncore_fini(struct drm_device *dev)
1096 {
1097         /* Paranoia: make sure we have disabled everything before we exit. */
1098         intel_uncore_sanitize(dev);
1099         intel_uncore_forcewake_reset(dev, false);
1100 }
1101
1102 #define GEN_RANGE(l, h) GENMASK(h, l)
1103
1104 static const struct register_whitelist {
1105         uint64_t offset;
1106         uint32_t size;
1107         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1108         uint32_t gen_bitmask;
1109 } whitelist[] = {
1110         { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1111 };
1112
1113 int i915_reg_read_ioctl(struct drm_device *dev,
1114                         void *data, struct drm_file *file)
1115 {
1116         struct drm_i915_private *dev_priv = dev->dev_private;
1117         struct drm_i915_reg_read *reg = data;
1118         struct register_whitelist const *entry = whitelist;
1119         int i, ret = 0;
1120
1121         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1122                 if (entry->offset == reg->offset &&
1123                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1124                         break;
1125         }
1126
1127         if (i == ARRAY_SIZE(whitelist))
1128                 return -EINVAL;
1129
1130         intel_runtime_pm_get(dev_priv);
1131
1132         switch (entry->size) {
1133         case 8:
1134                 reg->val = I915_READ64(reg->offset);
1135                 break;
1136         case 4:
1137                 reg->val = I915_READ(reg->offset);
1138                 break;
1139         case 2:
1140                 reg->val = I915_READ16(reg->offset);
1141                 break;
1142         case 1:
1143                 reg->val = I915_READ8(reg->offset);
1144                 break;
1145         default:
1146                 MISSING_CASE(entry->size);
1147                 ret = -EINVAL;
1148                 goto out;
1149         }
1150
1151 out:
1152         intel_runtime_pm_put(dev_priv);
1153         return ret;
1154 }
1155
1156 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1157                                void *data, struct drm_file *file)
1158 {
1159         struct drm_i915_private *dev_priv = dev->dev_private;
1160         struct drm_i915_reset_stats *args = data;
1161         struct i915_ctx_hang_stats *hs;
1162         struct intel_context *ctx;
1163         int ret;
1164
1165         if (args->flags || args->pad)
1166                 return -EINVAL;
1167
1168         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1169                 return -EPERM;
1170
1171         ret = mutex_lock_interruptible(&dev->struct_mutex);
1172         if (ret)
1173                 return ret;
1174
1175         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1176         if (IS_ERR(ctx)) {
1177                 mutex_unlock(&dev->struct_mutex);
1178                 return PTR_ERR(ctx);
1179         }
1180         hs = &ctx->hang_stats;
1181
1182         if (capable(CAP_SYS_ADMIN))
1183                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1184         else
1185                 args->reset_count = 0;
1186
1187         args->batch_active = hs->batch_active;
1188         args->batch_pending = hs->batch_pending;
1189
1190         mutex_unlock(&dev->struct_mutex);
1191
1192         return 0;
1193 }
1194
1195 static int i915_reset_complete(struct drm_device *dev)
1196 {
1197         u8 gdrst;
1198         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1199         return (gdrst & GRDOM_RESET_STATUS) == 0;
1200 }
1201
1202 static int i915_do_reset(struct drm_device *dev)
1203 {
1204         /* assert reset for at least 20 usec */
1205         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1206         udelay(20);
1207         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1208
1209         return wait_for(i915_reset_complete(dev), 500);
1210 }
1211
1212 static int g4x_reset_complete(struct drm_device *dev)
1213 {
1214         u8 gdrst;
1215         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1216         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1217 }
1218
1219 static int g33_do_reset(struct drm_device *dev)
1220 {
1221         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1222         return wait_for(g4x_reset_complete(dev), 500);
1223 }
1224
1225 static int g4x_do_reset(struct drm_device *dev)
1226 {
1227         struct drm_i915_private *dev_priv = dev->dev_private;
1228         int ret;
1229
1230         pci_write_config_byte(dev->pdev, I915_GDRST,
1231                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1232         ret =  wait_for(g4x_reset_complete(dev), 500);
1233         if (ret)
1234                 return ret;
1235
1236         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1237         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1238         POSTING_READ(VDECCLK_GATE_D);
1239
1240         pci_write_config_byte(dev->pdev, I915_GDRST,
1241                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1242         ret =  wait_for(g4x_reset_complete(dev), 500);
1243         if (ret)
1244                 return ret;
1245
1246         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1247         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1248         POSTING_READ(VDECCLK_GATE_D);
1249
1250         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1251
1252         return 0;
1253 }
1254
1255 static int ironlake_do_reset(struct drm_device *dev)
1256 {
1257         struct drm_i915_private *dev_priv = dev->dev_private;
1258         int ret;
1259
1260         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1261                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1262         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1263                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1264         if (ret)
1265                 return ret;
1266
1267         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1268                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1269         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1270                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1271         if (ret)
1272                 return ret;
1273
1274         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1275
1276         return 0;
1277 }
1278
1279 static int gen6_do_reset(struct drm_device *dev)
1280 {
1281         struct drm_i915_private *dev_priv = dev->dev_private;
1282         int     ret;
1283
1284         /* Reset the chip */
1285
1286         /* GEN6_GDRST is not in the gt power well, no need to check
1287          * for fifo space for the write or forcewake the chip for
1288          * the read
1289          */
1290         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1291
1292         /* Spin waiting for the device to ack the reset request */
1293         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1294
1295         intel_uncore_forcewake_reset(dev, true);
1296
1297         return ret;
1298 }
1299
1300 int intel_gpu_reset(struct drm_device *dev)
1301 {
1302         if (INTEL_INFO(dev)->gen >= 6)
1303                 return gen6_do_reset(dev);
1304         else if (IS_GEN5(dev))
1305                 return ironlake_do_reset(dev);
1306         else if (IS_G4X(dev))
1307                 return g4x_do_reset(dev);
1308         else if (IS_G33(dev))
1309                 return g33_do_reset(dev);
1310         else if (INTEL_INFO(dev)->gen >= 3)
1311                 return i915_do_reset(dev);
1312         else
1313                 return -ENODEV;
1314 }
1315
1316 void intel_uncore_check_errors(struct drm_device *dev)
1317 {
1318         struct drm_i915_private *dev_priv = dev->dev_private;
1319
1320         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1321             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1322                 DRM_ERROR("Unclaimed register before interrupt\n");
1323                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1324         }
1325 }