drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26
  27 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  28
  29 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
  30 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
  31
  32 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
  33 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
  34
  35 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  36 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
  37
  38 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
  39 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
  40
  41 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  42
  43 static void
  44 assert_device_not_suspended(struct drm_i915_private *dev_priv)
  45 {
  46         WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
  47                   "Device suspended\n");
  48 }
  49
  50 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
  51 {
  52         /* w/a for a sporadic read returning 0 by waiting for the GT
  53          * thread to wake up.
  54          */
  55         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
  56                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
  57                 DRM_ERROR("GT thread status wait timed out\n");
  58 }
  59
  60 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
  61 {
  62         __raw_i915_write32(dev_priv, FORCEWAKE, 0);
  63         /* something from same cacheline, but !FORCEWAKE */
  64         __raw_posting_read(dev_priv, ECOBUS);
  65 }
  66
  67 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
  68                                                         int fw_engine)
  69 {
  70         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
  71                             FORCEWAKE_ACK_TIMEOUT_MS))
  72                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
  73
  74         __raw_i915_write32(dev_priv, FORCEWAKE, 1);
  75         /* something from same cacheline, but !FORCEWAKE */
  76         __raw_posting_read(dev_priv, ECOBUS);
  77
  78         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
  79                             FORCEWAKE_ACK_TIMEOUT_MS))
  80                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
  81
  82         /* WaRsForcewakeWaitTC0:snb */
  83         __gen6_gt_wait_for_thread_c0(dev_priv);
  84 }
  85
  86 static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
  87 {
  88         __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
  89         /* something from same cacheline, but !FORCEWAKE_MT */
  90         __raw_posting_read(dev_priv, ECOBUS);
  91 }
  92
  93 static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
  94                                                         int fw_engine)
  95 {
  96         u32 forcewake_ack;
  97
  98         if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev))
  99                 forcewake_ack = FORCEWAKE_ACK_HSW;
 100         else
 101                 forcewake_ack = FORCEWAKE_MT_ACK;
 102
 103         if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
 104                             FORCEWAKE_ACK_TIMEOUT_MS))
 105                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
 106
 107         __raw_i915_write32(dev_priv, FORCEWAKE_MT,
 108                            _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 109         /* something from same cacheline, but !FORCEWAKE_MT */
 110         __raw_posting_read(dev_priv, ECOBUS);
 111
 112         if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
 113                             FORCEWAKE_ACK_TIMEOUT_MS))
 114                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
 115
 116         /* WaRsForcewakeWaitTC0:ivb,hsw */
 117         __gen6_gt_wait_for_thread_c0(dev_priv);
 118 }
 119
 120 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 121 {
 122         u32 gtfifodbg;
 123
 124         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 125         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 126                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 127 }
 128
 129 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
 130                                                         int fw_engine)
 131 {
 132         __raw_i915_write32(dev_priv, FORCEWAKE, 0);
 133         /* something from same cacheline, but !FORCEWAKE */
 134         __raw_posting_read(dev_priv, ECOBUS);
 135         gen6_gt_check_fifodbg(dev_priv);
 136 }
 137
 138 static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
 139                                                         int fw_engine)
 140 {
 141         __raw_i915_write32(dev_priv, FORCEWAKE_MT,
 142                            _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 143         /* something from same cacheline, but !FORCEWAKE_MT */
 144         __raw_posting_read(dev_priv, ECOBUS);
 145
 146         if (IS_GEN7(dev_priv->dev))
 147                 gen6_gt_check_fifodbg(dev_priv);
 148 }
 149
 150 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 151 {
 152         int ret = 0;
 153
 154         /* On VLV, FIFO will be shared by both SW and HW.
 155          * So, we need to read the FREE_ENTRIES everytime */
 156         if (IS_VALLEYVIEW(dev_priv->dev))
 157                 dev_priv->uncore.fifo_count =
 158                         __raw_i915_read32(dev_priv, GTFIFOCTL) &
 159                                                 GT_FIFO_FREE_ENTRIES_MASK;
 160
 161         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 162                 int loop = 500;
 163                 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 164                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 165                         udelay(10);
 166                         fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 167                 }
 168                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 169                         ++ret;
 170                 dev_priv->uncore.fifo_count = fifo;
 171         }
 172         dev_priv->uncore.fifo_count--;
 173
 174         return ret;
 175 }
 176
 177 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
 178 {
 179         __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 180                            _MASKED_BIT_DISABLE(0xffff));
 181         __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 182                            _MASKED_BIT_DISABLE(0xffff));
 183         /* something from same cacheline, but !FORCEWAKE_VLV */
 184         __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
 185 }
 186
 187 static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
 188                                                 int fw_engine)
 189 {
 190         /* Check for Render Engine */
 191         if (FORCEWAKE_RENDER & fw_engine) {
 192                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 193                                                 FORCEWAKE_ACK_VLV) &
 194                                                 FORCEWAKE_KERNEL) == 0,
 195                                         FORCEWAKE_ACK_TIMEOUT_MS))
 196                         DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
 197
 198                 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 199                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 200
 201                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 202                                                 FORCEWAKE_ACK_VLV) &
 203                                                 FORCEWAKE_KERNEL),
 204                                         FORCEWAKE_ACK_TIMEOUT_MS))
 205                         DRM_ERROR("Timed out: waiting for Render to ack.\n");
 206         }
 207
 208         /* Check for Media Engine */
 209         if (FORCEWAKE_MEDIA & fw_engine) {
 210                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 211                                                 FORCEWAKE_ACK_MEDIA_VLV) &
 212                                                 FORCEWAKE_KERNEL) == 0,
 213                                         FORCEWAKE_ACK_TIMEOUT_MS))
 214                         DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
 215
 216                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 217                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 218
 219                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 220                                                 FORCEWAKE_ACK_MEDIA_VLV) &
 221                                                 FORCEWAKE_KERNEL),
 222                                         FORCEWAKE_ACK_TIMEOUT_MS))
 223                         DRM_ERROR("Timed out: waiting for media to ack.\n");
 224         }
 225 }
 226
 227 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
 228                                         int fw_engine)
 229 {
 230
 231         /* Check for Render Engine */
 232         if (FORCEWAKE_RENDER & fw_engine)
 233                 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 234                                         _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 235
 236
 237         /* Check for Media Engine */
 238         if (FORCEWAKE_MEDIA & fw_engine)
 239                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 240                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 241
 242         /* something from same cacheline, but !FORCEWAKE_VLV */
 243         __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
 244         if (!IS_CHERRYVIEW(dev_priv->dev))
 245                 gen6_gt_check_fifodbg(dev_priv);
 246 }
 247
 248 static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 249 {
 250         unsigned long irqflags;
 251
 252         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 253
 254         if (fw_engine & FORCEWAKE_RENDER &&
 255             dev_priv->uncore.fw_rendercount++ != 0)
 256                 fw_engine &= ~FORCEWAKE_RENDER;
 257         if (fw_engine & FORCEWAKE_MEDIA &&
 258             dev_priv->uncore.fw_mediacount++ != 0)
 259                 fw_engine &= ~FORCEWAKE_MEDIA;
 260
 261         if (fw_engine)
 262                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
 263
 264         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 265 }
 266
 267 static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 268 {
 269         unsigned long irqflags;
 270
 271         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 272
 273         if (fw_engine & FORCEWAKE_RENDER) {
 274                 WARN_ON(!dev_priv->uncore.fw_rendercount);
 275                 if (--dev_priv->uncore.fw_rendercount != 0)
 276                         fw_engine &= ~FORCEWAKE_RENDER;
 277         }
 278
 279         if (fw_engine & FORCEWAKE_MEDIA) {
 280                 WARN_ON(!dev_priv->uncore.fw_mediacount);
 281                 if (--dev_priv->uncore.fw_mediacount != 0)
 282                         fw_engine &= ~FORCEWAKE_MEDIA;
 283         }
 284
 285         if (fw_engine)
 286                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine);
 287
 288         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 289 }
 290
 291 static void __gen9_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
 292 {
 293         __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
 294                         _MASKED_BIT_DISABLE(0xffff));
 295
 296         __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
 297                         _MASKED_BIT_DISABLE(0xffff));
 298
 299         __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
 300                         _MASKED_BIT_DISABLE(0xffff));
 301 }
 302
 303 static void
 304 __gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 305 {
 306         /* Check for Render Engine */
 307         if (FORCEWAKE_RENDER & fw_engine) {
 308                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 309                                                 FORCEWAKE_ACK_RENDER_GEN9) &
 310                                                 FORCEWAKE_KERNEL) == 0,
 311                                         FORCEWAKE_ACK_TIMEOUT_MS))
 312                         DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
 313
 314                 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
 315                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 316
 317                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 318                                                 FORCEWAKE_ACK_RENDER_GEN9) &
 319                                                 FORCEWAKE_KERNEL),
 320                                         FORCEWAKE_ACK_TIMEOUT_MS))
 321                         DRM_ERROR("Timed out: waiting for Render to ack.\n");
 322         }
 323
 324         /* Check for Media Engine */
 325         if (FORCEWAKE_MEDIA & fw_engine) {
 326                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 327                                                 FORCEWAKE_ACK_MEDIA_GEN9) &
 328                                                 FORCEWAKE_KERNEL) == 0,
 329                                         FORCEWAKE_ACK_TIMEOUT_MS))
 330                         DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
 331
 332                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
 333                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 334
 335                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 336                                                 FORCEWAKE_ACK_MEDIA_GEN9) &
 337                                                 FORCEWAKE_KERNEL),
 338                                         FORCEWAKE_ACK_TIMEOUT_MS))
 339                         DRM_ERROR("Timed out: waiting for Media to ack.\n");
 340         }
 341
 342         /* Check for Blitter Engine */
 343         if (FORCEWAKE_BLITTER & fw_engine) {
 344                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 345                                                 FORCEWAKE_ACK_BLITTER_GEN9) &
 346                                                 FORCEWAKE_KERNEL) == 0,
 347                                         FORCEWAKE_ACK_TIMEOUT_MS))
 348                         DRM_ERROR("Timed out: Blitter forcewake old ack to clear.\n");
 349
 350                 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
 351                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 352
 353                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 354                                                 FORCEWAKE_ACK_BLITTER_GEN9) &
 355                                                 FORCEWAKE_KERNEL),
 356                                         FORCEWAKE_ACK_TIMEOUT_MS))
 357                         DRM_ERROR("Timed out: waiting for Blitter to ack.\n");
 358         }
 359 }
 360
 361 static void
 362 __gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 363 {
 364         /* Check for Render Engine */
 365         if (FORCEWAKE_RENDER & fw_engine)
 366                 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
 367                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 368
 369         /* Check for Media Engine */
 370         if (FORCEWAKE_MEDIA & fw_engine)
 371                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
 372                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 373
 374         /* Check for Blitter Engine */
 375         if (FORCEWAKE_BLITTER & fw_engine)
 376                 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
 377                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 378 }
 379
 380 static void
 381 gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 382 {
 383         unsigned long irqflags;
 384
 385         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 386
 387         if (FORCEWAKE_RENDER & fw_engine) {
 388                 if (dev_priv->uncore.fw_rendercount++ == 0)
 389                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 390                                                         FORCEWAKE_RENDER);
 391         }
 392
 393         if (FORCEWAKE_MEDIA & fw_engine) {
 394                 if (dev_priv->uncore.fw_mediacount++ == 0)
 395                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 396                                                         FORCEWAKE_MEDIA);
 397         }
 398
 399         if (FORCEWAKE_BLITTER & fw_engine) {
 400                 if (dev_priv->uncore.fw_blittercount++ == 0)
 401                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 402                                                         FORCEWAKE_BLITTER);
 403         }
 404
 405         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 406 }
 407
 408 static void
 409 gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 410 {
 411         unsigned long irqflags;
 412
 413         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 414
 415         if (FORCEWAKE_RENDER & fw_engine) {
 416                 WARN_ON(dev_priv->uncore.fw_rendercount == 0);
 417                 if (--dev_priv->uncore.fw_rendercount == 0)
 418                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 419                                                         FORCEWAKE_RENDER);
 420         }
 421
 422         if (FORCEWAKE_MEDIA & fw_engine) {
 423                 WARN_ON(dev_priv->uncore.fw_mediacount == 0);
 424                 if (--dev_priv->uncore.fw_mediacount == 0)
 425                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 426                                                         FORCEWAKE_MEDIA);
 427         }
 428
 429         if (FORCEWAKE_BLITTER & fw_engine) {
 430                 WARN_ON(dev_priv->uncore.fw_blittercount == 0);
 431                 if (--dev_priv->uncore.fw_blittercount == 0)
 432                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 433                                                         FORCEWAKE_BLITTER);
 434         }
 435
 436         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 437 }
 438
 439 static void gen6_force_wake_timer(unsigned long arg)
 440 {
 441         struct drm_i915_private *dev_priv = (void *)arg;
 442         unsigned long irqflags;
 443
 444         assert_device_not_suspended(dev_priv);
 445
 446         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 447         WARN_ON(!dev_priv->uncore.forcewake_count);
 448
 449         if (--dev_priv->uncore.forcewake_count == 0)
 450                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
 451         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 452 }
 453
 454 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 455 {
 456         struct drm_i915_private *dev_priv = dev->dev_private;
 457         unsigned long irqflags;
 458
 459         if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
 460                 gen6_force_wake_timer((unsigned long)dev_priv);
 461
 462         /* Hold uncore.lock across reset to prevent any register access
 463          * with forcewake not set correctly
 464          */
 465         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 466
 467         if (IS_VALLEYVIEW(dev))
 468                 vlv_force_wake_reset(dev_priv);
 469         else if (IS_GEN6(dev) || IS_GEN7(dev))
 470                 __gen6_gt_force_wake_reset(dev_priv);
 471
 472         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
 473                 __gen7_gt_force_wake_mt_reset(dev_priv);
 474
 475         if (IS_GEN9(dev))
 476                 __gen9_gt_force_wake_mt_reset(dev_priv);
 477
 478         if (restore) { /* If reset with a user forcewake, try to restore */
 479                 unsigned fw = 0;
 480
 481                 if (IS_VALLEYVIEW(dev)) {
 482                         if (dev_priv->uncore.fw_rendercount)
 483                                 fw |= FORCEWAKE_RENDER;
 484
 485                         if (dev_priv->uncore.fw_mediacount)
 486                                 fw |= FORCEWAKE_MEDIA;
 487                 } else if (IS_GEN9(dev)) {
 488                         if (dev_priv->uncore.fw_rendercount)
 489                                 fw |= FORCEWAKE_RENDER;
 490
 491                         if (dev_priv->uncore.fw_mediacount)
 492                                 fw |= FORCEWAKE_MEDIA;
 493
 494                         if (dev_priv->uncore.fw_blittercount)
 495                                 fw |= FORCEWAKE_BLITTER;
 496                 } else {
 497                         if (dev_priv->uncore.forcewake_count)
 498                                 fw = FORCEWAKE_ALL;
 499                 }
 500
 501                 if (fw)
 502                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 503
 504                 if (IS_GEN6(dev) || IS_GEN7(dev))
 505                         dev_priv->uncore.fifo_count =
 506                                 __raw_i915_read32(dev_priv, GTFIFOCTL) &
 507                                 GT_FIFO_FREE_ENTRIES_MASK;
 508         }
 509
 510         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 511 }
 512
 513 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 514                                           bool restore_forcewake)
 515 {
 516         struct drm_i915_private *dev_priv = dev->dev_private;
 517
 518         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 519                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 520
 521         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
 522             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
 523                 /* The docs do not explain exactly how the calculation can be
 524                  * made. It is somewhat guessable, but for now, it's always
 525                  * 128MB.
 526                  * NB: We can't write IDICR yet because we do not have gt funcs
 527                  * set up */
 528                 dev_priv->ellc_size = 128;
 529                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 530         }
 531
 532         /* clear out old GT FIFO errors */
 533         if (IS_GEN6(dev) || IS_GEN7(dev))
 534                 __raw_i915_write32(dev_priv, GTFIFODBG,
 535                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 536
 537         intel_uncore_forcewake_reset(dev, restore_forcewake);
 538 }
 539
 540 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 541 {
 542         __intel_uncore_early_sanitize(dev, restore_forcewake);
 543         i915_check_and_clear_faults(dev);
 544 }
 545
 546 void intel_uncore_sanitize(struct drm_device *dev)
 547 {
 548         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 549         intel_disable_gt_powersave(dev);
 550 }
 551
 552 /*
 553  * Generally this is called implicitly by the register read function. However,
 554  * if some sequence requires the GT to not power down then this function should
 555  * be called at the beginning of the sequence followed by a call to
 556  * gen6_gt_force_wake_put() at the end of the sequence.
 557  */
 558 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 559 {
 560         unsigned long irqflags;
 561
 562         if (!dev_priv->uncore.funcs.force_wake_get)
 563                 return;
 564
 565         intel_runtime_pm_get(dev_priv);
 566
 567         /* Redirect to Gen9 specific routine */
 568         if (IS_GEN9(dev_priv->dev))
 569                 return gen9_force_wake_get(dev_priv, fw_engine);
 570
 571         /* Redirect to VLV specific routine */
 572         if (IS_VALLEYVIEW(dev_priv->dev))
 573                 return vlv_force_wake_get(dev_priv, fw_engine);
 574
 575         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 576         if (dev_priv->uncore.forcewake_count++ == 0)
 577                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
 578         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 579 }
 580
 581 /*
 582  * see gen6_gt_force_wake_get()
 583  */
 584 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 585 {
 586         unsigned long irqflags;
 587
 588         if (!dev_priv->uncore.funcs.force_wake_put)
 589                 return;
 590
 591         /* Redirect to Gen9 specific routine */
 592         if (IS_GEN9(dev_priv->dev)) {
 593                 gen9_force_wake_put(dev_priv, fw_engine);
 594                 goto out;
 595         }
 596
 597         /* Redirect to VLV specific routine */
 598         if (IS_VALLEYVIEW(dev_priv->dev)) {
 599                 vlv_force_wake_put(dev_priv, fw_engine);
 600                 goto out;
 601         }
 602
 603         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 604         WARN_ON(!dev_priv->uncore.forcewake_count);
 605
 606         if (--dev_priv->uncore.forcewake_count == 0) {
 607                 dev_priv->uncore.forcewake_count++;
 608                 mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
 609                                  jiffies + 1);
 610         }
 611
 612         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 613
 614 out:
 615         intel_runtime_pm_put(dev_priv);
 616 }
 617
 618 void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
 619 {
 620         if (!dev_priv->uncore.funcs.force_wake_get)
 621                 return;
 622
 623         WARN_ON(dev_priv->uncore.forcewake_count > 0);
 624 }
 625
 626 /* We give fast paths for the really cool registers */
 627 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 628          ((reg) < 0x40000 && (reg) != FORCEWAKE)
 629
 630 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 631
 632 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 633         (REG_RANGE((reg), 0x2000, 0x4000) || \
 634          REG_RANGE((reg), 0x5000, 0x8000) || \
 635          REG_RANGE((reg), 0xB000, 0x12000) || \
 636          REG_RANGE((reg), 0x2E000, 0x30000))
 637
 638 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 639         (REG_RANGE((reg), 0x12000, 0x14000) || \
 640          REG_RANGE((reg), 0x22000, 0x24000) || \
 641          REG_RANGE((reg), 0x30000, 0x40000))
 642
 643 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 644         (REG_RANGE((reg), 0x2000, 0x4000) || \
 645          REG_RANGE((reg), 0x5200, 0x8000) || \
 646          REG_RANGE((reg), 0x8300, 0x8500) || \
 647          REG_RANGE((reg), 0xB000, 0xB480) || \
 648          REG_RANGE((reg), 0xE000, 0xE800))
 649
 650 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 651         (REG_RANGE((reg), 0x8800, 0x8900) || \
 652          REG_RANGE((reg), 0xD000, 0xD800) || \
 653          REG_RANGE((reg), 0x12000, 0x14000) || \
 654          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 655          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 656          REG_RANGE((reg), 0x30000, 0x38000))
 657
 658 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 659         (REG_RANGE((reg), 0x4000, 0x5000) || \
 660          REG_RANGE((reg), 0x8000, 0x8300) || \
 661          REG_RANGE((reg), 0x8500, 0x8600) || \
 662          REG_RANGE((reg), 0x9000, 0xB000) || \
 663          REG_RANGE((reg), 0xF000, 0x10000))
 664
 665 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 666         REG_RANGE((reg), 0xB00,  0x2000)
 667
 668 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 669         (REG_RANGE((reg), 0x2000, 0x2700) || \
 670          REG_RANGE((reg), 0x3000, 0x4000) || \
 671          REG_RANGE((reg), 0x5200, 0x8000) || \
 672          REG_RANGE((reg), 0x8140, 0x8160) || \
 673          REG_RANGE((reg), 0x8300, 0x8500) || \
 674          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 675          REG_RANGE((reg), 0xB000, 0xB480) || \
 676          REG_RANGE((reg), 0xE000, 0xE900) || \
 677          REG_RANGE((reg), 0x24400, 0x24800))
 678
 679 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 680         (REG_RANGE((reg), 0x8130, 0x8140) || \
 681          REG_RANGE((reg), 0x8800, 0x8A00) || \
 682          REG_RANGE((reg), 0xD000, 0xD800) || \
 683          REG_RANGE((reg), 0x12000, 0x14000) || \
 684          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 685          REG_RANGE((reg), 0x30000, 0x40000))
 686
 687 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 688         REG_RANGE((reg), 0x9400, 0x9800)
 689
 690 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 691         ((reg) < 0x40000 &&\
 692          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 693          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 694          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 695          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 696
 697 static void
 698 ilk_dummy_write(struct drm_i915_private *dev_priv)
 699 {
 700         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 701          * the chip from rc6 before touching it for real. MI_MODE is masked,
 702          * hence harmless to write 0 into. */
 703         __raw_i915_write32(dev_priv, MI_MODE, 0);
 704 }
 705
 706 static void
 707 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
 708                         bool before)
 709 {
 710         const char *op = read ? "reading" : "writing to";
 711         const char *when = before ? "before" : "after";
 712
 713         if (!i915.mmio_debug)
 714                 return;
 715
 716         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 717                 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 718                      when, op, reg);
 719                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 720         }
 721 }
 722
 723 static void
 724 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 725 {
 726         if (i915.mmio_debug)
 727                 return;
 728
 729         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 730                 DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
 731                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 732         }
 733 }
 734
 735 #define REG_READ_HEADER(x) \
 736         unsigned long irqflags; \
 737         u##x val = 0; \
 738         assert_device_not_suspended(dev_priv); \
 739         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 740
 741 #define REG_READ_FOOTER \
 742         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 743         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 744         return val
 745
 746 #define __gen4_read(x) \
 747 static u##x \
 748 gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 749         REG_READ_HEADER(x); \
 750         val = __raw_i915_read##x(dev_priv, reg); \
 751         REG_READ_FOOTER; \
 752 }
 753
 754 #define __gen5_read(x) \
 755 static u##x \
 756 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 757         REG_READ_HEADER(x); \
 758         ilk_dummy_write(dev_priv); \
 759         val = __raw_i915_read##x(dev_priv, reg); \
 760         REG_READ_FOOTER; \
 761 }
 762
 763 #define __gen6_read(x) \
 764 static u##x \
 765 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 766         REG_READ_HEADER(x); \
 767         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 768         if (dev_priv->uncore.forcewake_count == 0 && \
 769             NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 770                 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
 771                                                       FORCEWAKE_ALL); \
 772                 dev_priv->uncore.forcewake_count++; \
 773                 mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \
 774                                  jiffies + 1); \
 775         } \
 776         val = __raw_i915_read##x(dev_priv, reg); \
 777         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 778         REG_READ_FOOTER; \
 779 }
 780
 781 #define __vlv_read(x) \
 782 static u##x \
 783 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 784         unsigned fwengine = 0; \
 785         REG_READ_HEADER(x); \
 786         if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
 787                 if (dev_priv->uncore.fw_rendercount == 0) \
 788                         fwengine = FORCEWAKE_RENDER; \
 789         } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
 790                 if (dev_priv->uncore.fw_mediacount == 0) \
 791                         fwengine = FORCEWAKE_MEDIA; \
 792         }  \
 793         if (fwengine) \
 794                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 795         val = __raw_i915_read##x(dev_priv, reg); \
 796         if (fwengine) \
 797                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 798         REG_READ_FOOTER; \
 799 }
 800
 801 #define __chv_read(x) \
 802 static u##x \
 803 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 804         unsigned fwengine = 0; \
 805         REG_READ_HEADER(x); \
 806         if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
 807                 if (dev_priv->uncore.fw_rendercount == 0) \
 808                         fwengine = FORCEWAKE_RENDER; \
 809         } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
 810                 if (dev_priv->uncore.fw_mediacount == 0) \
 811                         fwengine = FORCEWAKE_MEDIA; \
 812         } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
 813                 if (dev_priv->uncore.fw_rendercount == 0) \
 814                         fwengine |= FORCEWAKE_RENDER; \
 815                 if (dev_priv->uncore.fw_mediacount == 0) \
 816                         fwengine |= FORCEWAKE_MEDIA; \
 817         } \
 818         if (fwengine) \
 819                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 820         val = __raw_i915_read##x(dev_priv, reg); \
 821         if (fwengine) \
 822                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 823         REG_READ_FOOTER; \
 824 }
 825
 826 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)     \
 827          ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 828
 829 #define __gen9_read(x) \
 830 static u##x \
 831 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 832         REG_READ_HEADER(x); \
 833         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 834                 val = __raw_i915_read##x(dev_priv, reg); \
 835         } else { \
 836                 unsigned fwengine = 0; \
 837                 if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
 838                         if (dev_priv->uncore.fw_rendercount == 0) \
 839                                 fwengine = FORCEWAKE_RENDER; \
 840                 } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
 841                         if (dev_priv->uncore.fw_mediacount == 0) \
 842                                 fwengine = FORCEWAKE_MEDIA; \
 843                 } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
 844                         if (dev_priv->uncore.fw_rendercount == 0) \
 845                                 fwengine |= FORCEWAKE_RENDER; \
 846                         if (dev_priv->uncore.fw_mediacount == 0) \
 847                                 fwengine |= FORCEWAKE_MEDIA; \
 848                 } else { \
 849                         if (dev_priv->uncore.fw_blittercount == 0) \
 850                                 fwengine = FORCEWAKE_BLITTER; \
 851                 } \
 852                 if (fwengine) \
 853                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 854                 val = __raw_i915_read##x(dev_priv, reg); \
 855                 if (fwengine) \
 856                         dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 857         } \
 858         REG_READ_FOOTER; \
 859 }
 860
 861 __gen9_read(8)
 862 __gen9_read(16)
 863 __gen9_read(32)
 864 __gen9_read(64)
 865 __chv_read(8)
 866 __chv_read(16)
 867 __chv_read(32)
 868 __chv_read(64)
 869 __vlv_read(8)
 870 __vlv_read(16)
 871 __vlv_read(32)
 872 __vlv_read(64)
 873 __gen6_read(8)
 874 __gen6_read(16)
 875 __gen6_read(32)
 876 __gen6_read(64)
 877 __gen5_read(8)
 878 __gen5_read(16)
 879 __gen5_read(32)
 880 __gen5_read(64)
 881 __gen4_read(8)
 882 __gen4_read(16)
 883 __gen4_read(32)
 884 __gen4_read(64)
 885
 886 #undef __gen9_read
 887 #undef __chv_read
 888 #undef __vlv_read
 889 #undef __gen6_read
 890 #undef __gen5_read
 891 #undef __gen4_read
 892 #undef REG_READ_FOOTER
 893 #undef REG_READ_HEADER
 894
 895 #define REG_WRITE_HEADER \
 896         unsigned long irqflags; \
 897         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 898         assert_device_not_suspended(dev_priv); \
 899         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 900
 901 #define REG_WRITE_FOOTER \
 902         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 903
 904 #define __gen4_write(x) \
 905 static void \
 906 gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 907         REG_WRITE_HEADER; \
 908         __raw_i915_write##x(dev_priv, reg, val); \
 909         REG_WRITE_FOOTER; \
 910 }
 911
 912 #define __gen5_write(x) \
 913 static void \
 914 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 915         REG_WRITE_HEADER; \
 916         ilk_dummy_write(dev_priv); \
 917         __raw_i915_write##x(dev_priv, reg, val); \
 918         REG_WRITE_FOOTER; \
 919 }
 920
 921 #define __gen6_write(x) \
 922 static void \
 923 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 924         u32 __fifo_ret = 0; \
 925         REG_WRITE_HEADER; \
 926         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 927                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 928         } \
 929         __raw_i915_write##x(dev_priv, reg, val); \
 930         if (unlikely(__fifo_ret)) { \
 931                 gen6_gt_check_fifodbg(dev_priv); \
 932         } \
 933         REG_WRITE_FOOTER; \
 934 }
 935
 936 #define __hsw_write(x) \
 937 static void \
 938 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 939         u32 __fifo_ret = 0; \
 940         REG_WRITE_HEADER; \
 941         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 942                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 943         } \
 944         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 945         __raw_i915_write##x(dev_priv, reg, val); \
 946         if (unlikely(__fifo_ret)) { \
 947                 gen6_gt_check_fifodbg(dev_priv); \
 948         } \
 949         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 950         hsw_unclaimed_reg_detect(dev_priv); \
 951         REG_WRITE_FOOTER; \
 952 }
 953
 954 static const u32 gen8_shadowed_regs[] = {
 955         FORCEWAKE_MT,
 956         GEN6_RPNSWREQ,
 957         GEN6_RC_VIDEO_FREQ,
 958         RING_TAIL(RENDER_RING_BASE),
 959         RING_TAIL(GEN6_BSD_RING_BASE),
 960         RING_TAIL(VEBOX_RING_BASE),
 961         RING_TAIL(BLT_RING_BASE),
 962         /* TODO: Other registers are not yet used */
 963 };
 964
 965 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 966 {
 967         int i;
 968         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 969                 if (reg == gen8_shadowed_regs[i])
 970                         return true;
 971
 972         return false;
 973 }
 974
 975 #define __gen8_write(x) \
 976 static void \
 977 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 978         REG_WRITE_HEADER; \
 979         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 980         if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
 981                 if (dev_priv->uncore.forcewake_count == 0) \
 982                         dev_priv->uncore.funcs.force_wake_get(dev_priv, \
 983                                                               FORCEWAKE_ALL); \
 984                 __raw_i915_write##x(dev_priv, reg, val); \
 985                 if (dev_priv->uncore.forcewake_count == 0) \
 986                         dev_priv->uncore.funcs.force_wake_put(dev_priv, \
 987                                                               FORCEWAKE_ALL); \
 988         } else { \
 989                 __raw_i915_write##x(dev_priv, reg, val); \
 990         } \
 991         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 992         hsw_unclaimed_reg_detect(dev_priv); \
 993         REG_WRITE_FOOTER; \
 994 }
 995
 996 #define __chv_write(x) \
 997 static void \
 998 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 999         unsigned fwengine = 0; \
1000         bool shadowed = is_gen8_shadowed(dev_priv, reg); \
1001         REG_WRITE_HEADER; \
1002         if (!shadowed) { \
1003                 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
1004                         if (dev_priv->uncore.fw_rendercount == 0) \
1005                                 fwengine = FORCEWAKE_RENDER; \
1006                 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
1007                         if (dev_priv->uncore.fw_mediacount == 0) \
1008                                 fwengine = FORCEWAKE_MEDIA; \
1009                 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
1010                         if (dev_priv->uncore.fw_rendercount == 0) \
1011                                 fwengine |= FORCEWAKE_RENDER; \
1012                         if (dev_priv->uncore.fw_mediacount == 0) \
1013                                 fwengine |= FORCEWAKE_MEDIA; \
1014                 } \
1015         } \
1016         if (fwengine) \
1017                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
1018         __raw_i915_write##x(dev_priv, reg, val); \
1019         if (fwengine) \
1020                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
1021         REG_WRITE_FOOTER; \
1022 }
1023
1024 static const u32 gen9_shadowed_regs[] = {
1025         RING_TAIL(RENDER_RING_BASE),
1026         RING_TAIL(GEN6_BSD_RING_BASE),
1027         RING_TAIL(VEBOX_RING_BASE),
1028         RING_TAIL(BLT_RING_BASE),
1029         FORCEWAKE_BLITTER_GEN9,
1030         FORCEWAKE_RENDER_GEN9,
1031         FORCEWAKE_MEDIA_GEN9,
1032         GEN6_RPNSWREQ,
1033         GEN6_RC_VIDEO_FREQ,
1034         /* TODO: Other registers are not yet used */
1035 };
1036
1037 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
1038 {
1039         int i;
1040         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
1041                 if (reg == gen9_shadowed_regs[i])
1042                         return true;
1043
1044         return false;
1045 }
1046
1047 #define __gen9_write(x) \
1048 static void \
1049 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
1050                 bool trace) { \
1051         REG_WRITE_HEADER; \
1052         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
1053                         is_gen9_shadowed(dev_priv, reg)) { \
1054                 __raw_i915_write##x(dev_priv, reg, val); \
1055         } else { \
1056                 unsigned fwengine = 0; \
1057                 if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
1058                         if (dev_priv->uncore.fw_rendercount == 0) \
1059                                 fwengine = FORCEWAKE_RENDER; \
1060                 } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
1061                         if (dev_priv->uncore.fw_mediacount == 0) \
1062                                 fwengine = FORCEWAKE_MEDIA; \
1063                 } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
1064                         if (dev_priv->uncore.fw_rendercount == 0) \
1065                                 fwengine |= FORCEWAKE_RENDER; \
1066                         if (dev_priv->uncore.fw_mediacount == 0) \
1067                                 fwengine |= FORCEWAKE_MEDIA; \
1068                 } else { \
1069                         if (dev_priv->uncore.fw_blittercount == 0) \
1070                                 fwengine = FORCEWAKE_BLITTER; \
1071                 } \
1072                 if (fwengine) \
1073                         dev_priv->uncore.funcs.force_wake_get(dev_priv, \
1074                                         fwengine); \
1075                 __raw_i915_write##x(dev_priv, reg, val); \
1076                 if (fwengine) \
1077                         dev_priv->uncore.funcs.force_wake_put(dev_priv, \
1078                                         fwengine); \
1079         } \
1080         REG_WRITE_FOOTER; \
1081 }
1082
1083 __gen9_write(8)
1084 __gen9_write(16)
1085 __gen9_write(32)
1086 __gen9_write(64)
1087 __chv_write(8)
1088 __chv_write(16)
1089 __chv_write(32)
1090 __chv_write(64)
1091 __gen8_write(8)
1092 __gen8_write(16)
1093 __gen8_write(32)
1094 __gen8_write(64)
1095 __hsw_write(8)
1096 __hsw_write(16)
1097 __hsw_write(32)
1098 __hsw_write(64)
1099 __gen6_write(8)
1100 __gen6_write(16)
1101 __gen6_write(32)
1102 __gen6_write(64)
1103 __gen5_write(8)
1104 __gen5_write(16)
1105 __gen5_write(32)
1106 __gen5_write(64)
1107 __gen4_write(8)
1108 __gen4_write(16)
1109 __gen4_write(32)
1110 __gen4_write(64)
1111
1112 #undef __gen9_write
1113 #undef __chv_write
1114 #undef __gen8_write
1115 #undef __hsw_write
1116 #undef __gen6_write
1117 #undef __gen5_write
1118 #undef __gen4_write
1119 #undef REG_WRITE_FOOTER
1120 #undef REG_WRITE_HEADER
1121
1122 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1123 do { \
1124         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1125         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1126         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1127         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1128 } while (0)
1129
1130 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1131 do { \
1132         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1133         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1134         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1135         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1136 } while (0)
1137
1138 void intel_uncore_init(struct drm_device *dev)
1139 {
1140         struct drm_i915_private *dev_priv = dev->dev_private;
1141
1142         setup_timer(&dev_priv->uncore.force_wake_timer,
1143                     gen6_force_wake_timer, (unsigned long)dev_priv);
1144
1145         __intel_uncore_early_sanitize(dev, false);
1146
1147         if (IS_GEN9(dev)) {
1148                 dev_priv->uncore.funcs.force_wake_get = __gen9_force_wake_get;
1149                 dev_priv->uncore.funcs.force_wake_put = __gen9_force_wake_put;
1150         } else if (IS_VALLEYVIEW(dev)) {
1151                 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
1152                 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
1153         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1154                 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
1155                 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
1156         } else if (IS_IVYBRIDGE(dev)) {
1157                 u32 ecobus;
1158
1159                 /* IVB configs may use multi-threaded forcewake */
1160
1161                 /* A small trick here - if the bios hasn't configured
1162                  * MT forcewake, and if the device is in RC6, then
1163                  * force_wake_mt_get will not wake the device and the
1164                  * ECOBUS read will return zero. Which will be
1165                  * (correctly) interpreted by the test below as MT
1166                  * forcewake being disabled.
1167                  */
1168                 mutex_lock(&dev->struct_mutex);
1169                 __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
1170                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1171                 __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
1172                 mutex_unlock(&dev->struct_mutex);
1173
1174                 if (ecobus & FORCEWAKE_MT_ENABLE) {
1175                         dev_priv->uncore.funcs.force_wake_get =
1176                                 __gen7_gt_force_wake_mt_get;
1177                         dev_priv->uncore.funcs.force_wake_put =
1178                                 __gen7_gt_force_wake_mt_put;
1179                 } else {
1180                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1181                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1182                         dev_priv->uncore.funcs.force_wake_get =
1183                                 __gen6_gt_force_wake_get;
1184                         dev_priv->uncore.funcs.force_wake_put =
1185                                 __gen6_gt_force_wake_put;
1186                 }
1187         } else if (IS_GEN6(dev)) {
1188                 dev_priv->uncore.funcs.force_wake_get =
1189                         __gen6_gt_force_wake_get;
1190                 dev_priv->uncore.funcs.force_wake_put =
1191                         __gen6_gt_force_wake_put;
1192         }
1193
1194         switch (INTEL_INFO(dev)->gen) {
1195         default:
1196                 MISSING_CASE(INTEL_INFO(dev)->gen);
1197                 return;
1198         case 9:
1199                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1200                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1201                 break;
1202         case 8:
1203                 if (IS_CHERRYVIEW(dev)) {
1204                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1205                         ASSIGN_READ_MMIO_VFUNCS(chv);
1206
1207                 } else {
1208                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1209                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1210                 }
1211                 break;
1212         case 7:
1213         case 6:
1214                 if (IS_HASWELL(dev)) {
1215                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1216                 } else {
1217                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1218                 }
1219
1220                 if (IS_VALLEYVIEW(dev)) {
1221                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1222                 } else {
1223                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1224                 }
1225                 break;
1226         case 5:
1227                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1228                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1229                 break;
1230         case 4:
1231         case 3:
1232         case 2:
1233                 ASSIGN_WRITE_MMIO_VFUNCS(gen4);
1234                 ASSIGN_READ_MMIO_VFUNCS(gen4);
1235                 break;
1236         }
1237
1238         i915_check_and_clear_faults(dev);
1239 }
1240 #undef ASSIGN_WRITE_MMIO_VFUNCS
1241 #undef ASSIGN_READ_MMIO_VFUNCS
1242
1243 void intel_uncore_fini(struct drm_device *dev)
1244 {
1245         /* Paranoia: make sure we have disabled everything before we exit. */
1246         intel_uncore_sanitize(dev);
1247         intel_uncore_forcewake_reset(dev, false);
1248 }
1249
1250 #define GEN_RANGE(l, h) GENMASK(h, l)
1251
1252 static const struct register_whitelist {
1253         uint64_t offset;
1254         uint32_t size;
1255         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1256         uint32_t gen_bitmask;
1257 } whitelist[] = {
1258         { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1259 };
1260
1261 int i915_reg_read_ioctl(struct drm_device *dev,
1262                         void *data, struct drm_file *file)
1263 {
1264         struct drm_i915_private *dev_priv = dev->dev_private;
1265         struct drm_i915_reg_read *reg = data;
1266         struct register_whitelist const *entry = whitelist;
1267         int i, ret = 0;
1268
1269         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1270                 if (entry->offset == reg->offset &&
1271                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1272                         break;
1273         }
1274
1275         if (i == ARRAY_SIZE(whitelist))
1276                 return -EINVAL;
1277
1278         intel_runtime_pm_get(dev_priv);
1279
1280         switch (entry->size) {
1281         case 8:
1282                 reg->val = I915_READ64(reg->offset);
1283                 break;
1284         case 4:
1285                 reg->val = I915_READ(reg->offset);
1286                 break;
1287         case 2:
1288                 reg->val = I915_READ16(reg->offset);
1289                 break;
1290         case 1:
1291                 reg->val = I915_READ8(reg->offset);
1292                 break;
1293         default:
1294                 MISSING_CASE(entry->size);
1295                 ret = -EINVAL;
1296                 goto out;
1297         }
1298
1299 out:
1300         intel_runtime_pm_put(dev_priv);
1301         return ret;
1302 }
1303
1304 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1305                                void *data, struct drm_file *file)
1306 {
1307         struct drm_i915_private *dev_priv = dev->dev_private;
1308         struct drm_i915_reset_stats *args = data;
1309         struct i915_ctx_hang_stats *hs;
1310         struct intel_context *ctx;
1311         int ret;
1312
1313         if (args->flags || args->pad)
1314                 return -EINVAL;
1315
1316         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1317                 return -EPERM;
1318
1319         ret = mutex_lock_interruptible(&dev->struct_mutex);
1320         if (ret)
1321                 return ret;
1322
1323         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1324         if (IS_ERR(ctx)) {
1325                 mutex_unlock(&dev->struct_mutex);
1326                 return PTR_ERR(ctx);
1327         }
1328         hs = &ctx->hang_stats;
1329
1330         if (capable(CAP_SYS_ADMIN))
1331                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1332         else
1333                 args->reset_count = 0;
1334
1335         args->batch_active = hs->batch_active;
1336         args->batch_pending = hs->batch_pending;
1337
1338         mutex_unlock(&dev->struct_mutex);
1339
1340         return 0;
1341 }
1342
1343 static int i915_reset_complete(struct drm_device *dev)
1344 {
1345         u8 gdrst;
1346         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1347         return (gdrst & GRDOM_RESET_STATUS) == 0;
1348 }
1349
1350 static int i915_do_reset(struct drm_device *dev)
1351 {
1352         /* assert reset for at least 20 usec */
1353         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1354         udelay(20);
1355         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1356
1357         return wait_for(i915_reset_complete(dev), 500);
1358 }
1359
1360 static int g4x_reset_complete(struct drm_device *dev)
1361 {
1362         u8 gdrst;
1363         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1364         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1365 }
1366
1367 static int g33_do_reset(struct drm_device *dev)
1368 {
1369         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1370         return wait_for(g4x_reset_complete(dev), 500);
1371 }
1372
1373 static int g4x_do_reset(struct drm_device *dev)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         int ret;
1377
1378         pci_write_config_byte(dev->pdev, I915_GDRST,
1379                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1380         ret =  wait_for(g4x_reset_complete(dev), 500);
1381         if (ret)
1382                 return ret;
1383
1384         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1385         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1386         POSTING_READ(VDECCLK_GATE_D);
1387
1388         pci_write_config_byte(dev->pdev, I915_GDRST,
1389                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1390         ret =  wait_for(g4x_reset_complete(dev), 500);
1391         if (ret)
1392                 return ret;
1393
1394         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1395         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1396         POSTING_READ(VDECCLK_GATE_D);
1397
1398         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1399
1400         return 0;
1401 }
1402
1403 static int ironlake_do_reset(struct drm_device *dev)
1404 {
1405         struct drm_i915_private *dev_priv = dev->dev_private;
1406         int ret;
1407
1408         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1409                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1410         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1411                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1412         if (ret)
1413                 return ret;
1414
1415         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1416                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1417         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1418                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1419         if (ret)
1420                 return ret;
1421
1422         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1423
1424         return 0;
1425 }
1426
1427 static int gen6_do_reset(struct drm_device *dev)
1428 {
1429         struct drm_i915_private *dev_priv = dev->dev_private;
1430         int     ret;
1431
1432         /* Reset the chip */
1433
1434         /* GEN6_GDRST is not in the gt power well, no need to check
1435          * for fifo space for the write or forcewake the chip for
1436          * the read
1437          */
1438         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1439
1440         /* Spin waiting for the device to ack the reset request */
1441         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1442
1443         intel_uncore_forcewake_reset(dev, true);
1444
1445         return ret;
1446 }
1447
1448 int intel_gpu_reset(struct drm_device *dev)
1449 {
1450         if (INTEL_INFO(dev)->gen >= 6)
1451                 return gen6_do_reset(dev);
1452         else if (IS_GEN5(dev))
1453                 return ironlake_do_reset(dev);
1454         else if (IS_G4X(dev))
1455                 return g4x_do_reset(dev);
1456         else if (IS_G33(dev))
1457                 return g33_do_reset(dev);
1458         else if (INTEL_INFO(dev)->gen >= 3)
1459                 return i915_do_reset(dev);
1460         else
1461                 return -ENODEV;
1462 }
1463
1464 void intel_uncore_check_errors(struct drm_device *dev)
1465 {
1466         struct drm_i915_private *dev_priv = dev->dev_private;
1467
1468         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1469             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1470                 DRM_ERROR("Unclaimed register before interrupt\n");
1471                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1472         }
1473 }