2 * Copyright © 2006-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Eric Anholt <eric@anholt.net>
29 * This information is private to VBT parsing in intel_bios.c.
31 * Please do NOT include anywhere else.
33 #ifndef _INTEL_BIOS_PRIVATE
34 #error "intel_vbt_defs.h is private to intel_bios.c"
37 #ifndef _INTEL_VBT_DEFS_H_
38 #define _INTEL_VBT_DEFS_H_
40 #include "intel_bios.h"
43 * struct vbt_header - VBT Header structure
44 * @signature: VBT signature, always starts with "$VBT"
45 * @version: Version of this structure
46 * @header_size: Size of this structure
47 * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks)
48 * @vbt_checksum: Checksum
49 * @reserved0: Reserved
50 * @bdb_offset: Offset of &struct bdb_header from beginning of VBT
51 * @aim_offset: Offsets of add-in data blocks from beginning of VBT
65 * struct bdb_header - BDB Header structure
66 * @signature: BDB signature "BIOS_DATA_BLOCK"
67 * @version: Version of the data block definitions
68 * @header_size: Size of this structure
69 * @bdb_size: Size of BDB (BDB Header and data blocks)
78 /* strictly speaking, this is a "skip" block, but it has interesting info */
80 u8 type
; /* 0 == desktop, 1 == mobile */
85 u8 rsvd2
:6; /* finish byte */
92 u8 rsvd4
; /* popup memory size */
94 u8 rsvd5
; /* is crt already on ddc2 */
98 * There are several types of BIOS data blocks (BDBs), each block has
99 * an ID and size in the first 3 bytes (ID in first, size in next 2).
100 * Known types are listed below.
102 #define BDB_GENERAL_FEATURES 1
103 #define BDB_GENERAL_DEFINITIONS 2
104 #define BDB_OLD_TOGGLE_LIST 3
105 #define BDB_MODE_SUPPORT_LIST 4
106 #define BDB_GENERIC_MODE_TABLE 5
107 #define BDB_EXT_MMIO_REGS 6
109 #define BDB_SWF_MMIO 8
111 #define BDB_MODE_REMOVAL_TABLE 10
112 #define BDB_CHILD_DEVICE_TABLE 11
113 #define BDB_DRIVER_FEATURES 12
114 #define BDB_DRIVER_PERSISTENCE 13
115 #define BDB_EXT_TABLE_PTRS 14
116 #define BDB_DOT_CLOCK_OVERRIDE 15
117 #define BDB_DISPLAY_SELECT 16
119 #define BDB_DRIVER_ROTATION 18
120 #define BDB_DISPLAY_REMOVE 19
121 #define BDB_OEM_CUSTOM 20
122 #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
123 #define BDB_SDVO_LVDS_OPTIONS 22
124 #define BDB_SDVO_PANEL_DTDS 23
125 #define BDB_SDVO_LVDS_PNP_IDS 24
126 #define BDB_SDVO_LVDS_POWER_SEQ 25
127 #define BDB_TV_OPTIONS 26
129 #define BDB_LVDS_OPTIONS 40
130 #define BDB_LVDS_LFP_DATA_PTRS 41
131 #define BDB_LVDS_LFP_DATA 42
132 #define BDB_LVDS_BACKLIGHT 43
133 #define BDB_LVDS_POWER 44
134 #define BDB_MIPI_CONFIG 52
135 #define BDB_MIPI_SEQUENCE 53
136 #define BDB_SKIP 254 /* VBIOS private block, ignore */
138 struct bdb_general_features
{
147 u8 download_ext_vbt
:1;
150 u8 enable_lfp_on_override
:1;
151 u8 disable_ssc_ddt
:1;
153 u8 display_clock_mode
:1;
154 u8 rsvd8
:1; /* finish byte */
157 u8 disable_smooth_vision
:1;
160 u8 fdi_rx_polarity_inverted
:1;
161 u8 rsvd10
:4; /* finish byte */
164 u8 legacy_monitor_detect
;
167 u8 int_crt_support
:1;
169 u8 int_efp_support
:1;
170 u8 dp_ssc_enb
:1; /* PCH attached eDP supports SSC */
171 u8 dp_ssc_freq
:1; /* SSC freq for PCH attached eDP */
172 u8 rsvd11
:3; /* finish byte */
176 #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
177 #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
178 #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
179 #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
182 #define DEVICE_TYPE_NONE 0x00
183 #define DEVICE_TYPE_CRT 0x01
184 #define DEVICE_TYPE_TV 0x09
185 #define DEVICE_TYPE_EFP 0x12
186 #define DEVICE_TYPE_LFP 0x22
188 #define DEVICE_TYPE_CRT_DPMS 0x6001
189 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
190 #define DEVICE_TYPE_TV_COMPOSITE 0x0209
191 #define DEVICE_TYPE_TV_MACROVISION 0x0289
192 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
193 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
194 #define DEVICE_TYPE_TV_SCART 0x0209
195 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
196 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
197 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
198 #define DEVICE_TYPE_EFP_DVI_I 0x6053
199 #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
200 #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
201 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
202 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
203 #define DEVICE_TYPE_LFP_PANELLINK 0x5012
204 #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
205 #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
206 #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
207 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
209 #define DEVICE_CFG_NONE 0x00
210 #define DEVICE_CFG_12BIT_DVOB 0x01
211 #define DEVICE_CFG_12BIT_DVOC 0x02
212 #define DEVICE_CFG_24BIT_DVOBC 0x09
213 #define DEVICE_CFG_24BIT_DVOCB 0x0a
214 #define DEVICE_CFG_DUAL_DVOB 0x11
215 #define DEVICE_CFG_DUAL_DVOC 0x12
216 #define DEVICE_CFG_DUAL_DVOBC 0x13
217 #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
218 #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
220 #define DEVICE_WIRE_NONE 0x00
221 #define DEVICE_WIRE_DVOB 0x01
222 #define DEVICE_WIRE_DVOC 0x02
223 #define DEVICE_WIRE_DVOBC 0x03
224 #define DEVICE_WIRE_DVOBB 0x05
225 #define DEVICE_WIRE_DVOCC 0x06
226 #define DEVICE_WIRE_DVOB_MASTER 0x0d
227 #define DEVICE_WIRE_DVOC_MASTER 0x0e
229 #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
230 #define DEVICE_PORT_DVOB 0x01
231 #define DEVICE_PORT_DVOC 0x02
234 * We used to keep this struct but without any version control. We should avoid
235 * using it in the future, but it should be safe to keep using it in the old
236 * code. Do not change; we rely on its size.
238 struct old_child_dev_config
{
241 u8 device_id
[10]; /* ascii string */
243 u8 dvo_port
; /* See Device_PORT_* above */
248 u8 dvo_cfg
; /* See DEVICE_CFG_* above */
254 u8 dvo_wiring
;/* See DEVICE_WIRE_* above */
260 /* This one contains field offsets that are known to be common for all BDB
261 * versions. Notice that the meaning of the contents contents may still change,
262 * but at least the offsets are consistent. */
264 struct common_child_dev_config
{
272 u8 dvo_cfg
; /* See DEVICE_CFG_* above */
282 u8 support_reserved
:5;
288 /* This field changes depending on the BDB version, so the most reliable way to
289 * read it is by checking the BDB version and reading the raw pointer. */
290 union child_device_config
{
291 /* This one is safe to be used anywhere, but the code should still check
292 * the BDB version. */
294 /* This one should only be kept for legacy code. */
295 struct old_child_dev_config old
;
296 /* This one should also be safe to use anywhere, even without version
298 struct common_child_dev_config common
;
301 struct bdb_general_definitions
{
303 u8 crt_ddc_gmbus_pin
;
307 u8 skip_boot_crt_detect
:1;
309 u8 rsvd1
:5; /* finish byte */
311 /* boot device bits */
317 * If TV is present, it'll be at devices[0].
318 * LVDS will be next, either devices[0] or [1], if present.
319 * On some platforms the number of device is 6. But could be as few as
320 * 4 if both TV and LVDS are missing.
321 * And the device num is related with the size of general definition
322 * block. It is obtained by using the following formula:
323 * number = (block_size - sizeof(bdb_general_definitions))/
324 * defs->child_dev_size;
329 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
330 #define MODE_MASK 0x3
332 struct bdb_lvds_options
{
335 /* LVDS capabilities, stored in a dword */
337 u8 pfit_text_mode_enhanced
:1;
338 u8 pfit_gfx_mode_enhanced
:1;
339 u8 pfit_ratio_auto
:1;
344 /* LVDS Panel channel bits stored here */
345 u32 lvds_panel_channel_bits
;
346 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
350 /* Panel color depth defined here */
351 u16 panel_color_depth
;
352 /* LVDS panel type bits stored here */
353 u32 dps_panel_type_bits
;
354 /* LVDS backlight control type bits stored here */
355 u32 blt_control_type_bits
;
358 /* LFP pointer table contains entries to the struct below */
359 struct bdb_lvds_lfp_data_ptr
{
360 u16 fp_timing_offset
; /* offsets are from start of bdb */
362 u16 dvo_timing_offset
;
364 u16 panel_pnp_id_offset
;
368 struct bdb_lvds_lfp_data_ptrs
{
369 u8 lvds_entries
; /* followed by one or more lvds_data_ptr structs */
370 struct bdb_lvds_lfp_data_ptr ptr
[16];
373 /* LFP data has 3 blocks per entry */
374 struct lvds_fp_timing
{
384 u32 pp_cycle_reg_val
;
390 struct lvds_dvo_timing
{
391 u16 clock
; /**< In 10khz */
401 u8 hsync_pulse_width
;
402 u8 vsync_pulse_width
:4;
426 struct bdb_lvds_lfp_data_entry
{
427 struct lvds_fp_timing fp_timing
;
428 struct lvds_dvo_timing dvo_timing
;
429 struct lvds_pnp_id pnp_id
;
432 struct bdb_lvds_lfp_data
{
433 struct bdb_lvds_lfp_data_entry data
[16];
436 #define BDB_BACKLIGHT_TYPE_NONE 0
437 #define BDB_BACKLIGHT_TYPE_PWM 2
439 struct bdb_lfp_backlight_data_entry
{
449 struct bdb_lfp_backlight_data
{
451 struct bdb_lfp_backlight_data_entry data
[16];
455 struct aimdb_header
{
459 u16 aimdb_header_size
;
468 struct vch_panel_data
{
469 u16 fp_timing_offset
;
471 u16 dvo_timing_offset
;
473 u16 text_fitting_offset
;
474 u8 text_fitting_size
;
475 u16 graphics_fitting_offset
;
476 u8 graphics_fitting_size
;
480 struct aimdb_block aimdb_block
;
481 struct vch_panel_data panels
[16];
484 struct bdb_sdvo_lvds_options
{
486 u8 h40_set_panel_type
;
491 u8 sclalarcoeff_tab_row_num
;
492 u8 sclalarcoeff_tab_row_size
;
494 u8 panel_misc_bits_1
;
495 u8 panel_misc_bits_2
;
496 u8 panel_misc_bits_3
;
497 u8 panel_misc_bits_4
;
501 #define BDB_DRIVER_FEATURE_NO_LVDS 0
502 #define BDB_DRIVER_FEATURE_INT_LVDS 1
503 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2
504 #define BDB_DRIVER_FEATURE_EDP 3
506 struct bdb_driver_features
{
507 u8 boot_dev_algorithm
:1;
508 u8 block_display_switch
:1;
509 u8 allow_display_switch
:1;
513 u8 sprite_in_clone
:1;
519 u8 boot_mode_refresh
;
521 u16 enable_lfp_primary
:1;
522 u16 selective_mode_pruning
:1;
523 u16 dual_frequency
:1;
524 u16 render_clock_freq
:1; /* 0: high freq; 1: low freq */
525 u16 nt_clone_support
:1;
526 u16 power_scheme_ui
:1; /* 0: CUI; 1: 3rd party */
527 u16 sprite_display_assign
:1; /* 0: secondary; 1: primary */
528 u16 cui_aspect_scaling
:1;
529 u16 preserve_aspect_ratio
:1;
530 u16 sdvo_device_power_down
:1;
538 u16 legacy_crt_max_x
;
539 u16 legacy_crt_max_y
;
540 u8 legacy_crt_max_refresh
;
543 u8 custom_vbt_version
;
544 /* Driver features data block */
548 u16 bltclt_enabled
:1;
557 u16 pc_feature_valid
:1;
563 #define EDP_RATE_1_62 0
564 #define EDP_RATE_2_7 1
568 #define EDP_PREEMPHASIS_NONE 0
569 #define EDP_PREEMPHASIS_3_5dB 1
570 #define EDP_PREEMPHASIS_6dB 2
571 #define EDP_PREEMPHASIS_9_5dB 3
572 #define EDP_VSWING_0_4V 0
573 #define EDP_VSWING_0_6V 1
574 #define EDP_VSWING_0_8V 2
575 #define EDP_VSWING_1_2V 3
578 struct edp_link_params
{
586 struct edp_power_seq power_seqs
[16];
588 struct edp_link_params link_params
[16];
589 u32 sdrrs_msa_timing_delay
;
591 /* ith bit indicates enabled/disabled for (i+1)th panel */
593 u16 edp_t3_optimization
;
594 u64 edp_vswing_preemph
; /* v173 */
600 u8 require_aux_to_wakeup
:1;
601 u8 feature_bits_rsvd
:6;
606 u8 wait_times_rsvd
:1;
608 /* TP wake up time in multiple of 100 */
610 u16 tp2_tp3_wakeup_time
;
614 struct psr_table psr_table
[16];
618 * Driver<->VBIOS interaction occurs through scratch bits in
622 /* GR18 bits are set on display switch and hotkey events */
623 #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
624 #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
625 #define GR18_HK_NONE (0x0<<3)
626 #define GR18_HK_LFP_STRETCH (0x1<<3)
627 #define GR18_HK_TOGGLE_DISP (0x2<<3)
628 #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
629 #define GR18_HK_POPUP_DISABLED (0x6<<3)
630 #define GR18_HK_POPUP_ENABLED (0x7<<3)
631 #define GR18_HK_PFIT (0x8<<3)
632 #define GR18_HK_APM_CHANGE (0xa<<3)
633 #define GR18_HK_MULTIPLE (0xc<<3)
634 #define GR18_USER_INT_EN (1<<2)
635 #define GR18_A0000_FLUSH_EN (1<<1)
636 #define GR18_SMM_EN (1<<0)
638 /* Set by driver, cleared by VBIOS */
639 #define SWF00_YRES_SHIFT 16
640 #define SWF00_XRES_SHIFT 0
641 #define SWF00_RES_MASK 0xffff
643 /* Set by VBIOS at boot time and driver at runtime */
644 #define SWF01_TV2_FORMAT_SHIFT 8
645 #define SWF01_TV1_FORMAT_SHIFT 0
646 #define SWF01_TV_FORMAT_MASK 0xffff
648 #define SWF10_VBIOS_BLC_I2C_EN (1<<29)
649 #define SWF10_GTT_OVERRIDE_EN (1<<28)
650 #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
651 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
652 #define SWF10_OLD_TOGGLE 0x0
653 #define SWF10_TOGGLE_LIST_1 0x1
654 #define SWF10_TOGGLE_LIST_2 0x2
655 #define SWF10_TOGGLE_LIST_3 0x3
656 #define SWF10_TOGGLE_LIST_4 0x4
657 #define SWF10_PANNING_EN (1<<23)
658 #define SWF10_DRIVER_LOADED (1<<22)
659 #define SWF10_EXTENDED_DESKTOP (1<<21)
660 #define SWF10_EXCLUSIVE_MODE (1<<20)
661 #define SWF10_OVERLAY_EN (1<<19)
662 #define SWF10_PLANEB_HOLDOFF (1<<18)
663 #define SWF10_PLANEA_HOLDOFF (1<<17)
664 #define SWF10_VGA_HOLDOFF (1<<16)
665 #define SWF10_ACTIVE_DISP_MASK 0xffff
666 #define SWF10_PIPEB_LFP2 (1<<15)
667 #define SWF10_PIPEB_EFP2 (1<<14)
668 #define SWF10_PIPEB_TV2 (1<<13)
669 #define SWF10_PIPEB_CRT2 (1<<12)
670 #define SWF10_PIPEB_LFP (1<<11)
671 #define SWF10_PIPEB_EFP (1<<10)
672 #define SWF10_PIPEB_TV (1<<9)
673 #define SWF10_PIPEB_CRT (1<<8)
674 #define SWF10_PIPEA_LFP2 (1<<7)
675 #define SWF10_PIPEA_EFP2 (1<<6)
676 #define SWF10_PIPEA_TV2 (1<<5)
677 #define SWF10_PIPEA_CRT2 (1<<4)
678 #define SWF10_PIPEA_LFP (1<<3)
679 #define SWF10_PIPEA_EFP (1<<2)
680 #define SWF10_PIPEA_TV (1<<1)
681 #define SWF10_PIPEA_CRT (1<<0)
683 #define SWF11_MEMORY_SIZE_SHIFT 16
684 #define SWF11_SV_TEST_EN (1<<15)
685 #define SWF11_IS_AGP (1<<14)
686 #define SWF11_DISPLAY_HOLDOFF (1<<13)
687 #define SWF11_DPMS_REDUCED (1<<12)
688 #define SWF11_IS_VBE_MODE (1<<11)
689 #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
690 #define SWF11_DPMS_MASK 0x07
691 #define SWF11_DPMS_OFF (1<<2)
692 #define SWF11_DPMS_SUSPEND (1<<1)
693 #define SWF11_DPMS_STANDBY (1<<0)
694 #define SWF11_DPMS_ON 0
696 #define SWF14_GFX_PFIT_EN (1<<31)
697 #define SWF14_TEXT_PFIT_EN (1<<30)
698 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
699 #define SWF14_POPUP_EN (1<<28)
700 #define SWF14_DISPLAY_HOLDOFF (1<<27)
701 #define SWF14_DISP_DETECT_EN (1<<26)
702 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
703 #define SWF14_DRIVER_STATUS (1<<24)
704 #define SWF14_OS_TYPE_WIN9X (1<<23)
705 #define SWF14_OS_TYPE_WINNT (1<<22)
707 #define SWF14_PM_TYPE_MASK 0x00070000
708 #define SWF14_PM_ACPI_VIDEO (0x4 << 16)
709 #define SWF14_PM_ACPI (0x3 << 16)
710 #define SWF14_PM_APM_12 (0x2 << 16)
711 #define SWF14_PM_APM_11 (0x1 << 16)
712 #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
713 /* if GR18 indicates a display switch */
714 #define SWF14_DS_PIPEB_LFP2_EN (1<<15)
715 #define SWF14_DS_PIPEB_EFP2_EN (1<<14)
716 #define SWF14_DS_PIPEB_TV2_EN (1<<13)
717 #define SWF14_DS_PIPEB_CRT2_EN (1<<12)
718 #define SWF14_DS_PIPEB_LFP_EN (1<<11)
719 #define SWF14_DS_PIPEB_EFP_EN (1<<10)
720 #define SWF14_DS_PIPEB_TV_EN (1<<9)
721 #define SWF14_DS_PIPEB_CRT_EN (1<<8)
722 #define SWF14_DS_PIPEA_LFP2_EN (1<<7)
723 #define SWF14_DS_PIPEA_EFP2_EN (1<<6)
724 #define SWF14_DS_PIPEA_TV2_EN (1<<5)
725 #define SWF14_DS_PIPEA_CRT2_EN (1<<4)
726 #define SWF14_DS_PIPEA_LFP_EN (1<<3)
727 #define SWF14_DS_PIPEA_EFP_EN (1<<2)
728 #define SWF14_DS_PIPEA_TV_EN (1<<1)
729 #define SWF14_DS_PIPEA_CRT_EN (1<<0)
730 /* if GR18 indicates a panel fitting request */
731 #define SWF14_PFIT_EN (1<<0) /* 0 means disable */
732 /* if GR18 indicates an APM change request */
733 #define SWF14_APM_HIBERNATE 0x4
734 #define SWF14_APM_SUSPEND 0x3
735 #define SWF14_APM_STANDBY 0x1
736 #define SWF14_APM_RESTORE 0x0
738 /* Add the device class for LFP, TV, HDMI */
739 #define DEVICE_TYPE_INT_LFP 0x1022
740 #define DEVICE_TYPE_INT_TV 0x1009
741 #define DEVICE_TYPE_HDMI 0x60D2
742 #define DEVICE_TYPE_DP 0x68C6
743 #define DEVICE_TYPE_eDP 0x78C6
745 #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15)
746 #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14)
747 #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13)
748 #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
749 #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11)
750 #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10)
751 #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9)
752 #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8)
753 #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6)
754 #define DEVICE_TYPE_LVDS_SINGALING (1 << 5)
755 #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
756 #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3)
757 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
758 #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
759 #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
762 * Bits we care about when checking for DEVICE_TYPE_eDP
763 * Depending on the system, the other bits may or may not
764 * be set for eDP outputs.
766 #define DEVICE_TYPE_eDP_BITS \
767 (DEVICE_TYPE_INTERNAL_CONNECTOR | \
768 DEVICE_TYPE_MIPI_OUTPUT | \
769 DEVICE_TYPE_COMPOSITE_OUTPUT | \
770 DEVICE_TYPE_DUAL_CHANNEL | \
771 DEVICE_TYPE_LVDS_SINGALING | \
772 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
773 DEVICE_TYPE_VIDEO_SIGNALING | \
774 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
775 DEVICE_TYPE_ANALOG_OUTPUT)
777 /* define the DVO port for HDMI output type */
782 /* Possible values for the "DVO Port" field for versions >= 155: */
783 #define DVO_PORT_HDMIA 0
784 #define DVO_PORT_HDMIB 1
785 #define DVO_PORT_HDMIC 2
786 #define DVO_PORT_HDMID 3
787 #define DVO_PORT_LVDS 4
788 #define DVO_PORT_TV 5
789 #define DVO_PORT_CRT 6
790 #define DVO_PORT_DPB 7
791 #define DVO_PORT_DPC 8
792 #define DVO_PORT_DPD 9
793 #define DVO_PORT_DPA 10
794 #define DVO_PORT_DPE 11
795 #define DVO_PORT_HDMIE 12
796 #define DVO_PORT_MIPIA 21
797 #define DVO_PORT_MIPIB 22
798 #define DVO_PORT_MIPIC 23
799 #define DVO_PORT_MIPID 24
801 /* Block 52 contains MIPI configuration block
802 * 6 * bdb_mipi_config, followed by 6 pps data block
805 #define MAX_MIPI_CONFIGURATIONS 6
807 struct bdb_mipi_config
{
808 struct mipi_config config
[MAX_MIPI_CONFIGURATIONS
];
809 struct mipi_pps_data pps
[MAX_MIPI_CONFIGURATIONS
];
812 /* Block 53 contains MIPI sequences as needed by the panel
813 * for enabling it. This block can be variable in size and
814 * can be maximum of 6 blocks
816 struct bdb_mipi_sequence
{
821 enum mipi_gpio_pin_index
{
822 MIPI_GPIO_UNDEFINED
= 0,
823 MIPI_GPIO_PANEL_ENABLE
,
825 MIPI_GPIO_PWM_ENABLE
,
827 MIPI_GPIO_PWR_DOWN_R
,
828 MIPI_GPIO_STDBY_RST_N
,
832 #endif /* _INTEL_VBT_DEFS_H_ */