drm/imx: store internal bus configuration in crtc state
[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-crtc.c
1 /*
2 * i.MX IPUv3 Graphics driver
3 *
4 * Copyright (C) 2011 Sascha Hauer, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/component.h>
16 #include <linux/module.h>
17 #include <linux/export.h>
18 #include <linux/device.h>
19 #include <linux/platform_device.h>
20 #include <drm/drmP.h>
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_crtc_helper.h>
24 #include <linux/fb.h>
25 #include <linux/clk.h>
26 #include <linux/errno.h>
27 #include <drm/drm_gem_cma_helper.h>
28 #include <drm/drm_fb_cma_helper.h>
29
30 #include <video/imx-ipu-v3.h>
31 #include "imx-drm.h"
32 #include "ipuv3-plane.h"
33
34 #define DRIVER_DESC "i.MX IPUv3 Graphics"
35
36 struct ipu_crtc {
37 struct device *dev;
38 struct drm_crtc base;
39 struct imx_drm_crtc *imx_crtc;
40
41 /* plane[0] is the full plane, plane[1] is the partial plane */
42 struct ipu_plane *plane[2];
43
44 struct ipu_dc *dc;
45 struct ipu_di *di;
46 int irq;
47 };
48
49 #define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)
50
51 static void ipu_crtc_enable(struct drm_crtc *crtc)
52 {
53 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
54 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
55
56 ipu_dc_enable(ipu);
57 ipu_dc_enable_channel(ipu_crtc->dc);
58 ipu_di_enable(ipu_crtc->di);
59 }
60
61 static void ipu_crtc_disable(struct drm_crtc *crtc)
62 {
63 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
64 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
65
66 ipu_dc_disable_channel(ipu_crtc->dc);
67 ipu_di_disable(ipu_crtc->di);
68 ipu_dc_disable(ipu);
69
70 spin_lock_irq(&crtc->dev->event_lock);
71 if (crtc->state->event) {
72 drm_crtc_send_vblank_event(crtc, crtc->state->event);
73 crtc->state->event = NULL;
74 }
75 spin_unlock_irq(&crtc->dev->event_lock);
76 }
77
78 static void imx_drm_crtc_reset(struct drm_crtc *crtc)
79 {
80 struct imx_crtc_state *state;
81
82 if (crtc->state) {
83 if (crtc->state->mode_blob)
84 drm_property_unreference_blob(crtc->state->mode_blob);
85
86 state = to_imx_crtc_state(crtc->state);
87 memset(state, 0, sizeof(*state));
88 } else {
89 state = kzalloc(sizeof(*state), GFP_KERNEL);
90 if (!state)
91 return;
92 crtc->state = &state->base;
93 }
94
95 state->base.crtc = crtc;
96 }
97
98 static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
99 {
100 struct imx_crtc_state *state;
101
102 state = kzalloc(sizeof(*state), GFP_KERNEL);
103 if (!state)
104 return NULL;
105
106 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
107
108 WARN_ON(state->base.crtc != crtc);
109 state->base.crtc = crtc;
110
111 return &state->base;
112 }
113
114 static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
115 struct drm_crtc_state *state)
116 {
117 __drm_atomic_helper_crtc_destroy_state(state);
118 kfree(to_imx_crtc_state(state));
119 }
120
121 static const struct drm_crtc_funcs ipu_crtc_funcs = {
122 .set_config = drm_atomic_helper_set_config,
123 .destroy = drm_crtc_cleanup,
124 .page_flip = drm_atomic_helper_page_flip,
125 .reset = imx_drm_crtc_reset,
126 .atomic_duplicate_state = imx_drm_crtc_duplicate_state,
127 .atomic_destroy_state = imx_drm_crtc_destroy_state,
128 };
129
130 static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
131 {
132 struct ipu_crtc *ipu_crtc = dev_id;
133
134 imx_drm_handle_vblank(ipu_crtc->imx_crtc);
135
136 return IRQ_HANDLED;
137 }
138
139 static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
140 const struct drm_display_mode *mode,
141 struct drm_display_mode *adjusted_mode)
142 {
143 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
144 struct videomode vm;
145 int ret;
146
147 drm_display_mode_to_videomode(adjusted_mode, &vm);
148
149 ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
150 if (ret)
151 return false;
152
153 if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
154 return false;
155
156 drm_display_mode_from_videomode(&vm, adjusted_mode);
157
158 return true;
159 }
160
161 static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
162 struct drm_crtc_state *state)
163 {
164 u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);
165
166 if (state->active && (primary_plane_mask & state->plane_mask) == 0)
167 return -EINVAL;
168
169 return 0;
170 }
171
172 static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
173 struct drm_crtc_state *old_crtc_state)
174 {
175 spin_lock_irq(&crtc->dev->event_lock);
176 if (crtc->state->event) {
177 WARN_ON(drm_crtc_vblank_get(crtc));
178 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
179 crtc->state->event = NULL;
180 }
181 spin_unlock_irq(&crtc->dev->event_lock);
182 }
183
184 static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
185 {
186 struct drm_device *dev = crtc->dev;
187 struct drm_encoder *encoder;
188 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
189 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
190 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
191 struct ipu_di_signal_cfg sig_cfg = {};
192 unsigned long encoder_types = 0;
193
194 dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
195 mode->hdisplay);
196 dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
197 mode->vdisplay);
198
199 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
200 if (encoder->crtc == crtc)
201 encoder_types |= BIT(encoder->encoder_type);
202 }
203
204 dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
205 __func__, encoder_types);
206
207 /*
208 * If we have DAC or LDB, then we need the IPU DI clock to be
209 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
210 * clock from 27 MHz TVE_DI clock, but allow to divide it.
211 */
212 if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
213 BIT(DRM_MODE_ENCODER_LVDS)))
214 sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
215 else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
216 sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
217 else
218 sig_cfg.clkflags = 0;
219
220 sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
221 /* Default to driving pixel data on negative clock edges */
222 sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
223 DRM_BUS_FLAG_PIXDATA_POSEDGE);
224 sig_cfg.bus_format = imx_crtc_state->bus_format;
225 sig_cfg.v_to_h_sync = 0;
226 sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
227 sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
228
229 drm_display_mode_to_videomode(mode, &sig_cfg.mode);
230
231 ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
232 mode->flags & DRM_MODE_FLAG_INTERLACE,
233 imx_crtc_state->bus_format, mode->hdisplay);
234 ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
235 }
236
237 static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
238 .mode_fixup = ipu_crtc_mode_fixup,
239 .mode_set_nofb = ipu_crtc_mode_set_nofb,
240 .atomic_check = ipu_crtc_atomic_check,
241 .atomic_begin = ipu_crtc_atomic_begin,
242 .disable = ipu_crtc_disable,
243 .enable = ipu_crtc_enable,
244 };
245
246 static int ipu_enable_vblank(struct drm_crtc *crtc)
247 {
248 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
249
250 enable_irq(ipu_crtc->irq);
251
252 return 0;
253 }
254
255 static void ipu_disable_vblank(struct drm_crtc *crtc)
256 {
257 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
258
259 disable_irq_nosync(ipu_crtc->irq);
260 }
261
262 static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
263 .enable_vblank = ipu_enable_vblank,
264 .disable_vblank = ipu_disable_vblank,
265 .crtc_funcs = &ipu_crtc_funcs,
266 .crtc_helper_funcs = &ipu_helper_funcs,
267 };
268
269 static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
270 {
271 if (!IS_ERR_OR_NULL(ipu_crtc->dc))
272 ipu_dc_put(ipu_crtc->dc);
273 if (!IS_ERR_OR_NULL(ipu_crtc->di))
274 ipu_di_put(ipu_crtc->di);
275 }
276
277 static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
278 struct ipu_client_platformdata *pdata)
279 {
280 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
281 int ret;
282
283 ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
284 if (IS_ERR(ipu_crtc->dc)) {
285 ret = PTR_ERR(ipu_crtc->dc);
286 goto err_out;
287 }
288
289 ipu_crtc->di = ipu_di_get(ipu, pdata->di);
290 if (IS_ERR(ipu_crtc->di)) {
291 ret = PTR_ERR(ipu_crtc->di);
292 goto err_out;
293 }
294
295 return 0;
296 err_out:
297 ipu_put_resources(ipu_crtc);
298
299 return ret;
300 }
301
302 static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
303 struct ipu_client_platformdata *pdata, struct drm_device *drm)
304 {
305 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
306 int dp = -EINVAL;
307 int ret;
308
309 ret = ipu_get_resources(ipu_crtc, pdata);
310 if (ret) {
311 dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
312 ret);
313 return ret;
314 }
315
316 if (pdata->dp >= 0)
317 dp = IPU_DP_FLOW_SYNC_BG;
318 ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
319 DRM_PLANE_TYPE_PRIMARY);
320 if (IS_ERR(ipu_crtc->plane[0])) {
321 ret = PTR_ERR(ipu_crtc->plane[0]);
322 goto err_put_resources;
323 }
324
325 ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
326 &ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
327 pdata->of_node);
328 if (ret) {
329 dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
330 goto err_put_resources;
331 }
332
333 ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
334 if (ret) {
335 dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
336 ret);
337 goto err_remove_crtc;
338 }
339
340 /* If this crtc is using the DP, add an overlay plane */
341 if (pdata->dp >= 0 && pdata->dma[1] > 0) {
342 ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
343 IPU_DP_FLOW_SYNC_FG,
344 drm_crtc_mask(&ipu_crtc->base),
345 DRM_PLANE_TYPE_OVERLAY);
346 if (IS_ERR(ipu_crtc->plane[1])) {
347 ipu_crtc->plane[1] = NULL;
348 } else {
349 ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
350 if (ret) {
351 dev_err(ipu_crtc->dev, "getting plane 1 "
352 "resources failed with %d.\n", ret);
353 goto err_put_plane0_res;
354 }
355 }
356 }
357
358 ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
359 ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
360 "imx_drm", ipu_crtc);
361 if (ret < 0) {
362 dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
363 goto err_put_plane1_res;
364 }
365 /* Only enable IRQ when we actually need it to trigger work. */
366 disable_irq(ipu_crtc->irq);
367
368 return 0;
369
370 err_put_plane1_res:
371 if (ipu_crtc->plane[1])
372 ipu_plane_put_resources(ipu_crtc->plane[1]);
373 err_put_plane0_res:
374 ipu_plane_put_resources(ipu_crtc->plane[0]);
375 err_remove_crtc:
376 imx_drm_remove_crtc(ipu_crtc->imx_crtc);
377 err_put_resources:
378 ipu_put_resources(ipu_crtc);
379
380 return ret;
381 }
382
383 static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
384 {
385 struct ipu_client_platformdata *pdata = dev->platform_data;
386 struct drm_device *drm = data;
387 struct ipu_crtc *ipu_crtc;
388 int ret;
389
390 ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
391 if (!ipu_crtc)
392 return -ENOMEM;
393
394 ipu_crtc->dev = dev;
395
396 ret = ipu_crtc_init(ipu_crtc, pdata, drm);
397 if (ret)
398 return ret;
399
400 dev_set_drvdata(dev, ipu_crtc);
401
402 return 0;
403 }
404
405 static void ipu_drm_unbind(struct device *dev, struct device *master,
406 void *data)
407 {
408 struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
409
410 imx_drm_remove_crtc(ipu_crtc->imx_crtc);
411
412 ipu_put_resources(ipu_crtc);
413 if (ipu_crtc->plane[1])
414 ipu_plane_put_resources(ipu_crtc->plane[1]);
415 ipu_plane_put_resources(ipu_crtc->plane[0]);
416 }
417
418 static const struct component_ops ipu_crtc_ops = {
419 .bind = ipu_drm_bind,
420 .unbind = ipu_drm_unbind,
421 };
422
423 static int ipu_drm_probe(struct platform_device *pdev)
424 {
425 struct device *dev = &pdev->dev;
426 int ret;
427
428 if (!dev->platform_data)
429 return -EINVAL;
430
431 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
432 if (ret)
433 return ret;
434
435 return component_add(dev, &ipu_crtc_ops);
436 }
437
438 static int ipu_drm_remove(struct platform_device *pdev)
439 {
440 component_del(&pdev->dev, &ipu_crtc_ops);
441 return 0;
442 }
443
444 static struct platform_driver ipu_drm_driver = {
445 .driver = {
446 .name = "imx-ipuv3-crtc",
447 },
448 .probe = ipu_drm_probe,
449 .remove = ipu_drm_remove,
450 };
451 module_platform_driver(ipu_drm_driver);
452
453 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
454 MODULE_DESCRIPTION(DRIVER_DESC);
455 MODULE_LICENSE("GPL");
456 MODULE_ALIAS("platform:imx-ipuv3-crtc");
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