846b5f558897fb2927731b437e9dabf4e49e6970
[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-crtc.c
1 /*
2 * i.MX IPUv3 Graphics driver
3 *
4 * Copyright (C) 2011 Sascha Hauer, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/component.h>
16 #include <linux/module.h>
17 #include <linux/export.h>
18 #include <linux/device.h>
19 #include <linux/platform_device.h>
20 #include <drm/drmP.h>
21 #include <drm/drm_crtc_helper.h>
22 #include <linux/fb.h>
23 #include <linux/clk.h>
24 #include <linux/errno.h>
25 #include <drm/drm_gem_cma_helper.h>
26 #include <drm/drm_fb_cma_helper.h>
27
28 #include <video/imx-ipu-v3.h>
29 #include "imx-drm.h"
30 #include "ipuv3-plane.h"
31
32 #define DRIVER_DESC "i.MX IPUv3 Graphics"
33
34 struct ipu_crtc {
35 struct device *dev;
36 struct drm_crtc base;
37 struct imx_drm_crtc *imx_crtc;
38
39 /* plane[0] is the full plane, plane[1] is the partial plane */
40 struct ipu_plane *plane[2];
41
42 struct ipu_dc *dc;
43 struct ipu_di *di;
44 int enabled;
45 struct drm_pending_vblank_event *page_flip_event;
46 struct drm_framebuffer *newfb;
47 int irq;
48 u32 bus_format;
49 int di_hsync_pin;
50 int di_vsync_pin;
51 };
52
53 #define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)
54
55 static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
56 {
57 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
58
59 if (ipu_crtc->enabled)
60 return;
61
62 ipu_dc_enable(ipu);
63 ipu_plane_enable(ipu_crtc->plane[0]);
64 /* Start DC channel and DI after IDMAC */
65 ipu_dc_enable_channel(ipu_crtc->dc);
66 ipu_di_enable(ipu_crtc->di);
67
68 ipu_crtc->enabled = 1;
69 }
70
71 static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
72 {
73 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
74
75 if (!ipu_crtc->enabled)
76 return;
77
78 /* Stop DC channel and DI before IDMAC */
79 ipu_dc_disable_channel(ipu_crtc->dc);
80 ipu_di_disable(ipu_crtc->di);
81 ipu_plane_disable(ipu_crtc->plane[0]);
82 ipu_dc_disable(ipu);
83
84 ipu_crtc->enabled = 0;
85 }
86
87 static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
88 {
89 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
90
91 dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);
92
93 switch (mode) {
94 case DRM_MODE_DPMS_ON:
95 ipu_fb_enable(ipu_crtc);
96 break;
97 case DRM_MODE_DPMS_STANDBY:
98 case DRM_MODE_DPMS_SUSPEND:
99 case DRM_MODE_DPMS_OFF:
100 ipu_fb_disable(ipu_crtc);
101 break;
102 }
103 }
104
105 static int ipu_page_flip(struct drm_crtc *crtc,
106 struct drm_framebuffer *fb,
107 struct drm_pending_vblank_event *event,
108 uint32_t page_flip_flags)
109 {
110 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
111 int ret;
112
113 if (ipu_crtc->newfb)
114 return -EBUSY;
115
116 ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
117 if (ret) {
118 dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
119 list_del(&event->base.link);
120
121 return ret;
122 }
123
124 ipu_crtc->newfb = fb;
125 ipu_crtc->page_flip_event = event;
126 crtc->primary->fb = fb;
127
128 return 0;
129 }
130
131 static const struct drm_crtc_funcs ipu_crtc_funcs = {
132 .set_config = drm_crtc_helper_set_config,
133 .destroy = drm_crtc_cleanup,
134 .page_flip = ipu_page_flip,
135 };
136
137 static int ipu_crtc_mode_set(struct drm_crtc *crtc,
138 struct drm_display_mode *orig_mode,
139 struct drm_display_mode *mode,
140 int x, int y,
141 struct drm_framebuffer *old_fb)
142 {
143 struct drm_device *dev = crtc->dev;
144 struct drm_encoder *encoder;
145 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
146 struct ipu_di_signal_cfg sig_cfg = {};
147 unsigned long encoder_types = 0;
148 int ret;
149
150 dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
151 mode->hdisplay);
152 dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
153 mode->vdisplay);
154
155 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
156 if (encoder->crtc == crtc)
157 encoder_types |= BIT(encoder->encoder_type);
158
159 dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
160 __func__, encoder_types);
161
162 /*
163 * If we have DAC or LDB, then we need the IPU DI clock to be
164 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
165 * clock from 27 MHz TVE_DI clock, but allow to divide it.
166 */
167 if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
168 BIT(DRM_MODE_ENCODER_LVDS)))
169 sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
170 else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
171 sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
172 else
173 sig_cfg.clkflags = 0;
174
175 sig_cfg.enable_pol = 1;
176 sig_cfg.clk_pol = 0;
177 sig_cfg.bus_format = ipu_crtc->bus_format;
178 sig_cfg.v_to_h_sync = 0;
179 sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
180 sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
181
182 drm_display_mode_to_videomode(mode, &sig_cfg.mode);
183
184 ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
185 mode->flags & DRM_MODE_FLAG_INTERLACE,
186 ipu_crtc->bus_format, mode->hdisplay);
187 if (ret) {
188 dev_err(ipu_crtc->dev,
189 "initializing display controller failed with %d\n",
190 ret);
191 return ret;
192 }
193
194 ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
195 if (ret) {
196 dev_err(ipu_crtc->dev,
197 "initializing panel failed with %d\n", ret);
198 return ret;
199 }
200
201 return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode,
202 crtc->primary->fb,
203 0, 0, mode->hdisplay, mode->vdisplay,
204 x, y, mode->hdisplay, mode->vdisplay,
205 mode->flags & DRM_MODE_FLAG_INTERLACE);
206 }
207
208 static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
209 {
210 unsigned long flags;
211 struct drm_device *drm = ipu_crtc->base.dev;
212
213 spin_lock_irqsave(&drm->event_lock, flags);
214 if (ipu_crtc->page_flip_event)
215 drm_crtc_send_vblank_event(&ipu_crtc->base,
216 ipu_crtc->page_flip_event);
217 ipu_crtc->page_flip_event = NULL;
218 imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
219 spin_unlock_irqrestore(&drm->event_lock, flags);
220 }
221
222 static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
223 {
224 struct ipu_crtc *ipu_crtc = dev_id;
225
226 imx_drm_handle_vblank(ipu_crtc->imx_crtc);
227
228 if (ipu_crtc->newfb) {
229 struct ipu_plane *plane = ipu_crtc->plane[0];
230
231 ipu_crtc->newfb = NULL;
232 ipu_plane_set_base(plane, ipu_crtc->base.primary->fb,
233 plane->x, plane->y);
234 ipu_crtc_handle_pageflip(ipu_crtc);
235 }
236
237 return IRQ_HANDLED;
238 }
239
240 static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
241 const struct drm_display_mode *mode,
242 struct drm_display_mode *adjusted_mode)
243 {
244 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
245 struct videomode vm;
246 int ret;
247
248 drm_display_mode_to_videomode(adjusted_mode, &vm);
249
250 ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
251 if (ret)
252 return false;
253
254 drm_display_mode_from_videomode(&vm, adjusted_mode);
255
256 return true;
257 }
258
259 static void ipu_crtc_prepare(struct drm_crtc *crtc)
260 {
261 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
262
263 ipu_fb_disable(ipu_crtc);
264 }
265
266 static void ipu_crtc_commit(struct drm_crtc *crtc)
267 {
268 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
269
270 ipu_fb_enable(ipu_crtc);
271 }
272
273 static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
274 .dpms = ipu_crtc_dpms,
275 .mode_fixup = ipu_crtc_mode_fixup,
276 .mode_set = ipu_crtc_mode_set,
277 .prepare = ipu_crtc_prepare,
278 .commit = ipu_crtc_commit,
279 };
280
281 static int ipu_enable_vblank(struct drm_crtc *crtc)
282 {
283 return 0;
284 }
285
286 static void ipu_disable_vblank(struct drm_crtc *crtc)
287 {
288 }
289
290 static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc,
291 u32 bus_format, int hsync_pin, int vsync_pin)
292 {
293 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
294
295 ipu_crtc->bus_format = bus_format;
296 ipu_crtc->di_hsync_pin = hsync_pin;
297 ipu_crtc->di_vsync_pin = vsync_pin;
298
299 return 0;
300 }
301
302 static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
303 .enable_vblank = ipu_enable_vblank,
304 .disable_vblank = ipu_disable_vblank,
305 .set_interface_pix_fmt = ipu_set_interface_pix_fmt,
306 .crtc_funcs = &ipu_crtc_funcs,
307 .crtc_helper_funcs = &ipu_helper_funcs,
308 };
309
310 static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
311 {
312 if (!IS_ERR_OR_NULL(ipu_crtc->dc))
313 ipu_dc_put(ipu_crtc->dc);
314 if (!IS_ERR_OR_NULL(ipu_crtc->di))
315 ipu_di_put(ipu_crtc->di);
316 }
317
318 static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
319 struct ipu_client_platformdata *pdata)
320 {
321 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
322 int ret;
323
324 ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
325 if (IS_ERR(ipu_crtc->dc)) {
326 ret = PTR_ERR(ipu_crtc->dc);
327 goto err_out;
328 }
329
330 ipu_crtc->di = ipu_di_get(ipu, pdata->di);
331 if (IS_ERR(ipu_crtc->di)) {
332 ret = PTR_ERR(ipu_crtc->di);
333 goto err_out;
334 }
335
336 return 0;
337 err_out:
338 ipu_put_resources(ipu_crtc);
339
340 return ret;
341 }
342
343 static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
344 struct ipu_client_platformdata *pdata, struct drm_device *drm)
345 {
346 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
347 int dp = -EINVAL;
348 int ret;
349
350 ret = ipu_get_resources(ipu_crtc, pdata);
351 if (ret) {
352 dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
353 ret);
354 return ret;
355 }
356
357 if (pdata->dp >= 0)
358 dp = IPU_DP_FLOW_SYNC_BG;
359 ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
360 DRM_PLANE_TYPE_PRIMARY);
361 if (IS_ERR(ipu_crtc->plane[0])) {
362 ret = PTR_ERR(ipu_crtc->plane[0]);
363 goto err_put_resources;
364 }
365
366 ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
367 &ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
368 ipu_crtc->dev->of_node);
369 if (ret) {
370 dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
371 goto err_put_resources;
372 }
373
374 ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
375 if (ret) {
376 dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
377 ret);
378 goto err_remove_crtc;
379 }
380
381 /* If this crtc is using the DP, add an overlay plane */
382 if (pdata->dp >= 0 && pdata->dma[1] > 0) {
383 ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
384 IPU_DP_FLOW_SYNC_FG,
385 drm_crtc_mask(&ipu_crtc->base),
386 DRM_PLANE_TYPE_OVERLAY);
387 if (IS_ERR(ipu_crtc->plane[1]))
388 ipu_crtc->plane[1] = NULL;
389 }
390
391 ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
392 ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
393 "imx_drm", ipu_crtc);
394 if (ret < 0) {
395 dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
396 goto err_put_plane_res;
397 }
398
399 return 0;
400
401 err_put_plane_res:
402 ipu_plane_put_resources(ipu_crtc->plane[0]);
403 err_remove_crtc:
404 imx_drm_remove_crtc(ipu_crtc->imx_crtc);
405 err_put_resources:
406 ipu_put_resources(ipu_crtc);
407
408 return ret;
409 }
410
411 static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
412 {
413 struct ipu_client_platformdata *pdata = dev->platform_data;
414 struct drm_device *drm = data;
415 struct ipu_crtc *ipu_crtc;
416 int ret;
417
418 ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
419 if (!ipu_crtc)
420 return -ENOMEM;
421
422 ipu_crtc->dev = dev;
423
424 ret = ipu_crtc_init(ipu_crtc, pdata, drm);
425 if (ret)
426 return ret;
427
428 dev_set_drvdata(dev, ipu_crtc);
429
430 return 0;
431 }
432
433 static void ipu_drm_unbind(struct device *dev, struct device *master,
434 void *data)
435 {
436 struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
437
438 imx_drm_remove_crtc(ipu_crtc->imx_crtc);
439
440 ipu_plane_put_resources(ipu_crtc->plane[0]);
441 ipu_put_resources(ipu_crtc);
442 }
443
444 static const struct component_ops ipu_crtc_ops = {
445 .bind = ipu_drm_bind,
446 .unbind = ipu_drm_unbind,
447 };
448
449 static int ipu_drm_probe(struct platform_device *pdev)
450 {
451 struct device *dev = &pdev->dev;
452 int ret;
453
454 if (!dev->platform_data)
455 return -EINVAL;
456
457 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
458 if (ret)
459 return ret;
460
461 return component_add(dev, &ipu_crtc_ops);
462 }
463
464 static int ipu_drm_remove(struct platform_device *pdev)
465 {
466 component_del(&pdev->dev, &ipu_crtc_ops);
467 return 0;
468 }
469
470 static struct platform_driver ipu_drm_driver = {
471 .driver = {
472 .name = "imx-ipuv3-crtc",
473 },
474 .probe = ipu_drm_probe,
475 .remove = ipu_drm_remove,
476 };
477 module_platform_driver(ipu_drm_driver);
478
479 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
480 MODULE_DESCRIPTION(DRIVER_DESC);
481 MODULE_LICENSE("GPL");
482 MODULE_ALIAS("platform:imx-ipuv3-crtc");
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