2 * i.MX IPUv3 DP Overlay Planes
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <drm/drm_fb_cma_helper.h>
18 #include <drm/drm_gem_cma_helper.h>
20 #include "video/imx-ipu-v3.h"
21 #include "ipuv3-plane.h"
23 #define to_ipu_plane(x) container_of(x, struct ipu_plane, base)
25 static const uint32_t ipu_plane_formats
[] = {
50 int ipu_plane_irq(struct ipu_plane
*ipu_plane
)
52 return ipu_idmac_channel_irq(ipu_plane
->ipu
, ipu_plane
->ipu_ch
,
56 static int calc_vref(struct drm_display_mode
*mode
)
58 unsigned long htotal
, vtotal
;
60 htotal
= mode
->htotal
;
61 vtotal
= mode
->vtotal
;
63 if (!htotal
|| !vtotal
)
66 return DIV_ROUND_UP(mode
->clock
* 1000, vtotal
* htotal
);
69 static inline int calc_bandwidth(int width
, int height
, unsigned int vref
)
71 return width
* height
* vref
;
74 int ipu_plane_set_base(struct ipu_plane
*ipu_plane
, struct drm_framebuffer
*fb
,
77 struct drm_gem_cma_object
*cma_obj
[3];
78 unsigned long eba
, ubo
, vbo
;
81 for (i
= 0; i
< drm_format_num_planes(fb
->pixel_format
); i
++) {
82 cma_obj
[i
] = drm_fb_cma_get_gem_obj(fb
, i
);
84 DRM_DEBUG_KMS("plane %d entry is null.\n", i
);
89 eba
= cma_obj
[0]->paddr
+ fb
->offsets
[0] +
90 fb
->pitches
[0] * y
+ (fb
->bits_per_pixel
>> 3) * x
;
93 DRM_DEBUG_KMS("base address must be a multiple of 8.\n");
97 if (fb
->pitches
[0] < 1 || fb
->pitches
[0] > 16384) {
98 DRM_DEBUG_KMS("pitches out of range.\n");
102 if (ipu_plane
->enabled
&& fb
->pitches
[0] != ipu_plane
->stride
[0]) {
103 DRM_DEBUG_KMS("pitches must not change while plane is enabled.\n");
107 ipu_plane
->stride
[0] = fb
->pitches
[0];
109 switch (fb
->pixel_format
) {
110 case DRM_FORMAT_YUV420
:
111 case DRM_FORMAT_YVU420
:
113 * Multiplanar formats have to meet the following restrictions:
114 * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
115 * - EBA, UBO and VBO are a multiple of 8
116 * - UBO and VBO are unsigned and not larger than 0xfffff8
117 * - Only EBA may be changed while scanout is active
118 * - The strides of U and V planes must be identical.
120 ubo
= cma_obj
[1]->paddr
+ fb
->offsets
[1] +
121 fb
->pitches
[1] * y
/ 2 + x
/ 2 - eba
;
122 vbo
= cma_obj
[2]->paddr
+ fb
->offsets
[2] +
123 fb
->pitches
[2] * y
/ 2 + x
/ 2 - eba
;
125 if ((ubo
& 0x7) || (vbo
& 0x7)) {
126 DRM_DEBUG_KMS("U/V buffer offsets must be a multiple of 8.\n");
130 if ((ubo
> 0xfffff8) || (vbo
> 0xfffff8)) {
131 DRM_DEBUG_KMS("U/V buffer offsets must be positive and not larger than 0xfffff8.\n");
135 if (ipu_plane
->enabled
&& ((ipu_plane
->u_offset
!= ubo
) ||
136 (ipu_plane
->v_offset
!= vbo
))) {
137 DRM_DEBUG_KMS("U/V buffer offsets must not change while plane is enabled.\n");
141 if (fb
->pitches
[1] != fb
->pitches
[2]) {
142 DRM_DEBUG_KMS("U/V pitches must be identical.\n");
146 if (fb
->pitches
[1] < 1 || fb
->pitches
[1] > 16384) {
147 DRM_DEBUG_KMS("U/V pitches out of range.\n");
151 if (ipu_plane
->enabled
&&
152 (ipu_plane
->stride
[1] != fb
->pitches
[1])) {
153 DRM_DEBUG_KMS("U/V pitches must not change while plane is enabled.\n");
157 ipu_plane
->u_offset
= ubo
;
158 ipu_plane
->v_offset
= vbo
;
159 ipu_plane
->stride
[1] = fb
->pitches
[1];
161 dev_dbg(ipu_plane
->base
.dev
->dev
,
162 "phys = %pad %pad %pad, x = %d, y = %d",
163 &cma_obj
[0]->paddr
, &cma_obj
[1]->paddr
,
164 &cma_obj
[2]->paddr
, x
, y
);
167 dev_dbg(ipu_plane
->base
.dev
->dev
, "phys = %pad, x = %d, y = %d",
168 &cma_obj
[0]->paddr
, x
, y
);
172 if (ipu_plane
->enabled
) {
173 active
= ipu_idmac_get_current_buffer(ipu_plane
->ipu_ch
);
174 ipu_cpmem_set_buffer(ipu_plane
->ipu_ch
, !active
, eba
);
175 ipu_idmac_select_buffer(ipu_plane
->ipu_ch
, !active
);
177 ipu_cpmem_set_buffer(ipu_plane
->ipu_ch
, 0, eba
);
178 ipu_cpmem_set_buffer(ipu_plane
->ipu_ch
, 1, eba
);
181 /* cache offsets for subsequent pageflips */
188 int ipu_plane_mode_set(struct ipu_plane
*ipu_plane
, struct drm_crtc
*crtc
,
189 struct drm_display_mode
*mode
,
190 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
191 unsigned int crtc_w
, unsigned int crtc_h
,
192 uint32_t src_x
, uint32_t src_y
,
193 uint32_t src_w
, uint32_t src_h
, bool interlaced
)
195 struct device
*dev
= ipu_plane
->base
.dev
->dev
;
199 if (src_w
!= crtc_w
|| src_h
!= crtc_h
)
202 /* clip to crtc bounds */
204 if (-crtc_x
> crtc_w
)
212 if (-crtc_y
> crtc_h
)
219 if (crtc_x
+ crtc_w
> mode
->hdisplay
) {
220 if (crtc_x
> mode
->hdisplay
)
222 crtc_w
= mode
->hdisplay
- crtc_x
;
225 if (crtc_y
+ crtc_h
> mode
->vdisplay
) {
226 if (crtc_y
> mode
->vdisplay
)
228 crtc_h
= mode
->vdisplay
- crtc_y
;
231 /* full plane minimum width is 13 pixels */
232 if (crtc_w
< 13 && (ipu_plane
->dp_flow
!= IPU_DP_FLOW_SYNC_FG
))
238 * since we cannot touch active IDMAC channels, we do not support
239 * resizing the enabled plane or changing its format
241 if (ipu_plane
->enabled
) {
242 if (src_w
!= ipu_plane
->w
|| src_h
!= ipu_plane
->h
||
243 fb
->pixel_format
!= ipu_plane
->base
.fb
->pixel_format
)
246 return ipu_plane_set_base(ipu_plane
, fb
, src_x
, src_y
);
249 switch (ipu_plane
->dp_flow
) {
250 case IPU_DP_FLOW_SYNC_BG
:
251 ret
= ipu_dp_setup_channel(ipu_plane
->dp
,
252 IPUV3_COLORSPACE_RGB
,
253 IPUV3_COLORSPACE_RGB
);
256 "initializing display processor failed with %d\n",
260 ipu_dp_set_global_alpha(ipu_plane
->dp
, true, 0, true);
262 case IPU_DP_FLOW_SYNC_FG
:
263 ipu_dp_setup_channel(ipu_plane
->dp
,
264 ipu_drm_fourcc_to_colorspace(fb
->pixel_format
),
265 IPUV3_COLORSPACE_UNKNOWN
);
266 ipu_dp_set_window_pos(ipu_plane
->dp
, crtc_x
, crtc_y
);
267 /* Enable local alpha on partial plane */
268 switch (fb
->pixel_format
) {
269 case DRM_FORMAT_ARGB1555
:
270 case DRM_FORMAT_ABGR1555
:
271 case DRM_FORMAT_RGBA5551
:
272 case DRM_FORMAT_BGRA5551
:
273 case DRM_FORMAT_ARGB4444
:
274 case DRM_FORMAT_ARGB8888
:
275 case DRM_FORMAT_ABGR8888
:
276 case DRM_FORMAT_RGBA8888
:
277 case DRM_FORMAT_BGRA8888
:
278 ipu_dp_set_global_alpha(ipu_plane
->dp
, false, 0, false);
285 ret
= ipu_dmfc_alloc_bandwidth(ipu_plane
->dmfc
,
286 calc_bandwidth(crtc_w
, crtc_h
,
287 calc_vref(mode
)), 64);
289 dev_err(dev
, "allocating dmfc bandwidth failed with %d\n", ret
);
293 ipu_dmfc_config_wait4eot(ipu_plane
->dmfc
, crtc_w
);
295 ipu_cpmem_zero(ipu_plane
->ipu_ch
);
296 ipu_cpmem_set_resolution(ipu_plane
->ipu_ch
, src_w
, src_h
);
297 ret
= ipu_cpmem_set_fmt(ipu_plane
->ipu_ch
, fb
->pixel_format
);
299 dev_err(dev
, "unsupported pixel format 0x%08x\n",
303 ipu_cpmem_set_high_priority(ipu_plane
->ipu_ch
);
304 ipu_idmac_set_double_buffer(ipu_plane
->ipu_ch
, 1);
305 ipu_cpmem_set_stride(ipu_plane
->ipu_ch
, fb
->pitches
[0]);
307 ret
= ipu_plane_set_base(ipu_plane
, fb
, src_x
, src_y
);
311 ipu_cpmem_interlaced_scan(ipu_plane
->ipu_ch
, fb
->pitches
[0]);
313 if (fb
->pixel_format
== DRM_FORMAT_YUV420
) {
314 ipu_cpmem_set_yuv_planar_full(ipu_plane
->ipu_ch
,
315 ipu_plane
->stride
[1],
317 ipu_plane
->v_offset
);
318 } else if (fb
->pixel_format
== DRM_FORMAT_YVU420
) {
319 ipu_cpmem_set_yuv_planar_full(ipu_plane
->ipu_ch
,
320 ipu_plane
->stride
[1],
322 ipu_plane
->u_offset
);
325 ipu_plane
->w
= src_w
;
326 ipu_plane
->h
= src_h
;
331 void ipu_plane_put_resources(struct ipu_plane
*ipu_plane
)
333 if (!IS_ERR_OR_NULL(ipu_plane
->dp
))
334 ipu_dp_put(ipu_plane
->dp
);
335 if (!IS_ERR_OR_NULL(ipu_plane
->dmfc
))
336 ipu_dmfc_put(ipu_plane
->dmfc
);
337 if (!IS_ERR_OR_NULL(ipu_plane
->ipu_ch
))
338 ipu_idmac_put(ipu_plane
->ipu_ch
);
341 int ipu_plane_get_resources(struct ipu_plane
*ipu_plane
)
345 ipu_plane
->ipu_ch
= ipu_idmac_get(ipu_plane
->ipu
, ipu_plane
->dma
);
346 if (IS_ERR(ipu_plane
->ipu_ch
)) {
347 ret
= PTR_ERR(ipu_plane
->ipu_ch
);
348 DRM_ERROR("failed to get idmac channel: %d\n", ret
);
352 ipu_plane
->dmfc
= ipu_dmfc_get(ipu_plane
->ipu
, ipu_plane
->dma
);
353 if (IS_ERR(ipu_plane
->dmfc
)) {
354 ret
= PTR_ERR(ipu_plane
->dmfc
);
355 DRM_ERROR("failed to get dmfc: ret %d\n", ret
);
359 if (ipu_plane
->dp_flow
>= 0) {
360 ipu_plane
->dp
= ipu_dp_get(ipu_plane
->ipu
, ipu_plane
->dp_flow
);
361 if (IS_ERR(ipu_plane
->dp
)) {
362 ret
= PTR_ERR(ipu_plane
->dp
);
363 DRM_ERROR("failed to get dp flow: %d\n", ret
);
370 ipu_plane_put_resources(ipu_plane
);
375 void ipu_plane_enable(struct ipu_plane
*ipu_plane
)
378 ipu_dp_enable(ipu_plane
->ipu
);
379 ipu_dmfc_enable_channel(ipu_plane
->dmfc
);
380 ipu_idmac_enable_channel(ipu_plane
->ipu_ch
);
382 ipu_dp_enable_channel(ipu_plane
->dp
);
384 ipu_plane
->enabled
= true;
387 void ipu_plane_disable(struct ipu_plane
*ipu_plane
)
389 ipu_plane
->enabled
= false;
391 ipu_idmac_wait_busy(ipu_plane
->ipu_ch
, 50);
394 ipu_dp_disable_channel(ipu_plane
->dp
);
395 ipu_idmac_disable_channel(ipu_plane
->ipu_ch
);
396 ipu_dmfc_disable_channel(ipu_plane
->dmfc
);
398 ipu_dp_disable(ipu_plane
->ipu
);
405 static int ipu_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
406 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
407 unsigned int crtc_w
, unsigned int crtc_h
,
408 uint32_t src_x
, uint32_t src_y
,
409 uint32_t src_w
, uint32_t src_h
)
411 struct ipu_plane
*ipu_plane
= to_ipu_plane(plane
);
414 DRM_DEBUG_KMS("plane - %p\n", plane
);
416 if (!ipu_plane
->enabled
)
417 ret
= ipu_plane_get_resources(ipu_plane
);
421 ret
= ipu_plane_mode_set(ipu_plane
, crtc
, &crtc
->hwmode
, fb
,
422 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
423 src_x
>> 16, src_y
>> 16, src_w
>> 16, src_h
>> 16,
426 ipu_plane_put_resources(ipu_plane
);
430 if (crtc
!= plane
->crtc
)
431 dev_dbg(plane
->dev
->dev
, "crtc change: %p -> %p\n",
434 if (!ipu_plane
->enabled
)
435 ipu_plane_enable(ipu_plane
);
440 static int ipu_disable_plane(struct drm_plane
*plane
)
442 struct ipu_plane
*ipu_plane
= to_ipu_plane(plane
);
444 DRM_DEBUG_KMS("[%d] %s\n", __LINE__
, __func__
);
446 if (ipu_plane
->enabled
)
447 ipu_plane_disable(ipu_plane
);
449 ipu_plane_put_resources(ipu_plane
);
454 static void ipu_plane_destroy(struct drm_plane
*plane
)
456 struct ipu_plane
*ipu_plane
= to_ipu_plane(plane
);
458 DRM_DEBUG_KMS("[%d] %s\n", __LINE__
, __func__
);
460 ipu_disable_plane(plane
);
461 drm_plane_cleanup(plane
);
465 static const struct drm_plane_funcs ipu_plane_funcs
= {
466 .update_plane
= ipu_update_plane
,
467 .disable_plane
= ipu_disable_plane
,
468 .destroy
= ipu_plane_destroy
,
471 struct ipu_plane
*ipu_plane_init(struct drm_device
*dev
, struct ipu_soc
*ipu
,
472 int dma
, int dp
, unsigned int possible_crtcs
,
473 enum drm_plane_type type
)
475 struct ipu_plane
*ipu_plane
;
478 DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
479 dma
, dp
, possible_crtcs
);
481 ipu_plane
= kzalloc(sizeof(*ipu_plane
), GFP_KERNEL
);
483 DRM_ERROR("failed to allocate plane\n");
484 return ERR_PTR(-ENOMEM
);
487 ipu_plane
->ipu
= ipu
;
488 ipu_plane
->dma
= dma
;
489 ipu_plane
->dp_flow
= dp
;
491 ret
= drm_universal_plane_init(dev
, &ipu_plane
->base
, possible_crtcs
,
492 &ipu_plane_funcs
, ipu_plane_formats
,
493 ARRAY_SIZE(ipu_plane_formats
), type
,
496 DRM_ERROR("failed to initialize plane\n");