drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  * Authors:
   4  *      YT Shen <yt.shen@mediatek.com>
   5  *      CK Hu <ck.hu@mediatek.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/platform_device.h>
  23 #include <drm/drmP.h>
  24 #include "mtk_drm_drv.h"
  25 #include "mtk_drm_plane.h"
  26 #include "mtk_drm_ddp_comp.h"
  27
  28 #define DISP_OD_EN                              0x0000
  29 #define DISP_OD_INTEN                           0x0008
  30 #define DISP_OD_INTSTA                          0x000c
  31 #define DISP_OD_CFG                             0x0020
  32 #define DISP_OD_SIZE                            0x0030
  33
  34 #define DISP_REG_UFO_START                      0x0000
  35
  36 #define DISP_COLOR_CFG_MAIN                     0x0400
  37 #define DISP_COLOR_START                        0x0c00
  38 #define DISP_COLOR_WIDTH                        0x0c50
  39 #define DISP_COLOR_HEIGHT                       0x0c54
  40
  41 #define DISP_AAL_EN                             0x0000
  42 #define DISP_AAL_SIZE                           0x0030
  43
  44 #define OD_RELAY_MODE           BIT(0)
  45
  46 #define UFO_BYPASS              BIT(2)
  47
  48 #define COLOR_BYPASS_ALL        BIT(7)
  49 #define COLOR_SEQ_SEL           BIT(13)
  50
  51 #define AAL_EN                  BIT(0)
  52
  53 static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
  54                              unsigned int h, unsigned int vrefresh)
  55 {
  56         writel(w, comp->regs + DISP_COLOR_WIDTH);
  57         writel(h, comp->regs + DISP_COLOR_HEIGHT);
  58 }
  59
  60 static void mtk_color_start(struct mtk_ddp_comp *comp)
  61 {
  62         writel(COLOR_BYPASS_ALL | COLOR_SEQ_SEL,
  63                comp->regs + DISP_COLOR_CFG_MAIN);
  64         writel(0x1, comp->regs + DISP_COLOR_START);
  65 }
  66
  67 static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
  68                           unsigned int h, unsigned int vrefresh)
  69 {
  70         writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
  71 }
  72
  73 static void mtk_od_start(struct mtk_ddp_comp *comp)
  74 {
  75         writel(OD_RELAY_MODE, comp->regs + DISP_OD_CFG);
  76         writel(1, comp->regs + DISP_OD_EN);
  77 }
  78
  79 static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
  80 {
  81         writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START);
  82 }
  83
  84 static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
  85                            unsigned int h, unsigned int vrefresh)
  86 {
  87         writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
  88 }
  89
  90 static void mtk_aal_start(struct mtk_ddp_comp *comp)
  91 {
  92         writel(AAL_EN, comp->regs + DISP_AAL_EN);
  93 }
  94
  95 static void mtk_aal_stop(struct mtk_ddp_comp *comp)
  96 {
  97         writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
  98 }
  99
 100 static const struct mtk_ddp_comp_funcs ddp_aal = {
 101         .config = mtk_aal_config,
 102         .start = mtk_aal_start,
 103         .stop = mtk_aal_stop,
 104 };
 105
 106 static const struct mtk_ddp_comp_funcs ddp_color = {
 107         .config = mtk_color_config,
 108         .start = mtk_color_start,
 109 };
 110
 111 static const struct mtk_ddp_comp_funcs ddp_od = {
 112         .config = mtk_od_config,
 113         .start = mtk_od_start,
 114 };
 115
 116 static const struct mtk_ddp_comp_funcs ddp_ufoe = {
 117         .start = mtk_ufoe_start,
 118 };
 119
 120 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 121         [MTK_DISP_OVL] = "ovl",
 122         [MTK_DISP_RDMA] = "rdma",
 123         [MTK_DISP_WDMA] = "wdma",
 124         [MTK_DISP_COLOR] = "color",
 125         [MTK_DISP_AAL] = "aal",
 126         [MTK_DISP_GAMMA] = "gamma",
 127         [MTK_DISP_UFOE] = "ufoe",
 128         [MTK_DSI] = "dsi",
 129         [MTK_DPI] = "dpi",
 130         [MTK_DISP_PWM] = "pwm",
 131         [MTK_DISP_MUTEX] = "mutex",
 132         [MTK_DISP_OD] = "od",
 133 };
 134
 135 struct mtk_ddp_comp_match {
 136         enum mtk_ddp_comp_type type;
 137         int alias_id;
 138         const struct mtk_ddp_comp_funcs *funcs;
 139 };
 140
 141 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 142         [DDP_COMPONENT_AAL]     = { MTK_DISP_AAL,       0, &ddp_aal },
 143         [DDP_COMPONENT_COLOR0]  = { MTK_DISP_COLOR,     0, &ddp_color },
 144         [DDP_COMPONENT_COLOR1]  = { MTK_DISP_COLOR,     1, &ddp_color },
 145         [DDP_COMPONENT_DPI0]    = { MTK_DPI,            0, NULL },
 146         [DDP_COMPONENT_DSI0]    = { MTK_DSI,            0, NULL },
 147         [DDP_COMPONENT_DSI1]    = { MTK_DSI,            1, NULL },
 148         [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA,     0, NULL },
 149         [DDP_COMPONENT_OD]      = { MTK_DISP_OD,        0, &ddp_od },
 150         [DDP_COMPONENT_OVL0]    = { MTK_DISP_OVL,       0, NULL },
 151         [DDP_COMPONENT_OVL1]    = { MTK_DISP_OVL,       1, NULL },
 152         [DDP_COMPONENT_PWM0]    = { MTK_DISP_PWM,       0, NULL },
 153         [DDP_COMPONENT_RDMA0]   = { MTK_DISP_RDMA,      0, NULL },
 154         [DDP_COMPONENT_RDMA1]   = { MTK_DISP_RDMA,      1, NULL },
 155         [DDP_COMPONENT_RDMA2]   = { MTK_DISP_RDMA,      2, NULL },
 156         [DDP_COMPONENT_UFOE]    = { MTK_DISP_UFOE,      0, &ddp_ufoe },
 157         [DDP_COMPONENT_WDMA0]   = { MTK_DISP_WDMA,      0, NULL },
 158         [DDP_COMPONENT_WDMA1]   = { MTK_DISP_WDMA,      1, NULL },
 159 };
 160
 161 int mtk_ddp_comp_get_id(struct device_node *node,
 162                         enum mtk_ddp_comp_type comp_type)
 163 {
 164         int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
 165         int i;
 166
 167         for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
 168                 if (comp_type == mtk_ddp_matches[i].type &&
 169                     (id < 0 || id == mtk_ddp_matches[i].alias_id))
 170                         return i;
 171         }
 172
 173         return -EINVAL;
 174 }
 175
 176 int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
 177                       struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
 178                       const struct mtk_ddp_comp_funcs *funcs)
 179 {
 180         enum mtk_ddp_comp_type type;
 181         struct device_node *larb_node;
 182         struct platform_device *larb_pdev;
 183
 184         if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
 185                 return -EINVAL;
 186
 187         comp->id = comp_id;
 188         comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs;
 189
 190         if (comp_id == DDP_COMPONENT_DPI0 ||
 191             comp_id == DDP_COMPONENT_DSI0 ||
 192             comp_id == DDP_COMPONENT_PWM0) {
 193                 comp->regs = NULL;
 194                 comp->clk = NULL;
 195                 comp->irq = 0;
 196                 return 0;
 197         }
 198
 199         comp->regs = of_iomap(node, 0);
 200         comp->irq = of_irq_get(node, 0);
 201         comp->clk = of_clk_get(node, 0);
 202         if (IS_ERR(comp->clk))
 203                 comp->clk = NULL;
 204
 205         type = mtk_ddp_matches[comp_id].type;
 206
 207         /* Only DMA capable components need the LARB property */
 208         comp->larb_dev = NULL;
 209         if (type != MTK_DISP_OVL &&
 210             type != MTK_DISP_RDMA &&
 211             type != MTK_DISP_WDMA)
 212                 return 0;
 213
 214         larb_node = of_parse_phandle(node, "mediatek,larb", 0);
 215         if (!larb_node) {
 216                 dev_err(dev,
 217                         "Missing mediadek,larb phandle in %s node\n",
 218                         node->full_name);
 219                 return -EINVAL;
 220         }
 221
 222         larb_pdev = of_find_device_by_node(larb_node);
 223         if (!larb_pdev) {
 224                 dev_warn(dev, "Waiting for larb device %s\n",
 225                          larb_node->full_name);
 226                 of_node_put(larb_node);
 227                 return -EPROBE_DEFER;
 228         }
 229         of_node_put(larb_node);
 230
 231         comp->larb_dev = &larb_pdev->dev;
 232
 233         return 0;
 234 }
 235
 236 int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp)
 237 {
 238         struct mtk_drm_private *private = drm->dev_private;
 239
 240         if (private->ddp_comp[comp->id])
 241                 return -EBUSY;
 242
 243         private->ddp_comp[comp->id] = comp;
 244         return 0;
 245 }
 246
 247 void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp)
 248 {
 249         struct mtk_drm_private *private = drm->dev_private;
 250
 251         private->ddp_comp[comp->id] = NULL;
 252 }