drivers/gpu/drm/msm/adreno/adreno_gpu.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "adreno_gpu.h"
  19 #include "msm_gem.h"
  20
  21 struct adreno_info {
  22         struct adreno_rev rev;
  23         uint32_t revn;
  24         const char *name;
  25         const char *pm4fw, *pfpfw;
  26         uint32_t gmem;
  27 };
  28
  29 #define ANY_ID 0xff
  30
  31 static const struct adreno_info gpulist[] = {
  32         {
  33                 .rev   = ADRENO_REV(3, 0, 5, ANY_ID),
  34                 .revn  = 305,
  35                 .name  = "A305",
  36                 .pm4fw = "a300_pm4.fw",
  37                 .pfpfw = "a300_pfp.fw",
  38                 .gmem  = SZ_256K,
  39         }, {
  40                 .rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  41                 .revn  = 320,
  42                 .name  = "A320",
  43                 .pm4fw = "a300_pm4.fw",
  44                 .pfpfw = "a300_pfp.fw",
  45                 .gmem  = SZ_512K,
  46         }, {
  47                 .rev   = ADRENO_REV(3, 3, 0, 0),
  48                 .revn  = 330,
  49                 .name  = "A330",
  50                 .pm4fw = "a330_pm4.fw",
  51                 .pfpfw = "a330_pfp.fw",
  52                 .gmem  = SZ_1M,
  53         },
  54 };
  55
  56 #define RB_SIZE    SZ_32K
  57 #define RB_BLKSIZE 16
  58
  59 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
  60 {
  61         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
  62
  63         switch (param) {
  64         case MSM_PARAM_GPU_ID:
  65                 *value = adreno_gpu->info->revn;
  66                 return 0;
  67         case MSM_PARAM_GMEM_SIZE:
  68                 *value = adreno_gpu->info->gmem;
  69                 return 0;
  70         default:
  71                 DBG("%s: invalid param: %u", gpu->name, param);
  72                 return -EINVAL;
  73         }
  74 }
  75
  76 #define rbmemptr(adreno_gpu, member)  \
  77         ((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))
  78
  79 int adreno_hw_init(struct msm_gpu *gpu)
  80 {
  81         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
  82
  83         DBG("%s", gpu->name);
  84
  85         /* Setup REG_CP_RB_CNTL: */
  86         gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
  87                         /* size is log2(quad-words): */
  88                         AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
  89                         AXXX_CP_RB_CNTL_BLKSZ(RB_BLKSIZE));
  90
  91         /* Setup ringbuffer address: */
  92         gpu_write(gpu, REG_AXXX_CP_RB_BASE, gpu->rb_iova);
  93         gpu_write(gpu, REG_AXXX_CP_RB_RPTR_ADDR, rbmemptr(adreno_gpu, rptr));
  94
  95         /* Setup scratch/timestamp: */
  96         gpu_write(gpu, REG_AXXX_SCRATCH_ADDR, rbmemptr(adreno_gpu, fence));
  97
  98         gpu_write(gpu, REG_AXXX_SCRATCH_UMSK, 0x1);
  99
 100         return 0;
 101 }
 102
 103 static uint32_t get_wptr(struct msm_ringbuffer *ring)
 104 {
 105         return ring->cur - ring->start;
 106 }
 107
 108 uint32_t adreno_last_fence(struct msm_gpu *gpu)
 109 {
 110         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 111         return adreno_gpu->memptrs->fence;
 112 }
 113
 114 int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 115                 struct msm_file_private *ctx)
 116 {
 117         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 118         struct msm_drm_private *priv = gpu->dev->dev_private;
 119         struct msm_ringbuffer *ring = gpu->rb;
 120         unsigned i, ibs = 0;
 121
 122         adreno_gpu->last_fence = submit->fence;
 123
 124         for (i = 0; i < submit->nr_cmds; i++) {
 125                 switch (submit->cmd[i].type) {
 126                 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
 127                         /* ignore IB-targets */
 128                         break;
 129                 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
 130                         /* ignore if there has not been a ctx switch: */
 131                         if (priv->lastctx == ctx)
 132                                 break;
 133                 case MSM_SUBMIT_CMD_BUF:
 134                         OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);
 135                         OUT_RING(ring, submit->cmd[i].iova);
 136                         OUT_RING(ring, submit->cmd[i].size);
 137                         ibs++;
 138                         break;
 139                 }
 140         }
 141
 142         /* on a320, at least, we seem to need to pad things out to an
 143          * even number of qwords to avoid issue w/ CP hanging on wrap-
 144          * around:
 145          */
 146         if (ibs % 2)
 147                 OUT_PKT2(ring);
 148
 149         OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
 150         OUT_RING(ring, submit->fence);
 151
 152         if (adreno_is_a3xx(adreno_gpu)) {
 153                 /* Flush HLSQ lazy updates to make sure there is nothing
 154                  * pending for indirect loads after the timestamp has
 155                  * passed:
 156                  */
 157                 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 158                 OUT_RING(ring, HLSQ_FLUSH);
 159
 160                 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 161                 OUT_RING(ring, 0x00000000);
 162         }
 163
 164         OUT_PKT3(ring, CP_EVENT_WRITE, 3);
 165         OUT_RING(ring, CACHE_FLUSH_TS);
 166         OUT_RING(ring, rbmemptr(adreno_gpu, fence));
 167         OUT_RING(ring, submit->fence);
 168
 169         /* we could maybe be clever and only CP_COND_EXEC the interrupt: */
 170         OUT_PKT3(ring, CP_INTERRUPT, 1);
 171         OUT_RING(ring, 0x80000000);
 172
 173 #if 0
 174         if (adreno_is_a3xx(adreno_gpu)) {
 175                 /* Dummy set-constant to trigger context rollover */
 176                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 177                 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
 178                 OUT_RING(ring, 0x00000000);
 179         }
 180 #endif
 181
 182         gpu->funcs->flush(gpu);
 183
 184         return 0;
 185 }
 186
 187 void adreno_flush(struct msm_gpu *gpu)
 188 {
 189         uint32_t wptr = get_wptr(gpu->rb);
 190
 191         /* ensure writes to ringbuffer have hit system memory: */
 192         mb();
 193
 194         gpu_write(gpu, REG_AXXX_CP_RB_WPTR, wptr);
 195 }
 196
 197 void adreno_idle(struct msm_gpu *gpu)
 198 {
 199         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 200         uint32_t rptr, wptr = get_wptr(gpu->rb);
 201         unsigned long t;
 202
 203         t = jiffies + ADRENO_IDLE_TIMEOUT;
 204
 205         /* then wait for CP to drain ringbuffer: */
 206         do {
 207                 rptr = adreno_gpu->memptrs->rptr;
 208                 if (rptr == wptr)
 209                         return;
 210         } while(time_before(jiffies, t));
 211
 212         DRM_ERROR("timeout waiting for %s to drain ringbuffer!\n", gpu->name);
 213
 214         /* TODO maybe we need to reset GPU here to recover from hang? */
 215 }
 216
 217 #ifdef CONFIG_DEBUG_FS
 218 void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
 219 {
 220         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 221
 222         seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
 223                         adreno_gpu->info->revn, adreno_gpu->rev.core,
 224                         adreno_gpu->rev.major, adreno_gpu->rev.minor,
 225                         adreno_gpu->rev.patchid);
 226
 227         seq_printf(m, "fence:    %d/%d\n", adreno_gpu->memptrs->fence,
 228                         adreno_gpu->last_fence);
 229         seq_printf(m, "rptr:     %d\n", adreno_gpu->memptrs->rptr);
 230         seq_printf(m, "wptr:     %d\n", adreno_gpu->memptrs->wptr);
 231         seq_printf(m, "rb wptr:  %d\n", get_wptr(gpu->rb));
 232 }
 233 #endif
 234
 235 void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
 236 {
 237         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 238         uint32_t freedwords;
 239         do {
 240                 uint32_t size = gpu->rb->size / 4;
 241                 uint32_t wptr = get_wptr(gpu->rb);
 242                 uint32_t rptr = adreno_gpu->memptrs->rptr;
 243                 freedwords = (rptr + (size - 1) - wptr) % size;
 244         } while(freedwords < ndwords);
 245 }
 246
 247 static const char *iommu_ports[] = {
 248                 "gfx3d_user", "gfx3d_priv",
 249                 "gfx3d1_user", "gfx3d1_priv",
 250 };
 251
 252 static inline bool _rev_match(uint8_t entry, uint8_t id)
 253 {
 254         return (entry == ANY_ID) || (entry == id);
 255 }
 256
 257 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 258                 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
 259                 struct adreno_rev rev)
 260 {
 261         int i, ret;
 262
 263         /* identify gpu: */
 264         for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
 265                 const struct adreno_info *info = &gpulist[i];
 266                 if (_rev_match(info->rev.core, rev.core) &&
 267                                 _rev_match(info->rev.major, rev.major) &&
 268                                 _rev_match(info->rev.minor, rev.minor) &&
 269                                 _rev_match(info->rev.patchid, rev.patchid)) {
 270                         gpu->info = info;
 271                         gpu->revn = info->revn;
 272                         break;
 273                 }
 274         }
 275
 276         if (i == ARRAY_SIZE(gpulist)) {
 277                 dev_err(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
 278                                 rev.core, rev.major, rev.minor, rev.patchid);
 279                 return -ENXIO;
 280         }
 281
 282         DBG("Found GPU: %s (%u.%u.%u.%u)", gpu->info->name,
 283                         rev.core, rev.major, rev.minor, rev.patchid);
 284
 285         gpu->funcs = funcs;
 286         gpu->rev = rev;
 287
 288         ret = request_firmware(&gpu->pm4, gpu->info->pm4fw, drm->dev);
 289         if (ret) {
 290                 dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n",
 291                                 gpu->info->pm4fw, ret);
 292                 return ret;
 293         }
 294
 295         ret = request_firmware(&gpu->pfp, gpu->info->pfpfw, drm->dev);
 296         if (ret) {
 297                 dev_err(drm->dev, "failed to load %s PFP firmware: %d\n",
 298                                 gpu->info->pfpfw, ret);
 299                 return ret;
 300         }
 301
 302         ret = msm_gpu_init(drm, pdev, &gpu->base, &funcs->base,
 303                         gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
 304                         RB_SIZE);
 305         if (ret)
 306                 return ret;
 307
 308         ret = msm_iommu_attach(drm, gpu->base.iommu,
 309                         iommu_ports, ARRAY_SIZE(iommu_ports));
 310         if (ret)
 311                 return ret;
 312
 313         gpu->memptrs_bo = msm_gem_new(drm, sizeof(*gpu->memptrs),
 314                         MSM_BO_UNCACHED);
 315         if (IS_ERR(gpu->memptrs_bo)) {
 316                 ret = PTR_ERR(gpu->memptrs_bo);
 317                 gpu->memptrs_bo = NULL;
 318                 dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
 319                 return ret;
 320         }
 321
 322         gpu->memptrs = msm_gem_vaddr_locked(gpu->memptrs_bo);
 323         if (!gpu->memptrs) {
 324                 dev_err(drm->dev, "could not vmap memptrs\n");
 325                 return -ENOMEM;
 326         }
 327
 328         ret = msm_gem_get_iova_locked(gpu->memptrs_bo, gpu->base.id,
 329                         &gpu->memptrs_iova);
 330         if (ret) {
 331                 dev_err(drm->dev, "could not map memptrs: %d\n", ret);
 332                 return ret;
 333         }
 334
 335         return 0;
 336 }
 337
 338 void adreno_gpu_cleanup(struct adreno_gpu *gpu)
 339 {
 340         if (gpu->memptrs_bo) {
 341                 if (gpu->memptrs_iova)
 342                         msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);
 343                 drm_gem_object_unreference(gpu->memptrs_bo);
 344         }
 345         if (gpu->pm4)
 346                 release_firmware(gpu->pm4);
 347         if (gpu->pfp)
 348                 release_firmware(gpu->pfp);
 349         msm_gpu_cleanup(&gpu->base);
 350 }