2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include "adreno_gpu.h"
22 struct adreno_rev rev
;
25 const char *pm4fw
, *pfpfw
;
31 static const struct adreno_info gpulist
[] = {
33 .rev
= ADRENO_REV(3, 0, 5, ANY_ID
),
36 .pm4fw
= "a300_pm4.fw",
37 .pfpfw
= "a300_pfp.fw",
40 .rev
= ADRENO_REV(3, 2, ANY_ID
, ANY_ID
),
43 .pm4fw
= "a300_pm4.fw",
44 .pfpfw
= "a300_pfp.fw",
47 .rev
= ADRENO_REV(3, 3, 0, 0),
50 .pm4fw
= "a330_pm4.fw",
51 .pfpfw
= "a330_pfp.fw",
56 #define RB_SIZE SZ_32K
59 int adreno_get_param(struct msm_gpu
*gpu
, uint32_t param
, uint64_t *value
)
61 struct adreno_gpu
*adreno_gpu
= to_adreno_gpu(gpu
);
64 case MSM_PARAM_GPU_ID
:
65 *value
= adreno_gpu
->info
->revn
;
67 case MSM_PARAM_GMEM_SIZE
:
68 *value
= adreno_gpu
->info
->gmem
;
71 DBG("%s: invalid param: %u", gpu
->name
, param
);
76 #define rbmemptr(adreno_gpu, member) \
77 ((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))
79 int adreno_hw_init(struct msm_gpu
*gpu
)
81 struct adreno_gpu
*adreno_gpu
= to_adreno_gpu(gpu
);
85 /* Setup REG_CP_RB_CNTL: */
86 gpu_write(gpu
, REG_AXXX_CP_RB_CNTL
,
87 /* size is log2(quad-words): */
88 AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu
->rb
->size
/ 8)) |
89 AXXX_CP_RB_CNTL_BLKSZ(RB_BLKSIZE
));
91 /* Setup ringbuffer address: */
92 gpu_write(gpu
, REG_AXXX_CP_RB_BASE
, gpu
->rb_iova
);
93 gpu_write(gpu
, REG_AXXX_CP_RB_RPTR_ADDR
, rbmemptr(adreno_gpu
, rptr
));
95 /* Setup scratch/timestamp: */
96 gpu_write(gpu
, REG_AXXX_SCRATCH_ADDR
, rbmemptr(adreno_gpu
, fence
));
98 gpu_write(gpu
, REG_AXXX_SCRATCH_UMSK
, 0x1);
103 static uint32_t get_wptr(struct msm_ringbuffer
*ring
)
105 return ring
->cur
- ring
->start
;
108 uint32_t adreno_last_fence(struct msm_gpu
*gpu
)
110 struct adreno_gpu
*adreno_gpu
= to_adreno_gpu(gpu
);
111 return adreno_gpu
->memptrs
->fence
;
114 void adreno_recover(struct msm_gpu
*gpu
)
116 struct adreno_gpu
*adreno_gpu
= to_adreno_gpu(gpu
);
117 struct drm_device
*dev
= gpu
->dev
;
120 gpu
->funcs
->pm_suspend(gpu
);
122 /* reset ringbuffer: */
123 gpu
->rb
->cur
= gpu
->rb
->start
;
125 /* reset completed fence seqno, just discard anything pending: */
126 adreno_gpu
->memptrs
->fence
= gpu
->submitted_fence
;
128 gpu
->funcs
->pm_resume(gpu
);
129 ret
= gpu
->funcs
->hw_init(gpu
);
131 dev_err(dev
->dev
, "gpu hw init failed: %d\n", ret
);
136 int adreno_submit(struct msm_gpu
*gpu
, struct msm_gem_submit
*submit
,
137 struct msm_file_private
*ctx
)
139 struct adreno_gpu
*adreno_gpu
= to_adreno_gpu(gpu
);
140 struct msm_drm_private
*priv
= gpu
->dev
->dev_private
;
141 struct msm_ringbuffer
*ring
= gpu
->rb
;
144 for (i
= 0; i
< submit
->nr_cmds
; i
++) {
145 switch (submit
->cmd
[i
].type
) {
146 case MSM_SUBMIT_CMD_IB_TARGET_BUF
:
147 /* ignore IB-targets */
149 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF
:
150 /* ignore if there has not been a ctx switch: */
151 if (priv
->lastctx
== ctx
)
153 case MSM_SUBMIT_CMD_BUF
:
154 OUT_PKT3(ring
, CP_INDIRECT_BUFFER_PFD
, 2);
155 OUT_RING(ring
, submit
->cmd
[i
].iova
);
156 OUT_RING(ring
, submit
->cmd
[i
].size
);
162 /* on a320, at least, we seem to need to pad things out to an
163 * even number of qwords to avoid issue w/ CP hanging on wrap-
169 OUT_PKT0(ring
, REG_AXXX_CP_SCRATCH_REG2
, 1);
170 OUT_RING(ring
, submit
->fence
);
172 if (adreno_is_a3xx(adreno_gpu
)) {
173 /* Flush HLSQ lazy updates to make sure there is nothing
174 * pending for indirect loads after the timestamp has
177 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
178 OUT_RING(ring
, HLSQ_FLUSH
);
180 OUT_PKT3(ring
, CP_WAIT_FOR_IDLE
, 1);
181 OUT_RING(ring
, 0x00000000);
184 OUT_PKT3(ring
, CP_EVENT_WRITE
, 3);
185 OUT_RING(ring
, CACHE_FLUSH_TS
);
186 OUT_RING(ring
, rbmemptr(adreno_gpu
, fence
));
187 OUT_RING(ring
, submit
->fence
);
189 /* we could maybe be clever and only CP_COND_EXEC the interrupt: */
190 OUT_PKT3(ring
, CP_INTERRUPT
, 1);
191 OUT_RING(ring
, 0x80000000);
194 if (adreno_is_a3xx(adreno_gpu
)) {
195 /* Dummy set-constant to trigger context rollover */
196 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
197 OUT_RING(ring
, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG
));
198 OUT_RING(ring
, 0x00000000);
202 gpu
->funcs
->flush(gpu
);
207 void adreno_flush(struct msm_gpu
*gpu
)
209 uint32_t wptr
= get_wptr(gpu
->rb
);
211 /* ensure writes to ringbuffer have hit system memory: */
214 gpu_write(gpu
, REG_AXXX_CP_RB_WPTR
, wptr
);
217 void adreno_idle(struct msm_gpu
*gpu
)
219 struct adreno_gpu
*adreno_gpu
= to_adreno_gpu(gpu
);
220 uint32_t rptr
, wptr
= get_wptr(gpu
->rb
);
223 t
= jiffies
+ ADRENO_IDLE_TIMEOUT
;
225 /* then wait for CP to drain ringbuffer: */
227 rptr
= adreno_gpu
->memptrs
->rptr
;
230 } while(time_before(jiffies
, t
));
232 DRM_ERROR("timeout waiting for %s to drain ringbuffer!\n", gpu
->name
);
234 /* TODO maybe we need to reset GPU here to recover from hang? */
237 #ifdef CONFIG_DEBUG_FS
238 void adreno_show(struct msm_gpu
*gpu
, struct seq_file
*m
)
240 struct adreno_gpu
*adreno_gpu
= to_adreno_gpu(gpu
);
242 seq_printf(m
, "revision: %d (%d.%d.%d.%d)\n",
243 adreno_gpu
->info
->revn
, adreno_gpu
->rev
.core
,
244 adreno_gpu
->rev
.major
, adreno_gpu
->rev
.minor
,
245 adreno_gpu
->rev
.patchid
);
247 seq_printf(m
, "fence: %d/%d\n", adreno_gpu
->memptrs
->fence
,
248 gpu
->submitted_fence
);
249 seq_printf(m
, "rptr: %d\n", adreno_gpu
->memptrs
->rptr
);
250 seq_printf(m
, "wptr: %d\n", adreno_gpu
->memptrs
->wptr
);
251 seq_printf(m
, "rb wptr: %d\n", get_wptr(gpu
->rb
));
255 void adreno_wait_ring(struct msm_gpu
*gpu
, uint32_t ndwords
)
257 struct adreno_gpu
*adreno_gpu
= to_adreno_gpu(gpu
);
260 uint32_t size
= gpu
->rb
->size
/ 4;
261 uint32_t wptr
= get_wptr(gpu
->rb
);
262 uint32_t rptr
= adreno_gpu
->memptrs
->rptr
;
263 freedwords
= (rptr
+ (size
- 1) - wptr
) % size
;
264 } while(freedwords
< ndwords
);
267 static const char *iommu_ports
[] = {
268 "gfx3d_user", "gfx3d_priv",
269 "gfx3d1_user", "gfx3d1_priv",
272 static inline bool _rev_match(uint8_t entry
, uint8_t id
)
274 return (entry
== ANY_ID
) || (entry
== id
);
277 int adreno_gpu_init(struct drm_device
*drm
, struct platform_device
*pdev
,
278 struct adreno_gpu
*gpu
, const struct adreno_gpu_funcs
*funcs
,
279 struct adreno_rev rev
)
284 for (i
= 0; i
< ARRAY_SIZE(gpulist
); i
++) {
285 const struct adreno_info
*info
= &gpulist
[i
];
286 if (_rev_match(info
->rev
.core
, rev
.core
) &&
287 _rev_match(info
->rev
.major
, rev
.major
) &&
288 _rev_match(info
->rev
.minor
, rev
.minor
) &&
289 _rev_match(info
->rev
.patchid
, rev
.patchid
)) {
291 gpu
->revn
= info
->revn
;
296 if (i
== ARRAY_SIZE(gpulist
)) {
297 dev_err(drm
->dev
, "Unknown GPU revision: %u.%u.%u.%u\n",
298 rev
.core
, rev
.major
, rev
.minor
, rev
.patchid
);
302 DBG("Found GPU: %s (%u.%u.%u.%u)", gpu
->info
->name
,
303 rev
.core
, rev
.major
, rev
.minor
, rev
.patchid
);
308 ret
= request_firmware(&gpu
->pm4
, gpu
->info
->pm4fw
, drm
->dev
);
310 dev_err(drm
->dev
, "failed to load %s PM4 firmware: %d\n",
311 gpu
->info
->pm4fw
, ret
);
315 ret
= request_firmware(&gpu
->pfp
, gpu
->info
->pfpfw
, drm
->dev
);
317 dev_err(drm
->dev
, "failed to load %s PFP firmware: %d\n",
318 gpu
->info
->pfpfw
, ret
);
322 ret
= msm_gpu_init(drm
, pdev
, &gpu
->base
, &funcs
->base
,
323 gpu
->info
->name
, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
328 ret
= msm_iommu_attach(drm
, gpu
->base
.iommu
,
329 iommu_ports
, ARRAY_SIZE(iommu_ports
));
333 gpu
->memptrs_bo
= msm_gem_new(drm
, sizeof(*gpu
->memptrs
),
335 if (IS_ERR(gpu
->memptrs_bo
)) {
336 ret
= PTR_ERR(gpu
->memptrs_bo
);
337 gpu
->memptrs_bo
= NULL
;
338 dev_err(drm
->dev
, "could not allocate memptrs: %d\n", ret
);
342 gpu
->memptrs
= msm_gem_vaddr_locked(gpu
->memptrs_bo
);
344 dev_err(drm
->dev
, "could not vmap memptrs\n");
348 ret
= msm_gem_get_iova_locked(gpu
->memptrs_bo
, gpu
->base
.id
,
351 dev_err(drm
->dev
, "could not map memptrs: %d\n", ret
);
358 void adreno_gpu_cleanup(struct adreno_gpu
*gpu
)
360 if (gpu
->memptrs_bo
) {
361 if (gpu
->memptrs_iova
)
362 msm_gem_put_iova(gpu
->memptrs_bo
, gpu
->base
.id
);
363 drm_gem_object_unreference(gpu
->memptrs_bo
);
366 release_firmware(gpu
->pm4
);
368 release_firmware(gpu
->pfp
);
369 msm_gpu_cleanup(&gpu
->base
);