drivers/gpu/drm/msm/adreno/adreno_gpu.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "adreno_gpu.h"
  21 #include "msm_gem.h"
  22 #include "msm_mmu.h"
  23
  24 #define RB_SIZE    SZ_32K
  25 #define RB_BLKSIZE 16
  26
  27 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
  28 {
  29         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
  30
  31         switch (param) {
  32         case MSM_PARAM_GPU_ID:
  33                 *value = adreno_gpu->info->revn;
  34                 return 0;
  35         case MSM_PARAM_GMEM_SIZE:
  36                 *value = adreno_gpu->gmem;
  37                 return 0;
  38         case MSM_PARAM_CHIP_ID:
  39                 *value = adreno_gpu->rev.patchid |
  40                                 (adreno_gpu->rev.minor << 8) |
  41                                 (adreno_gpu->rev.major << 16) |
  42                                 (adreno_gpu->rev.core << 24);
  43                 return 0;
  44         case MSM_PARAM_MAX_FREQ:
  45                 *value = adreno_gpu->base.fast_rate;
  46                 return 0;
  47         case MSM_PARAM_TIMESTAMP:
  48                 if (adreno_gpu->funcs->get_timestamp)
  49                         return adreno_gpu->funcs->get_timestamp(gpu, value);
  50                 return -EINVAL;
  51         default:
  52                 DBG("%s: invalid param: %u", gpu->name, param);
  53                 return -EINVAL;
  54         }
  55 }
  56
  57 #define rbmemptr(adreno_gpu, member)  \
  58         ((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))
  59
  60 int adreno_hw_init(struct msm_gpu *gpu)
  61 {
  62         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
  63         int ret;
  64
  65         DBG("%s", gpu->name);
  66
  67         ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova);
  68         if (ret) {
  69                 gpu->rb_iova = 0;
  70                 dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
  71                 return ret;
  72         }
  73
  74         /* Setup REG_CP_RB_CNTL: */
  75         adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
  76                         /* size is log2(quad-words): */
  77                         AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
  78                         AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) |
  79                         (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
  80
  81         /* Setup ringbuffer address: */
  82         adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova);
  83
  84         if (!adreno_is_a430(adreno_gpu))
  85                 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
  86                                                 rbmemptr(adreno_gpu, rptr));
  87
  88         return 0;
  89 }
  90
  91 static uint32_t get_wptr(struct msm_ringbuffer *ring)
  92 {
  93         return ring->cur - ring->start;
  94 }
  95
  96 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */
  97 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu)
  98 {
  99         if (adreno_is_a430(adreno_gpu))
 100                 return adreno_gpu->memptrs->rptr = adreno_gpu_read(
 101                         adreno_gpu, REG_ADRENO_CP_RB_RPTR);
 102         else
 103                 return adreno_gpu->memptrs->rptr;
 104 }
 105
 106 uint32_t adreno_last_fence(struct msm_gpu *gpu)
 107 {
 108         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 109         return adreno_gpu->memptrs->fence;
 110 }
 111
 112 void adreno_recover(struct msm_gpu *gpu)
 113 {
 114         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 115         struct drm_device *dev = gpu->dev;
 116         int ret;
 117
 118         gpu->funcs->pm_suspend(gpu);
 119
 120         /* reset ringbuffer: */
 121         gpu->rb->cur = gpu->rb->start;
 122
 123         /* reset completed fence seqno: */
 124         adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;
 125         adreno_gpu->memptrs->rptr  = 0;
 126         adreno_gpu->memptrs->wptr  = 0;
 127
 128         gpu->funcs->pm_resume(gpu);
 129         ret = gpu->funcs->hw_init(gpu);
 130         if (ret) {
 131                 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
 132                 /* hmm, oh well? */
 133         }
 134 }
 135
 136 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 137                 struct msm_file_private *ctx)
 138 {
 139         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 140         struct msm_drm_private *priv = gpu->dev->dev_private;
 141         struct msm_ringbuffer *ring = gpu->rb;
 142         unsigned i, ibs = 0;
 143
 144         for (i = 0; i < submit->nr_cmds; i++) {
 145                 switch (submit->cmd[i].type) {
 146                 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
 147                         /* ignore IB-targets */
 148                         break;
 149                 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
 150                         /* ignore if there has not been a ctx switch: */
 151                         if (priv->lastctx == ctx)
 152                                 break;
 153                 case MSM_SUBMIT_CMD_BUF:
 154                         OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
 155                                 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
 156                         OUT_RING(ring, submit->cmd[i].iova);
 157                         OUT_RING(ring, submit->cmd[i].size);
 158                         ibs++;
 159                         break;
 160                 }
 161         }
 162
 163         /* on a320, at least, we seem to need to pad things out to an
 164          * even number of qwords to avoid issue w/ CP hanging on wrap-
 165          * around:
 166          */
 167         if (ibs % 2)
 168                 OUT_PKT2(ring);
 169
 170         OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
 171         OUT_RING(ring, submit->fence->seqno);
 172
 173         if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
 174                 /* Flush HLSQ lazy updates to make sure there is nothing
 175                  * pending for indirect loads after the timestamp has
 176                  * passed:
 177                  */
 178                 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 179                 OUT_RING(ring, HLSQ_FLUSH);
 180
 181                 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 182                 OUT_RING(ring, 0x00000000);
 183         }
 184
 185         OUT_PKT3(ring, CP_EVENT_WRITE, 3);
 186         OUT_RING(ring, CACHE_FLUSH_TS);
 187         OUT_RING(ring, rbmemptr(adreno_gpu, fence));
 188         OUT_RING(ring, submit->fence->seqno);
 189
 190         /* we could maybe be clever and only CP_COND_EXEC the interrupt: */
 191         OUT_PKT3(ring, CP_INTERRUPT, 1);
 192         OUT_RING(ring, 0x80000000);
 193
 194         /* Workaround for missing irq issue on 8x16/a306.  Unsure if the
 195          * root cause is a platform issue or some a306 quirk, but this
 196          * keeps things humming along:
 197          */
 198         if (adreno_is_a306(adreno_gpu)) {
 199                 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 200                 OUT_RING(ring, 0x00000000);
 201                 OUT_PKT3(ring, CP_INTERRUPT, 1);
 202                 OUT_RING(ring, 0x80000000);
 203         }
 204
 205 #if 0
 206         if (adreno_is_a3xx(adreno_gpu)) {
 207                 /* Dummy set-constant to trigger context rollover */
 208                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 209                 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
 210                 OUT_RING(ring, 0x00000000);
 211         }
 212 #endif
 213
 214         gpu->funcs->flush(gpu);
 215 }
 216
 217 void adreno_flush(struct msm_gpu *gpu)
 218 {
 219         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 220         uint32_t wptr = get_wptr(gpu->rb);
 221
 222         /* ensure writes to ringbuffer have hit system memory: */
 223         mb();
 224
 225         adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
 226 }
 227
 228 void adreno_idle(struct msm_gpu *gpu)
 229 {
 230         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 231         uint32_t wptr = get_wptr(gpu->rb);
 232         int ret;
 233
 234         /* wait for CP to drain ringbuffer: */
 235         ret = spin_until(get_rptr(adreno_gpu) == wptr);
 236
 237         if (ret)
 238                 DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
 239
 240         /* TODO maybe we need to reset GPU here to recover from hang? */
 241 }
 242
 243 #ifdef CONFIG_DEBUG_FS
 244 void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
 245 {
 246         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 247         int i;
 248
 249         seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
 250                         adreno_gpu->info->revn, adreno_gpu->rev.core,
 251                         adreno_gpu->rev.major, adreno_gpu->rev.minor,
 252                         adreno_gpu->rev.patchid);
 253
 254         seq_printf(m, "fence:    %d/%d\n", adreno_gpu->memptrs->fence,
 255                         gpu->fctx->last_fence);
 256         seq_printf(m, "rptr:     %d\n", get_rptr(adreno_gpu));
 257         seq_printf(m, "wptr:     %d\n", adreno_gpu->memptrs->wptr);
 258         seq_printf(m, "rb wptr:  %d\n", get_wptr(gpu->rb));
 259
 260         gpu->funcs->pm_resume(gpu);
 261
 262         /* dump these out in a form that can be parsed by demsm: */
 263         seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
 264         for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
 265                 uint32_t start = adreno_gpu->registers[i];
 266                 uint32_t end   = adreno_gpu->registers[i+1];
 267                 uint32_t addr;
 268
 269                 for (addr = start; addr <= end; addr++) {
 270                         uint32_t val = gpu_read(gpu, addr);
 271                         seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
 272                 }
 273         }
 274
 275         gpu->funcs->pm_suspend(gpu);
 276 }
 277 #endif
 278
 279 /* Dump common gpu status and scratch registers on any hang, to make
 280  * the hangcheck logs more useful.  The scratch registers seem always
 281  * safe to read when GPU has hung (unlike some other regs, depending
 282  * on how the GPU hung), and they are useful to match up to cmdstream
 283  * dumps when debugging hangs:
 284  */
 285 void adreno_dump_info(struct msm_gpu *gpu)
 286 {
 287         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 288         int i;
 289
 290         printk("revision: %d (%d.%d.%d.%d)\n",
 291                         adreno_gpu->info->revn, adreno_gpu->rev.core,
 292                         adreno_gpu->rev.major, adreno_gpu->rev.minor,
 293                         adreno_gpu->rev.patchid);
 294
 295         printk("fence:    %d/%d\n", adreno_gpu->memptrs->fence,
 296                         gpu->fctx->last_fence);
 297         printk("rptr:     %d\n", get_rptr(adreno_gpu));
 298         printk("wptr:     %d\n", adreno_gpu->memptrs->wptr);
 299         printk("rb wptr:  %d\n", get_wptr(gpu->rb));
 300
 301         for (i = 0; i < 8; i++) {
 302                 printk("CP_SCRATCH_REG%d: %u\n", i,
 303                         gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));
 304         }
 305 }
 306
 307 /* would be nice to not have to duplicate the _show() stuff with printk(): */
 308 void adreno_dump(struct msm_gpu *gpu)
 309 {
 310         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 311         int i;
 312
 313         /* dump these out in a form that can be parsed by demsm: */
 314         printk("IO:region %s 00000000 00020000\n", gpu->name);
 315         for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
 316                 uint32_t start = adreno_gpu->registers[i];
 317                 uint32_t end   = adreno_gpu->registers[i+1];
 318                 uint32_t addr;
 319
 320                 for (addr = start; addr <= end; addr++) {
 321                         uint32_t val = gpu_read(gpu, addr);
 322                         printk("IO:R %08x %08x\n", addr<<2, val);
 323                 }
 324         }
 325 }
 326
 327 static uint32_t ring_freewords(struct msm_gpu *gpu)
 328 {
 329         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 330         uint32_t size = gpu->rb->size / 4;
 331         uint32_t wptr = get_wptr(gpu->rb);
 332         uint32_t rptr = get_rptr(adreno_gpu);
 333         return (rptr + (size - 1) - wptr) % size;
 334 }
 335
 336 void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
 337 {
 338         if (spin_until(ring_freewords(gpu) >= ndwords))
 339                 DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
 340 }
 341
 342 static const char *iommu_ports[] = {
 343                 "gfx3d_user", "gfx3d_priv",
 344                 "gfx3d1_user", "gfx3d1_priv",
 345 };
 346
 347 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 348                 struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs)
 349 {
 350         struct adreno_platform_config *config = pdev->dev.platform_data;
 351         struct msm_gpu *gpu = &adreno_gpu->base;
 352         struct msm_mmu *mmu;
 353         int ret;
 354
 355         adreno_gpu->funcs = funcs;
 356         adreno_gpu->info = adreno_info(config->rev);
 357         adreno_gpu->gmem = adreno_gpu->info->gmem;
 358         adreno_gpu->revn = adreno_gpu->info->revn;
 359         adreno_gpu->rev = config->rev;
 360
 361         gpu->fast_rate = config->fast_rate;
 362         gpu->slow_rate = config->slow_rate;
 363         gpu->bus_freq  = config->bus_freq;
 364 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
 365         gpu->bus_scale_table = config->bus_scale_table;
 366 #endif
 367
 368         DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
 369                         gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
 370
 371         ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
 372                         adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
 373                         RB_SIZE);
 374         if (ret)
 375                 return ret;
 376
 377         ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev);
 378         if (ret) {
 379                 dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n",
 380                                 adreno_gpu->info->pm4fw, ret);
 381                 return ret;
 382         }
 383
 384         ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev);
 385         if (ret) {
 386                 dev_err(drm->dev, "failed to load %s PFP firmware: %d\n",
 387                                 adreno_gpu->info->pfpfw, ret);
 388                 return ret;
 389         }
 390
 391         mmu = gpu->mmu;
 392         if (mmu) {
 393                 ret = mmu->funcs->attach(mmu, iommu_ports,
 394                                 ARRAY_SIZE(iommu_ports));
 395                 if (ret)
 396                         return ret;
 397         }
 398
 399         mutex_lock(&drm->struct_mutex);
 400         adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs),
 401                         MSM_BO_UNCACHED);
 402         mutex_unlock(&drm->struct_mutex);
 403         if (IS_ERR(adreno_gpu->memptrs_bo)) {
 404                 ret = PTR_ERR(adreno_gpu->memptrs_bo);
 405                 adreno_gpu->memptrs_bo = NULL;
 406                 dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
 407                 return ret;
 408         }
 409
 410         adreno_gpu->memptrs = msm_gem_vaddr(adreno_gpu->memptrs_bo);
 411         if (!adreno_gpu->memptrs) {
 412                 dev_err(drm->dev, "could not vmap memptrs\n");
 413                 return -ENOMEM;
 414         }
 415
 416         ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id,
 417                         &adreno_gpu->memptrs_iova);
 418         if (ret) {
 419                 dev_err(drm->dev, "could not map memptrs: %d\n", ret);
 420                 return ret;
 421         }
 422
 423         return 0;
 424 }
 425
 426 void adreno_gpu_cleanup(struct adreno_gpu *gpu)
 427 {
 428         if (gpu->memptrs_bo) {
 429                 if (gpu->memptrs_iova)
 430                         msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);
 431                 drm_gem_object_unreference_unlocked(gpu->memptrs_bo);
 432         }
 433         release_firmware(gpu->pm4);
 434         release_firmware(gpu->pfp);
 435         msm_gpu_cleanup(&gpu->base);
 436 }