2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
23 static struct mdp4_platform_config
*mdp4_get_config(struct platform_device
*dev
);
25 static int mdp4_hw_init(struct msm_kms
*kms
)
27 struct mdp4_kms
*mdp4_kms
= to_mdp4_kms(to_mdp_kms(kms
));
28 struct drm_device
*dev
= mdp4_kms
->dev
;
29 uint32_t version
, major
, minor
, dmap_cfg
, vg_cfg
;
33 pm_runtime_get_sync(dev
->dev
);
35 mdp4_enable(mdp4_kms
);
36 version
= mdp4_read(mdp4_kms
, REG_MDP4_VERSION
);
37 mdp4_disable(mdp4_kms
);
39 major
= FIELD(version
, MDP4_VERSION_MAJOR
);
40 minor
= FIELD(version
, MDP4_VERSION_MINOR
);
42 DBG("found MDP4 version v%d.%d", major
, minor
);
45 dev_err(dev
->dev
, "unexpected MDP version: v%d.%d\n",
51 mdp4_kms
->rev
= minor
;
53 if (mdp4_kms
->rev
> 1) {
54 mdp4_write(mdp4_kms
, REG_MDP4_CS_CONTROLLER0
, 0x0707ffff);
55 mdp4_write(mdp4_kms
, REG_MDP4_CS_CONTROLLER1
, 0x03073f3f);
58 mdp4_write(mdp4_kms
, REG_MDP4_PORTMAP_MODE
, 0x3);
60 /* max read pending cmd config, 3 pending requests: */
61 mdp4_write(mdp4_kms
, REG_MDP4_READ_CNFG
, 0x02222);
63 clk
= clk_get_rate(mdp4_kms
->clk
);
65 if ((mdp4_kms
->rev
>= 1) || (clk
>= 90000000)) {
66 dmap_cfg
= 0x47; /* 16 bytes-burst x 8 req */
67 vg_cfg
= 0x47; /* 16 bytes-burs x 8 req */
69 dmap_cfg
= 0x27; /* 8 bytes-burst x 8 req */
70 vg_cfg
= 0x43; /* 16 bytes-burst x 4 req */
73 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg
, vg_cfg
);
75 mdp4_write(mdp4_kms
, REG_MDP4_DMA_FETCH_CONFIG(DMA_P
), dmap_cfg
);
76 mdp4_write(mdp4_kms
, REG_MDP4_DMA_FETCH_CONFIG(DMA_E
), dmap_cfg
);
78 mdp4_write(mdp4_kms
, REG_MDP4_PIPE_FETCH_CONFIG(VG1
), vg_cfg
);
79 mdp4_write(mdp4_kms
, REG_MDP4_PIPE_FETCH_CONFIG(VG2
), vg_cfg
);
80 mdp4_write(mdp4_kms
, REG_MDP4_PIPE_FETCH_CONFIG(RGB1
), vg_cfg
);
81 mdp4_write(mdp4_kms
, REG_MDP4_PIPE_FETCH_CONFIG(RGB2
), vg_cfg
);
83 if (mdp4_kms
->rev
>= 2)
84 mdp4_write(mdp4_kms
, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD
, 1);
85 mdp4_write(mdp4_kms
, REG_MDP4_LAYERMIXER_IN_CFG
, 0);
87 /* disable CSC matrix / YUV by default: */
88 mdp4_write(mdp4_kms
, REG_MDP4_PIPE_OP_MODE(VG1
), 0);
89 mdp4_write(mdp4_kms
, REG_MDP4_PIPE_OP_MODE(VG2
), 0);
90 mdp4_write(mdp4_kms
, REG_MDP4_DMA_P_OP_MODE
, 0);
91 mdp4_write(mdp4_kms
, REG_MDP4_DMA_S_OP_MODE
, 0);
92 mdp4_write(mdp4_kms
, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
93 mdp4_write(mdp4_kms
, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
95 if (mdp4_kms
->rev
> 1)
96 mdp4_write(mdp4_kms
, REG_MDP4_RESET_STATUS
, 1);
98 dev
->mode_config
.allow_fb_modifiers
= true;
101 pm_runtime_put_sync(dev
->dev
);
106 static void mdp4_prepare_commit(struct msm_kms
*kms
, struct drm_atomic_state
*state
)
108 struct mdp4_kms
*mdp4_kms
= to_mdp4_kms(to_mdp_kms(kms
));
109 int i
, ncrtcs
= state
->dev
->mode_config
.num_crtc
;
111 mdp4_enable(mdp4_kms
);
114 for (i
= 0; i
< ncrtcs
; i
++) {
115 struct drm_crtc
*crtc
= state
->crtcs
[i
];
118 drm_crtc_vblank_get(crtc
);
122 static void mdp4_complete_commit(struct msm_kms
*kms
, struct drm_atomic_state
*state
)
124 struct mdp4_kms
*mdp4_kms
= to_mdp4_kms(to_mdp_kms(kms
));
125 int i
, ncrtcs
= state
->dev
->mode_config
.num_crtc
;
128 for (i
= 0; i
< ncrtcs
; i
++) {
129 struct drm_crtc
*crtc
= state
->crtcs
[i
];
132 drm_crtc_vblank_put(crtc
);
135 mdp4_disable(mdp4_kms
);
138 static void mdp4_wait_for_crtc_commit_done(struct msm_kms
*kms
,
139 struct drm_crtc
*crtc
)
141 mdp4_crtc_wait_for_commit_done(crtc
);
144 static long mdp4_round_pixclk(struct msm_kms
*kms
, unsigned long rate
,
145 struct drm_encoder
*encoder
)
147 /* if we had >1 encoder, we'd need something more clever: */
148 switch (encoder
->encoder_type
) {
149 case DRM_MODE_ENCODER_TMDS
:
150 return mdp4_dtv_round_pixclk(encoder
, rate
);
151 case DRM_MODE_ENCODER_LVDS
:
152 case DRM_MODE_ENCODER_DSI
:
158 static const char * const iommu_ports
[] = {
159 "mdp_port0_cb0", "mdp_port1_cb0",
162 static void mdp4_destroy(struct msm_kms
*kms
)
164 struct mdp4_kms
*mdp4_kms
= to_mdp4_kms(to_mdp_kms(kms
));
165 struct msm_mmu
*mmu
= mdp4_kms
->mmu
;
168 mmu
->funcs
->detach(mmu
, iommu_ports
, ARRAY_SIZE(iommu_ports
));
169 mmu
->funcs
->destroy(mmu
);
172 if (mdp4_kms
->blank_cursor_iova
)
173 msm_gem_put_iova(mdp4_kms
->blank_cursor_bo
, mdp4_kms
->id
);
174 if (mdp4_kms
->blank_cursor_bo
)
175 drm_gem_object_unreference_unlocked(mdp4_kms
->blank_cursor_bo
);
179 static const struct mdp_kms_funcs kms_funcs
= {
181 .hw_init
= mdp4_hw_init
,
182 .irq_preinstall
= mdp4_irq_preinstall
,
183 .irq_postinstall
= mdp4_irq_postinstall
,
184 .irq_uninstall
= mdp4_irq_uninstall
,
186 .enable_vblank
= mdp4_enable_vblank
,
187 .disable_vblank
= mdp4_disable_vblank
,
188 .prepare_commit
= mdp4_prepare_commit
,
189 .complete_commit
= mdp4_complete_commit
,
190 .wait_for_crtc_commit_done
= mdp4_wait_for_crtc_commit_done
,
191 .get_format
= mdp_get_format
,
192 .round_pixclk
= mdp4_round_pixclk
,
193 .destroy
= mdp4_destroy
,
195 .set_irqmask
= mdp4_set_irqmask
,
198 int mdp4_disable(struct mdp4_kms
*mdp4_kms
)
202 clk_disable_unprepare(mdp4_kms
->clk
);
204 clk_disable_unprepare(mdp4_kms
->pclk
);
205 clk_disable_unprepare(mdp4_kms
->lut_clk
);
206 if (mdp4_kms
->axi_clk
)
207 clk_disable_unprepare(mdp4_kms
->axi_clk
);
212 int mdp4_enable(struct mdp4_kms
*mdp4_kms
)
216 clk_prepare_enable(mdp4_kms
->clk
);
218 clk_prepare_enable(mdp4_kms
->pclk
);
219 clk_prepare_enable(mdp4_kms
->lut_clk
);
220 if (mdp4_kms
->axi_clk
)
221 clk_prepare_enable(mdp4_kms
->axi_clk
);
226 static struct device_node
*mdp4_detect_lcdc_panel(struct drm_device
*dev
)
228 struct device_node
*endpoint
, *panel_node
;
229 struct device_node
*np
= dev
->dev
->of_node
;
231 endpoint
= of_graph_get_next_endpoint(np
, NULL
);
233 DBG("no endpoint in MDP4 to fetch LVDS panel\n");
237 /* don't proceed if we have an endpoint but no panel_node tied to it */
238 panel_node
= of_graph_get_remote_port_parent(endpoint
);
240 dev_err(dev
->dev
, "no valid panel node\n");
241 of_node_put(endpoint
);
242 return ERR_PTR(-ENODEV
);
245 of_node_put(endpoint
);
250 static int mdp4_modeset_init_intf(struct mdp4_kms
*mdp4_kms
,
253 struct drm_device
*dev
= mdp4_kms
->dev
;
254 struct msm_drm_private
*priv
= dev
->dev_private
;
255 struct drm_encoder
*encoder
;
256 struct drm_connector
*connector
;
257 struct device_node
*panel_node
;
258 struct drm_encoder
*dsi_encs
[MSM_DSI_ENCODER_NUM
];
263 case DRM_MODE_ENCODER_LVDS
:
266 * - there is no panel node (no need to initialize lcdc
267 * encoder and lvds connector), or
268 * - panel node is a bad pointer
270 panel_node
= mdp4_detect_lcdc_panel(dev
);
271 if (IS_ERR_OR_NULL(panel_node
))
272 return PTR_ERR(panel_node
);
274 encoder
= mdp4_lcdc_encoder_init(dev
, panel_node
);
275 if (IS_ERR(encoder
)) {
276 dev_err(dev
->dev
, "failed to construct LCDC encoder\n");
277 return PTR_ERR(encoder
);
280 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
281 encoder
->possible_crtcs
= 1 << DMA_P
;
283 connector
= mdp4_lvds_connector_init(dev
, panel_node
, encoder
);
284 if (IS_ERR(connector
)) {
285 dev_err(dev
->dev
, "failed to initialize LVDS connector\n");
286 return PTR_ERR(connector
);
289 priv
->encoders
[priv
->num_encoders
++] = encoder
;
290 priv
->connectors
[priv
->num_connectors
++] = connector
;
293 case DRM_MODE_ENCODER_TMDS
:
294 encoder
= mdp4_dtv_encoder_init(dev
);
295 if (IS_ERR(encoder
)) {
296 dev_err(dev
->dev
, "failed to construct DTV encoder\n");
297 return PTR_ERR(encoder
);
300 /* DTV can be hooked to DMA_E: */
301 encoder
->possible_crtcs
= 1 << 1;
304 /* Construct bridge/connector for HDMI: */
305 ret
= msm_hdmi_modeset_init(priv
->hdmi
, dev
, encoder
);
307 dev_err(dev
->dev
, "failed to initialize HDMI: %d\n", ret
);
312 priv
->encoders
[priv
->num_encoders
++] = encoder
;
315 case DRM_MODE_ENCODER_DSI
:
316 /* only DSI1 supported for now */
319 if (!priv
->dsi
[dsi_id
])
322 for (i
= 0; i
< MSM_DSI_ENCODER_NUM
; i
++) {
323 dsi_encs
[i
] = mdp4_dsi_encoder_init(dev
);
324 if (IS_ERR(dsi_encs
[i
])) {
325 ret
= PTR_ERR(dsi_encs
[i
]);
327 "failed to construct DSI encoder: %d\n",
332 /* TODO: Add DMA_S later? */
333 dsi_encs
[i
]->possible_crtcs
= 1 << DMA_P
;
334 priv
->encoders
[priv
->num_encoders
++] = dsi_encs
[i
];
337 ret
= msm_dsi_modeset_init(priv
->dsi
[dsi_id
], dev
, dsi_encs
);
339 dev_err(dev
->dev
, "failed to initialize DSI: %d\n",
346 dev_err(dev
->dev
, "Invalid or unsupported interface\n");
353 static int modeset_init(struct mdp4_kms
*mdp4_kms
)
355 struct drm_device
*dev
= mdp4_kms
->dev
;
356 struct msm_drm_private
*priv
= dev
->dev_private
;
357 struct drm_plane
*plane
;
358 struct drm_crtc
*crtc
;
360 static const enum mdp4_pipe rgb_planes
[] = {
363 static const enum mdp4_pipe vg_planes
[] = {
366 static const enum mdp4_dma mdp4_crtcs
[] = {
369 static const char * const mdp4_crtc_names
[] = {
372 static const int mdp4_intfs
[] = {
373 DRM_MODE_ENCODER_LVDS
,
374 DRM_MODE_ENCODER_DSI
,
375 DRM_MODE_ENCODER_TMDS
,
378 /* construct non-private planes: */
379 for (i
= 0; i
< ARRAY_SIZE(vg_planes
); i
++) {
380 plane
= mdp4_plane_init(dev
, vg_planes
[i
], false);
383 "failed to construct plane for VG%d\n", i
+ 1);
384 ret
= PTR_ERR(plane
);
387 priv
->planes
[priv
->num_planes
++] = plane
;
390 for (i
= 0; i
< ARRAY_SIZE(mdp4_crtcs
); i
++) {
391 plane
= mdp4_plane_init(dev
, rgb_planes
[i
], true);
394 "failed to construct plane for RGB%d\n", i
+ 1);
395 ret
= PTR_ERR(plane
);
399 crtc
= mdp4_crtc_init(dev
, plane
, priv
->num_crtcs
, i
,
402 dev_err(dev
->dev
, "failed to construct crtc for %s\n",
408 priv
->crtcs
[priv
->num_crtcs
++] = crtc
;
412 * we currently set up two relatively fixed paths:
414 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
416 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
418 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
421 for (i
= 0; i
< ARRAY_SIZE(mdp4_intfs
); i
++) {
422 ret
= mdp4_modeset_init_intf(mdp4_kms
, mdp4_intfs
[i
]);
424 dev_err(dev
->dev
, "failed to initialize intf: %d, %d\n",
436 struct msm_kms
*mdp4_kms_init(struct drm_device
*dev
)
438 struct platform_device
*pdev
= dev
->platformdev
;
439 struct mdp4_platform_config
*config
= mdp4_get_config(pdev
);
440 struct mdp4_kms
*mdp4_kms
;
441 struct msm_kms
*kms
= NULL
;
445 mdp4_kms
= kzalloc(sizeof(*mdp4_kms
), GFP_KERNEL
);
447 dev_err(dev
->dev
, "failed to allocate kms\n");
452 mdp_kms_init(&mdp4_kms
->base
, &kms_funcs
);
454 kms
= &mdp4_kms
->base
.base
;
458 mdp4_kms
->mmio
= msm_ioremap(pdev
, NULL
, "MDP4");
459 if (IS_ERR(mdp4_kms
->mmio
)) {
460 ret
= PTR_ERR(mdp4_kms
->mmio
);
464 /* NOTE: driver for this regulator still missing upstream.. use
465 * _get_exclusive() and ignore the error if it does not exist
466 * (and hope that the bootloader left it on for us)
468 mdp4_kms
->vdd
= devm_regulator_get_exclusive(&pdev
->dev
, "vdd");
469 if (IS_ERR(mdp4_kms
->vdd
))
470 mdp4_kms
->vdd
= NULL
;
473 ret
= regulator_enable(mdp4_kms
->vdd
);
475 dev_err(dev
->dev
, "failed to enable regulator vdd: %d\n", ret
);
480 mdp4_kms
->clk
= devm_clk_get(&pdev
->dev
, "core_clk");
481 if (IS_ERR(mdp4_kms
->clk
)) {
482 dev_err(dev
->dev
, "failed to get core_clk\n");
483 ret
= PTR_ERR(mdp4_kms
->clk
);
487 mdp4_kms
->pclk
= devm_clk_get(&pdev
->dev
, "iface_clk");
488 if (IS_ERR(mdp4_kms
->pclk
))
489 mdp4_kms
->pclk
= NULL
;
491 // XXX if (rev >= MDP_REV_42) { ???
492 mdp4_kms
->lut_clk
= devm_clk_get(&pdev
->dev
, "lut_clk");
493 if (IS_ERR(mdp4_kms
->lut_clk
)) {
494 dev_err(dev
->dev
, "failed to get lut_clk\n");
495 ret
= PTR_ERR(mdp4_kms
->lut_clk
);
499 mdp4_kms
->axi_clk
= devm_clk_get(&pdev
->dev
, "mdp_axi_clk");
500 if (IS_ERR(mdp4_kms
->axi_clk
)) {
501 dev_err(dev
->dev
, "failed to get axi_clk\n");
502 ret
= PTR_ERR(mdp4_kms
->axi_clk
);
506 clk_set_rate(mdp4_kms
->clk
, config
->max_clk
);
507 clk_set_rate(mdp4_kms
->lut_clk
, config
->max_clk
);
509 /* make sure things are off before attaching iommu (bootloader could
510 * have left things on, in which case we'll start getting faults if
513 mdp4_enable(mdp4_kms
);
514 mdp4_write(mdp4_kms
, REG_MDP4_DTV_ENABLE
, 0);
515 mdp4_write(mdp4_kms
, REG_MDP4_LCDC_ENABLE
, 0);
516 mdp4_write(mdp4_kms
, REG_MDP4_DSI_ENABLE
, 0);
517 mdp4_disable(mdp4_kms
);
521 mmu
= msm_iommu_new(&pdev
->dev
, config
->iommu
);
526 ret
= mmu
->funcs
->attach(mmu
, iommu_ports
,
527 ARRAY_SIZE(iommu_ports
));
533 dev_info(dev
->dev
, "no iommu, fallback to phys "
534 "contig buffers for scanout\n");
538 mdp4_kms
->id
= msm_register_mmu(dev
, mmu
);
539 if (mdp4_kms
->id
< 0) {
541 dev_err(dev
->dev
, "failed to register mdp4 iommu: %d\n", ret
);
545 ret
= modeset_init(mdp4_kms
);
547 dev_err(dev
->dev
, "modeset_init failed: %d\n", ret
);
551 mutex_lock(&dev
->struct_mutex
);
552 mdp4_kms
->blank_cursor_bo
= msm_gem_new(dev
, SZ_16K
, MSM_BO_WC
);
553 mutex_unlock(&dev
->struct_mutex
);
554 if (IS_ERR(mdp4_kms
->blank_cursor_bo
)) {
555 ret
= PTR_ERR(mdp4_kms
->blank_cursor_bo
);
556 dev_err(dev
->dev
, "could not allocate blank-cursor bo: %d\n", ret
);
557 mdp4_kms
->blank_cursor_bo
= NULL
;
561 ret
= msm_gem_get_iova(mdp4_kms
->blank_cursor_bo
, mdp4_kms
->id
,
562 &mdp4_kms
->blank_cursor_iova
);
564 dev_err(dev
->dev
, "could not pin blank-cursor bo: %d\n", ret
);
568 dev
->mode_config
.min_width
= 0;
569 dev
->mode_config
.min_height
= 0;
570 dev
->mode_config
.max_width
= 2048;
571 dev
->mode_config
.max_height
= 2048;
581 static struct mdp4_platform_config
*mdp4_get_config(struct platform_device
*dev
)
583 static struct mdp4_platform_config config
= {};
585 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
586 config
.max_clk
= 266667000;
587 config
.iommu
= iommu_domain_alloc(&platform_bus_type
);