2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __MDP4_KMS_H__
19 #define __MDP4_KMS_H__
23 #include "mdp/mdp_kms.h"
26 #include "drm_panel.h"
31 struct drm_device
*dev
;
35 /* mapper-id used to request GEM buffer mapped for scanout: */
40 struct regulator
*vdd
;
48 struct mdp_irq error_handler
;
50 /* empty/blank cursor bo to use when cursor is "disabled" */
51 struct drm_gem_object
*blank_cursor_bo
;
52 uint32_t blank_cursor_iova
;
54 #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
56 /* platform config data (ie. from DT, or pdata) */
57 struct mdp4_platform_config
{
58 struct iommu_domain
*iommu
;
62 static inline void mdp4_write(struct mdp4_kms
*mdp4_kms
, u32 reg
, u32 data
)
64 msm_writel(data
, mdp4_kms
->mmio
+ reg
);
67 static inline u32
mdp4_read(struct mdp4_kms
*mdp4_kms
, u32 reg
)
69 return msm_readl(mdp4_kms
->mmio
+ reg
);
72 static inline uint32_t pipe2flush(enum mdp4_pipe pipe
)
75 case VG1
: return MDP4_OVERLAY_FLUSH_VG1
;
76 case VG2
: return MDP4_OVERLAY_FLUSH_VG2
;
77 case RGB1
: return MDP4_OVERLAY_FLUSH_RGB1
;
78 case RGB2
: return MDP4_OVERLAY_FLUSH_RGB2
;
83 static inline uint32_t ovlp2flush(int ovlp
)
86 case 0: return MDP4_OVERLAY_FLUSH_OVLP0
;
87 case 1: return MDP4_OVERLAY_FLUSH_OVLP1
;
92 static inline uint32_t dma2irq(enum mdp4_dma dma
)
95 case DMA_P
: return MDP4_IRQ_DMA_P_DONE
;
96 case DMA_S
: return MDP4_IRQ_DMA_S_DONE
;
97 case DMA_E
: return MDP4_IRQ_DMA_E_DONE
;
102 static inline uint32_t dma2err(enum mdp4_dma dma
)
105 case DMA_P
: return MDP4_IRQ_PRIMARY_INTF_UDERRUN
;
106 case DMA_S
: return 0; // ???
107 case DMA_E
: return MDP4_IRQ_EXTERNAL_INTF_UDERRUN
;
112 static inline uint32_t mixercfg(uint32_t mixer_cfg
, int mixer
,
113 enum mdp4_pipe pipe
, enum mdp_mixer_stage_id stage
)
117 mixer_cfg
&= ~(MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK
|
118 MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1
);
119 mixer_cfg
|= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage
) |
120 COND(mixer
== 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1
);
123 mixer_cfg
&= ~(MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK
|
124 MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1
);
125 mixer_cfg
|= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage
) |
126 COND(mixer
== 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1
);
129 mixer_cfg
&= ~(MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK
|
130 MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1
);
131 mixer_cfg
|= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage
) |
132 COND(mixer
== 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1
);
135 mixer_cfg
&= ~(MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK
|
136 MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1
);
137 mixer_cfg
|= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage
) |
138 COND(mixer
== 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1
);
141 mixer_cfg
&= ~(MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK
|
142 MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1
);
143 mixer_cfg
|= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage
) |
144 COND(mixer
== 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1
);
147 mixer_cfg
&= ~(MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK
|
148 MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1
);
149 mixer_cfg
|= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage
) |
150 COND(mixer
== 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1
);
153 mixer_cfg
&= ~(MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK
|
154 MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1
);
155 mixer_cfg
|= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage
) |
156 COND(mixer
== 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1
);
159 WARN(1, "invalid pipe");
166 int mdp4_disable(struct mdp4_kms
*mdp4_kms
);
167 int mdp4_enable(struct mdp4_kms
*mdp4_kms
);
169 void mdp4_set_irqmask(struct mdp_kms
*mdp_kms
, uint32_t irqmask
,
170 uint32_t old_irqmask
);
171 void mdp4_irq_preinstall(struct msm_kms
*kms
);
172 int mdp4_irq_postinstall(struct msm_kms
*kms
);
173 void mdp4_irq_uninstall(struct msm_kms
*kms
);
174 irqreturn_t
mdp4_irq(struct msm_kms
*kms
);
175 int mdp4_enable_vblank(struct msm_kms
*kms
, struct drm_crtc
*crtc
);
176 void mdp4_disable_vblank(struct msm_kms
*kms
, struct drm_crtc
*crtc
);
178 static inline uint32_t mdp4_pipe_caps(enum mdp4_pipe pipe
)
185 return MDP_PIPE_CAP_HFLIP
| MDP_PIPE_CAP_VFLIP
|
186 MDP_PIPE_CAP_SCALE
| MDP_PIPE_CAP_CSC
;
190 return MDP_PIPE_CAP_SCALE
;
196 enum mdp4_pipe
mdp4_plane_pipe(struct drm_plane
*plane
);
197 struct drm_plane
*mdp4_plane_init(struct drm_device
*dev
,
198 enum mdp4_pipe pipe_id
, bool private_plane
);
200 uint32_t mdp4_crtc_vblank(struct drm_crtc
*crtc
);
201 void mdp4_crtc_set_config(struct drm_crtc
*crtc
, uint32_t config
);
202 void mdp4_crtc_set_intf(struct drm_crtc
*crtc
, enum mdp4_intf intf
, int mixer
);
203 void mdp4_crtc_wait_for_commit_done(struct drm_crtc
*crtc
);
204 struct drm_crtc
*mdp4_crtc_init(struct drm_device
*dev
,
205 struct drm_plane
*plane
, int id
, int ovlp_id
,
206 enum mdp4_dma dma_id
);
208 long mdp4_dtv_round_pixclk(struct drm_encoder
*encoder
, unsigned long rate
);
209 struct drm_encoder
*mdp4_dtv_encoder_init(struct drm_device
*dev
);
211 long mdp4_lcdc_round_pixclk(struct drm_encoder
*encoder
, unsigned long rate
);
212 struct drm_encoder
*mdp4_lcdc_encoder_init(struct drm_device
*dev
,
213 struct device_node
*panel_node
);
215 struct drm_connector
*mdp4_lvds_connector_init(struct drm_device
*dev
,
216 struct device_node
*panel_node
, struct drm_encoder
*encoder
);
218 #ifdef CONFIG_DRM_MSM_DSI
219 struct drm_encoder
*mdp4_dsi_encoder_init(struct drm_device
*dev
);
221 static inline struct drm_encoder
*mdp4_dsi_encoder_init(struct drm_device
*dev
)
223 return ERR_PTR(-ENODEV
);
227 #ifdef CONFIG_COMMON_CLK
228 struct clk
*mpd4_lvds_pll_init(struct drm_device
*dev
);
230 static inline struct clk
*mpd4_lvds_pll_init(struct drm_device
*dev
)
232 return ERR_PTR(-ENODEV
);
236 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
237 static inline int match_dev_name(struct device
*dev
, void *data
)
239 return !strcmp(dev_name(dev
), data
);
241 /* bus scaling data is associated with extra pointless platform devices,
242 * "dtv", etc.. this is a bit of a hack, but we need a way for encoders
243 * to find their pdata to make the bus-scaling stuff work.
245 static inline void *mdp4_find_pdata(const char *devname
)
248 dev
= bus_find_device(&platform_bus_type
, NULL
,
249 (void *)devname
, match_dev_name
);
250 return dev
? dev
->platform_data
: NULL
;
254 #endif /* __MDP4_KMS_H__ */