drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/irqdomain.h>
  19 #include <linux/irq.h>
  20
  21 #include "msm_drv.h"
  22 #include "mdp5_kms.h"
  23
  24 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask)
  25 {
  26         mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask);
  27 }
  28
  29 static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
  30 {
  31         DRM_ERROR("errors: %08x\n", irqstatus);
  32 }
  33
  34 void mdp5_irq_preinstall(struct msm_kms *kms)
  35 {
  36         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
  37         mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff);
  38 }
  39
  40 int mdp5_irq_postinstall(struct msm_kms *kms)
  41 {
  42         struct mdp_kms *mdp_kms = to_mdp_kms(kms);
  43         struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
  44         struct mdp_irq *error_handler = &mdp5_kms->error_handler;
  45
  46         error_handler->irq = mdp5_irq_error_handler;
  47         error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN |
  48                         MDP5_IRQ_INTF1_UNDER_RUN |
  49                         MDP5_IRQ_INTF2_UNDER_RUN |
  50                         MDP5_IRQ_INTF3_UNDER_RUN;
  51
  52         mdp_irq_register(mdp_kms, error_handler);
  53
  54         return 0;
  55 }
  56
  57 void mdp5_irq_uninstall(struct msm_kms *kms)
  58 {
  59         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
  60         mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
  61 }
  62
  63 static void mdp5_irq_mdp(struct mdp_kms *mdp_kms)
  64 {
  65         struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
  66         struct drm_device *dev = mdp5_kms->dev;
  67         struct msm_drm_private *priv = dev->dev_private;
  68         unsigned int id;
  69         uint32_t status;
  70
  71         status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS);
  72         mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status);
  73
  74         VERB("status=%08x", status);
  75
  76         mdp_dispatch_irqs(mdp_kms, status);
  77
  78         for (id = 0; id < priv->num_crtcs; id++)
  79                 if (status & mdp5_crtc_vblank(priv->crtcs[id]))
  80                         drm_handle_vblank(dev, id);
  81 }
  82
  83 irqreturn_t mdp5_irq(struct msm_kms *kms)
  84 {
  85         struct mdp_kms *mdp_kms = to_mdp_kms(kms);
  86         struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
  87         uint32_t intr;
  88
  89         intr = mdp5_read(mdp5_kms, REG_MDP5_HW_INTR_STATUS);
  90
  91         VERB("intr=%08x", intr);
  92
  93         if (intr & MDP5_HW_INTR_STATUS_INTR_MDP) {
  94                 mdp5_irq_mdp(mdp_kms);
  95                 intr &= ~MDP5_HW_INTR_STATUS_INTR_MDP;
  96         }
  97
  98         while (intr) {
  99                 irq_hw_number_t hwirq = fls(intr) - 1;
 100                 generic_handle_irq(irq_find_mapping(
 101                                 mdp5_kms->irqcontroller.domain, hwirq));
 102                 intr &= ~(1 << hwirq);
 103         }
 104
 105         return IRQ_HANDLED;
 106 }
 107
 108 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
 109 {
 110         mdp_update_vblank_mask(to_mdp_kms(kms),
 111                         mdp5_crtc_vblank(crtc), true);
 112         return 0;
 113 }
 114
 115 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
 116 {
 117         mdp_update_vblank_mask(to_mdp_kms(kms),
 118                         mdp5_crtc_vblank(crtc), false);
 119 }
 120
 121 /*
 122  * interrupt-controller implementation, so sub-blocks (hdmi/eDP/dsi/etc)
 123  * can register to get their irq's delivered
 124  */
 125
 126 #define VALID_IRQS  (MDP5_HW_INTR_STATUS_INTR_DSI0 | \
 127                 MDP5_HW_INTR_STATUS_INTR_DSI1 | \
 128                 MDP5_HW_INTR_STATUS_INTR_HDMI | \
 129                 MDP5_HW_INTR_STATUS_INTR_EDP)
 130
 131 static void mdp5_hw_mask_irq(struct irq_data *irqd)
 132 {
 133         struct mdp5_kms *mdp5_kms = irq_data_get_irq_chip_data(irqd);
 134         smp_mb__before_atomic();
 135         clear_bit(irqd->hwirq, &mdp5_kms->irqcontroller.enabled_mask);
 136         smp_mb__after_atomic();
 137 }
 138
 139 static void mdp5_hw_unmask_irq(struct irq_data *irqd)
 140 {
 141         struct mdp5_kms *mdp5_kms = irq_data_get_irq_chip_data(irqd);
 142         smp_mb__before_atomic();
 143         set_bit(irqd->hwirq, &mdp5_kms->irqcontroller.enabled_mask);
 144         smp_mb__after_atomic();
 145 }
 146
 147 static struct irq_chip mdp5_hw_irq_chip = {
 148         .name           = "mdp5",
 149         .irq_mask       = mdp5_hw_mask_irq,
 150         .irq_unmask     = mdp5_hw_unmask_irq,
 151 };
 152
 153 static int mdp5_hw_irqdomain_map(struct irq_domain *d,
 154                 unsigned int irq, irq_hw_number_t hwirq)
 155 {
 156         struct mdp5_kms *mdp5_kms = d->host_data;
 157
 158         if (!(VALID_IRQS & (1 << hwirq)))
 159                 return -EPERM;
 160
 161         irq_set_chip_and_handler(irq, &mdp5_hw_irq_chip, handle_level_irq);
 162         irq_set_chip_data(irq, mdp5_kms);
 163         set_irq_flags(irq, IRQF_VALID);
 164
 165         return 0;
 166 }
 167
 168 static struct irq_domain_ops mdp5_hw_irqdomain_ops = {
 169         .map = mdp5_hw_irqdomain_map,
 170         .xlate = irq_domain_xlate_onecell,
 171 };
 172
 173
 174 int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms)
 175 {
 176         struct device *dev = mdp5_kms->dev->dev;
 177         struct irq_domain *d;
 178
 179         d = irq_domain_add_linear(dev->of_node, 32,
 180                         &mdp5_hw_irqdomain_ops, mdp5_kms);
 181         if (!d) {
 182                 dev_err(dev, "mdp5 irq domain add failed\n");
 183                 return -ENXIO;
 184         }
 185
 186         mdp5_kms->irqcontroller.enabled_mask = 0;
 187         mdp5_kms->irqcontroller.domain = d;
 188
 189         return 0;
 190 }
 191
 192 void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms)
 193 {
 194         if (mdp5_kms->irqcontroller.domain) {
 195                 irq_domain_remove(mdp5_kms->irqcontroller.domain);
 196                 mdp5_kms->irqcontroller.domain = NULL;
 197         }
 198 }