drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c

   1 /*
   2  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19
  20 #include "msm_drv.h"
  21 #include "msm_mmu.h"
  22 #include "mdp5_kms.h"
  23
  24 static const char *iommu_ports[] = {
  25                 "mdp_0",
  26 };
  27
  28 static int mdp5_hw_init(struct msm_kms *kms)
  29 {
  30         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
  31         struct drm_device *dev = mdp5_kms->dev;
  32         unsigned long flags;
  33
  34         pm_runtime_get_sync(dev->dev);
  35
  36         /* Magic unknown register writes:
  37          *
  38          *    W VBIF:0x004 00000001      (mdss_mdp.c:839)
  39          *    W MDP5:0x2e0 0xe9          (mdss_mdp.c:839)
  40          *    W MDP5:0x2e4 0x55          (mdss_mdp.c:839)
  41          *    W MDP5:0x3ac 0xc0000ccc    (mdss_mdp.c:839)
  42          *    W MDP5:0x3b4 0xc0000ccc    (mdss_mdp.c:839)
  43          *    W MDP5:0x3bc 0xcccccc      (mdss_mdp.c:839)
  44          *    W MDP5:0x4a8 0xcccc0c0     (mdss_mdp.c:839)
  45          *    W MDP5:0x4b0 0xccccc0c0    (mdss_mdp.c:839)
  46          *    W MDP5:0x4b8 0xccccc000    (mdss_mdp.c:839)
  47          *
  48          * Downstream fbdev driver gets these register offsets/values
  49          * from DT.. not really sure what these registers are or if
  50          * different values for different boards/SoC's, etc.  I guess
  51          * they are the golden registers.
  52          *
  53          * Not setting these does not seem to cause any problem.  But
  54          * we may be getting lucky with the bootloader initializing
  55          * them for us.  OTOH, if we can always count on the bootloader
  56          * setting the golden registers, then perhaps we don't need to
  57          * care.
  58          */
  59
  60         spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
  61         mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
  62         spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
  63
  64         mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
  65
  66         pm_runtime_put_sync(dev->dev);
  67
  68         return 0;
  69 }
  70
  71 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
  72                 struct drm_encoder *encoder)
  73 {
  74         return rate;
  75 }
  76
  77 static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file)
  78 {
  79         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
  80         struct msm_drm_private *priv = mdp5_kms->dev->dev_private;
  81         unsigned i;
  82
  83         for (i = 0; i < priv->num_crtcs; i++)
  84                 mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file);
  85 }
  86
  87 static void mdp5_destroy(struct msm_kms *kms)
  88 {
  89         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
  90         struct msm_mmu *mmu = mdp5_kms->mmu;
  91
  92         mdp5_irq_domain_fini(mdp5_kms);
  93
  94         if (mmu) {
  95                 mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
  96                 mmu->funcs->destroy(mmu);
  97         }
  98
  99         if (mdp5_kms->ctlm)
 100                 mdp5_ctlm_destroy(mdp5_kms->ctlm);
 101         if (mdp5_kms->smp)
 102                 mdp5_smp_destroy(mdp5_kms->smp);
 103         if (mdp5_kms->cfg)
 104                 mdp5_cfg_destroy(mdp5_kms->cfg);
 105
 106         kfree(mdp5_kms);
 107 }
 108
 109 static const struct mdp_kms_funcs kms_funcs = {
 110         .base = {
 111                 .hw_init         = mdp5_hw_init,
 112                 .irq_preinstall  = mdp5_irq_preinstall,
 113                 .irq_postinstall = mdp5_irq_postinstall,
 114                 .irq_uninstall   = mdp5_irq_uninstall,
 115                 .irq             = mdp5_irq,
 116                 .enable_vblank   = mdp5_enable_vblank,
 117                 .disable_vblank  = mdp5_disable_vblank,
 118                 .get_format      = mdp_get_format,
 119                 .round_pixclk    = mdp5_round_pixclk,
 120                 .preclose        = mdp5_preclose,
 121                 .destroy         = mdp5_destroy,
 122         },
 123         .set_irqmask         = mdp5_set_irqmask,
 124 };
 125
 126 int mdp5_disable(struct mdp5_kms *mdp5_kms)
 127 {
 128         DBG("");
 129
 130         clk_disable_unprepare(mdp5_kms->ahb_clk);
 131         clk_disable_unprepare(mdp5_kms->axi_clk);
 132         clk_disable_unprepare(mdp5_kms->core_clk);
 133         clk_disable_unprepare(mdp5_kms->lut_clk);
 134
 135         return 0;
 136 }
 137
 138 int mdp5_enable(struct mdp5_kms *mdp5_kms)
 139 {
 140         DBG("");
 141
 142         clk_prepare_enable(mdp5_kms->ahb_clk);
 143         clk_prepare_enable(mdp5_kms->axi_clk);
 144         clk_prepare_enable(mdp5_kms->core_clk);
 145         clk_prepare_enable(mdp5_kms->lut_clk);
 146
 147         return 0;
 148 }
 149
 150 static int modeset_init(struct mdp5_kms *mdp5_kms)
 151 {
 152         static const enum mdp5_pipe crtcs[] = {
 153                         SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
 154         };
 155         static const enum mdp5_pipe pub_planes[] = {
 156                         SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
 157         };
 158         struct drm_device *dev = mdp5_kms->dev;
 159         struct msm_drm_private *priv = dev->dev_private;
 160         struct drm_encoder *encoder;
 161         const struct mdp5_cfg_hw *hw_cfg;
 162         int i, ret;
 163
 164         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 165
 166         /* register our interrupt-controller for hdmi/eDP/dsi/etc
 167          * to use for irqs routed through mdp:
 168          */
 169         ret = mdp5_irq_domain_init(mdp5_kms);
 170         if (ret)
 171                 goto fail;
 172
 173         /* construct CRTCs and their private planes: */
 174         for (i = 0; i < hw_cfg->pipe_rgb.count; i++) {
 175                 struct drm_plane *plane;
 176                 struct drm_crtc *crtc;
 177
 178                 plane = mdp5_plane_init(dev, crtcs[i], true,
 179                                 hw_cfg->pipe_rgb.base[i]);
 180                 if (IS_ERR(plane)) {
 181                         ret = PTR_ERR(plane);
 182                         dev_err(dev->dev, "failed to construct plane for %s (%d)\n",
 183                                         pipe2name(crtcs[i]), ret);
 184                         goto fail;
 185                 }
 186
 187                 crtc  = mdp5_crtc_init(dev, plane, i);
 188                 if (IS_ERR(crtc)) {
 189                         ret = PTR_ERR(crtc);
 190                         dev_err(dev->dev, "failed to construct crtc for %s (%d)\n",
 191                                         pipe2name(crtcs[i]), ret);
 192                         goto fail;
 193                 }
 194                 priv->crtcs[priv->num_crtcs++] = crtc;
 195         }
 196
 197         /* Construct public planes: */
 198         for (i = 0; i < hw_cfg->pipe_vig.count; i++) {
 199                 struct drm_plane *plane;
 200
 201                 plane = mdp5_plane_init(dev, pub_planes[i], false,
 202                                 hw_cfg->pipe_vig.base[i]);
 203                 if (IS_ERR(plane)) {
 204                         ret = PTR_ERR(plane);
 205                         dev_err(dev->dev, "failed to construct %s plane: %d\n",
 206                                         pipe2name(pub_planes[i]), ret);
 207                         goto fail;
 208                 }
 209         }
 210
 211         /* Construct encoder for HDMI: */
 212         encoder = mdp5_encoder_init(dev, 3, INTF_HDMI);
 213         if (IS_ERR(encoder)) {
 214                 dev_err(dev->dev, "failed to construct encoder\n");
 215                 ret = PTR_ERR(encoder);
 216                 goto fail;
 217         }
 218
 219         encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;;
 220         priv->encoders[priv->num_encoders++] = encoder;
 221
 222         /* Construct bridge/connector for HDMI: */
 223         if (priv->hdmi) {
 224                 ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
 225                 if (ret) {
 226                         dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
 227                         goto fail;
 228                 }
 229         }
 230
 231         return 0;
 232
 233 fail:
 234         return ret;
 235 }
 236
 237 static void read_hw_revision(struct mdp5_kms *mdp5_kms,
 238                 uint32_t *major, uint32_t *minor)
 239 {
 240         uint32_t version;
 241
 242         mdp5_enable(mdp5_kms);
 243         version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION);
 244         mdp5_disable(mdp5_kms);
 245
 246         *major = FIELD(version, MDP5_MDP_VERSION_MAJOR);
 247         *minor = FIELD(version, MDP5_MDP_VERSION_MINOR);
 248
 249         DBG("MDP5 version v%d.%d", *major, *minor);
 250 }
 251
 252 static int get_clk(struct platform_device *pdev, struct clk **clkp,
 253                 const char *name)
 254 {
 255         struct device *dev = &pdev->dev;
 256         struct clk *clk = devm_clk_get(dev, name);
 257         if (IS_ERR(clk)) {
 258                 dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
 259                 return PTR_ERR(clk);
 260         }
 261         *clkp = clk;
 262         return 0;
 263 }
 264
 265 struct msm_kms *mdp5_kms_init(struct drm_device *dev)
 266 {
 267         struct platform_device *pdev = dev->platformdev;
 268         struct mdp5_cfg *config;
 269         struct mdp5_kms *mdp5_kms;
 270         struct msm_kms *kms = NULL;
 271         struct msm_mmu *mmu;
 272         uint32_t major, minor;
 273         int i, ret;
 274
 275         mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);
 276         if (!mdp5_kms) {
 277                 dev_err(dev->dev, "failed to allocate kms\n");
 278                 ret = -ENOMEM;
 279                 goto fail;
 280         }
 281
 282         spin_lock_init(&mdp5_kms->resource_lock);
 283
 284         mdp_kms_init(&mdp5_kms->base, &kms_funcs);
 285
 286         kms = &mdp5_kms->base.base;
 287
 288         mdp5_kms->dev = dev;
 289
 290         mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
 291         if (IS_ERR(mdp5_kms->mmio)) {
 292                 ret = PTR_ERR(mdp5_kms->mmio);
 293                 goto fail;
 294         }
 295
 296         mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
 297         if (IS_ERR(mdp5_kms->vbif)) {
 298                 ret = PTR_ERR(mdp5_kms->vbif);
 299                 goto fail;
 300         }
 301
 302         mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
 303         if (IS_ERR(mdp5_kms->vdd)) {
 304                 ret = PTR_ERR(mdp5_kms->vdd);
 305                 goto fail;
 306         }
 307
 308         ret = regulator_enable(mdp5_kms->vdd);
 309         if (ret) {
 310                 dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
 311                 goto fail;
 312         }
 313
 314         ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk");
 315         if (ret)
 316                 goto fail;
 317         ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk");
 318         if (ret)
 319                 goto fail;
 320         ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src");
 321         if (ret)
 322                 goto fail;
 323         ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk");
 324         if (ret)
 325                 goto fail;
 326         ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk");
 327         if (ret)
 328                 goto fail;
 329         ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk");
 330         if (ret)
 331                 goto fail;
 332
 333         /* we need to set a default rate before enabling.  Set a safe
 334          * rate first, then figure out hw revision, and then set a
 335          * more optimal rate:
 336          */
 337         clk_set_rate(mdp5_kms->src_clk, 200000000);
 338
 339         read_hw_revision(mdp5_kms, &major, &minor);
 340
 341         mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
 342         if (IS_ERR(mdp5_kms->cfg)) {
 343                 ret = PTR_ERR(mdp5_kms->cfg);
 344                 mdp5_kms->cfg = NULL;
 345                 goto fail;
 346         }
 347
 348         config = mdp5_cfg_get_config(mdp5_kms->cfg);
 349
 350         /* TODO: compute core clock rate at runtime */
 351         clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk);
 352
 353         mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp);
 354         if (IS_ERR(mdp5_kms->smp)) {
 355                 ret = PTR_ERR(mdp5_kms->smp);
 356                 mdp5_kms->smp = NULL;
 357                 goto fail;
 358         }
 359
 360         mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, config->hw);
 361         if (IS_ERR(mdp5_kms->ctlm)) {
 362                 ret = PTR_ERR(mdp5_kms->ctlm);
 363                 mdp5_kms->ctlm = NULL;
 364                 goto fail;
 365         }
 366
 367         /* make sure things are off before attaching iommu (bootloader could
 368          * have left things on, in which case we'll start getting faults if
 369          * we don't disable):
 370          */
 371         mdp5_enable(mdp5_kms);
 372         for (i = 0; i < config->hw->intf.count; i++)
 373                 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
 374         mdp5_disable(mdp5_kms);
 375         mdelay(16);
 376
 377         if (config->platform.iommu) {
 378                 mmu = msm_iommu_new(&pdev->dev, config->platform.iommu);
 379                 if (IS_ERR(mmu)) {
 380                         ret = PTR_ERR(mmu);
 381                         dev_err(dev->dev, "failed to init iommu: %d\n", ret);
 382                         goto fail;
 383                 }
 384
 385                 ret = mmu->funcs->attach(mmu, iommu_ports,
 386                                 ARRAY_SIZE(iommu_ports));
 387                 if (ret) {
 388                         dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
 389                         mmu->funcs->destroy(mmu);
 390                         goto fail;
 391                 }
 392         } else {
 393                 dev_info(dev->dev, "no iommu, fallback to phys "
 394                                 "contig buffers for scanout\n");
 395                 mmu = NULL;
 396         }
 397         mdp5_kms->mmu = mmu;
 398
 399         mdp5_kms->id = msm_register_mmu(dev, mmu);
 400         if (mdp5_kms->id < 0) {
 401                 ret = mdp5_kms->id;
 402                 dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret);
 403                 goto fail;
 404         }
 405
 406         ret = modeset_init(mdp5_kms);
 407         if (ret) {
 408                 dev_err(dev->dev, "modeset_init failed: %d\n", ret);
 409                 goto fail;
 410         }
 411
 412         return kms;
 413
 414 fail:
 415         if (kms)
 416                 mdp5_destroy(kms);
 417         return ERR_PTR(ret);
 418 }