drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __MDP5_KMS_H__
  19 #define __MDP5_KMS_H__
  20
  21 #include "msm_drv.h"
  22 #include "msm_kms.h"
  23 #include "mdp/mdp_kms.h"
  24 #include "mdp5.xml.h"
  25 #include "mdp5_smp.h"
  26
  27 struct mdp5_kms {
  28         struct mdp_kms base;
  29
  30         struct drm_device *dev;
  31
  32         int rev;
  33
  34         /* mapper-id used to request GEM buffer mapped for scanout: */
  35         int id;
  36
  37         /* for tracking smp allocation amongst pipes: */
  38         mdp5_smp_state_t smp_state;
  39         struct mdp5_client_smp_state smp_client_state[CID_MAX];
  40         int smp_blk_cnt;
  41
  42         /* io/register spaces: */
  43         void __iomem *mmio, *vbif;
  44
  45         struct regulator *vdd;
  46
  47         struct clk *axi_clk;
  48         struct clk *ahb_clk;
  49         struct clk *src_clk;
  50         struct clk *core_clk;
  51         struct clk *lut_clk;
  52         struct clk *vsync_clk;
  53
  54         struct hdmi *hdmi;
  55
  56         struct mdp_irq error_handler;
  57 };
  58 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
  59
  60 /* platform config data (ie. from DT, or pdata) */
  61 struct mdp5_platform_config {
  62         struct iommu_domain *iommu;
  63         uint32_t max_clk;
  64         int smp_blk_cnt;
  65 };
  66
  67 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
  68 {
  69         msm_writel(data, mdp5_kms->mmio + reg);
  70 }
  71
  72 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
  73 {
  74         return msm_readl(mdp5_kms->mmio + reg);
  75 }
  76
  77 static inline const char *pipe2name(enum mdp5_pipe pipe)
  78 {
  79         static const char *names[] = {
  80 #define NAME(n) [SSPP_ ## n] = #n
  81                 NAME(VIG0), NAME(VIG1), NAME(VIG2),
  82                 NAME(RGB0), NAME(RGB1), NAME(RGB2),
  83                 NAME(DMA0), NAME(DMA1),
  84 #undef NAME
  85         };
  86         return names[pipe];
  87 }
  88
  89 static inline uint32_t pipe2flush(enum mdp5_pipe pipe)
  90 {
  91         switch (pipe) {
  92         case SSPP_VIG0: return MDP5_CTL_FLUSH_VIG0;
  93         case SSPP_VIG1: return MDP5_CTL_FLUSH_VIG1;
  94         case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2;
  95         case SSPP_RGB0: return MDP5_CTL_FLUSH_RGB0;
  96         case SSPP_RGB1: return MDP5_CTL_FLUSH_RGB1;
  97         case SSPP_RGB2: return MDP5_CTL_FLUSH_RGB2;
  98         case SSPP_DMA0: return MDP5_CTL_FLUSH_DMA0;
  99         case SSPP_DMA1: return MDP5_CTL_FLUSH_DMA1;
 100         default:        return 0;
 101         }
 102 }
 103
 104 static inline int pipe2nclients(enum mdp5_pipe pipe)
 105 {
 106         switch (pipe) {
 107         case SSPP_RGB0:
 108         case SSPP_RGB1:
 109         case SSPP_RGB2:
 110                 return 1;
 111         default:
 112                 return 3;
 113         }
 114 }
 115
 116 static inline enum mdp5_client_id pipe2client(enum mdp5_pipe pipe, int plane)
 117 {
 118         WARN_ON(plane >= pipe2nclients(pipe));
 119         switch (pipe) {
 120         case SSPP_VIG0: return CID_VIG0_Y + plane;
 121         case SSPP_VIG1: return CID_VIG1_Y + plane;
 122         case SSPP_VIG2: return CID_VIG2_Y + plane;
 123         case SSPP_RGB0: return CID_RGB0;
 124         case SSPP_RGB1: return CID_RGB1;
 125         case SSPP_RGB2: return CID_RGB2;
 126         case SSPP_DMA0: return CID_DMA0_Y + plane;
 127         case SSPP_DMA1: return CID_DMA1_Y + plane;
 128         default:        return CID_UNUSED;
 129         }
 130 }
 131
 132 static inline uint32_t mixer2flush(int lm)
 133 {
 134         switch (lm) {
 135         case 0:  return MDP5_CTL_FLUSH_LM0;
 136         case 1:  return MDP5_CTL_FLUSH_LM1;
 137         case 2:  return MDP5_CTL_FLUSH_LM2;
 138         default: return 0;
 139         }
 140 }
 141
 142 static inline uint32_t intf2err(int intf)
 143 {
 144         switch (intf) {
 145         case 0:  return MDP5_IRQ_INTF0_UNDER_RUN;
 146         case 1:  return MDP5_IRQ_INTF1_UNDER_RUN;
 147         case 2:  return MDP5_IRQ_INTF2_UNDER_RUN;
 148         case 3:  return MDP5_IRQ_INTF3_UNDER_RUN;
 149         default: return 0;
 150         }
 151 }
 152
 153 static inline uint32_t intf2vblank(int intf)
 154 {
 155         switch (intf) {
 156         case 0:  return MDP5_IRQ_INTF0_VSYNC;
 157         case 1:  return MDP5_IRQ_INTF1_VSYNC;
 158         case 2:  return MDP5_IRQ_INTF2_VSYNC;
 159         case 3:  return MDP5_IRQ_INTF3_VSYNC;
 160         default: return 0;
 161         }
 162 }
 163
 164 int mdp5_disable(struct mdp5_kms *mdp5_kms);
 165 int mdp5_enable(struct mdp5_kms *mdp5_kms);
 166
 167 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask);
 168 void mdp5_irq_preinstall(struct msm_kms *kms);
 169 int mdp5_irq_postinstall(struct msm_kms *kms);
 170 void mdp5_irq_uninstall(struct msm_kms *kms);
 171 irqreturn_t mdp5_irq(struct msm_kms *kms);
 172 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 173 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 174
 175 static inline
 176 uint32_t mdp5_get_formats(enum mdp5_pipe pipe, uint32_t *pixel_formats,
 177                 uint32_t max_formats)
 178 {
 179         /* TODO when we have YUV, we need to filter supported formats
 180          * based on pipe id..
 181          */
 182         return mdp_get_formats(pixel_formats, max_formats);
 183 }
 184
 185 void mdp5_plane_install_properties(struct drm_plane *plane,
 186                 struct drm_mode_object *obj);
 187 void mdp5_plane_set_scanout(struct drm_plane *plane,
 188                 struct drm_framebuffer *fb);
 189 int mdp5_plane_mode_set(struct drm_plane *plane,
 190                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
 191                 int crtc_x, int crtc_y,
 192                 unsigned int crtc_w, unsigned int crtc_h,
 193                 uint32_t src_x, uint32_t src_y,
 194                 uint32_t src_w, uint32_t src_h);
 195 void mdp5_plane_complete_flip(struct drm_plane *plane);
 196 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
 197 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
 198                 enum mdp5_pipe pipe, bool private_plane);
 199
 200 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
 201
 202 void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
 203 void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,
 204                 enum mdp5_intf intf_id);
 205 void mdp5_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane);
 206 void mdp5_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane);
 207 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
 208                 struct drm_plane *plane, int id);
 209
 210 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, int intf,
 211                 enum mdp5_intf intf_id);
 212
 213 #endif /* __MDP5_KMS_H__ */