2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/kernel.h>
22 #include <linux/clk.h>
23 #include <linux/cpufreq.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/slab.h>
29 #include <linux/list.h>
30 #include <linux/iommu.h>
31 #include <linux/types.h>
32 #include <asm/sizes.h>
35 #if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_ARCH_MSM)
36 /* stubs we need for compile-test: */
37 static inline struct device
*msm_iommu_get_ctx(const char *ctx_name
)
44 #include <mach/board.h>
45 #include <mach/socinfo.h>
46 #include <mach/iommu_domains.h>
50 #include <drm/drm_crtc_helper.h>
51 #include <drm/drm_fb_helper.h>
52 #include <drm/msm_drm.h>
57 #define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
59 struct msm_file_private
{
60 /* currently we don't do anything useful with this.. but when
61 * per-context address spaces are supported we'd keep track of
62 * the context's page-tables here.
67 struct msm_drm_private
{
71 /* when we have more than one 'msm_gpu' these need to be an array: */
73 struct msm_file_private
*lastctx
;
75 struct drm_fb_helper
*fbdev
;
77 uint32_t next_fence
, completed_fence
;
78 wait_queue_head_t fence_event
;
80 /* list of GEM objects: */
81 struct list_head inactive_list
;
83 struct workqueue_struct
*wq
;
85 /* callbacks deferred until bo is inactive: */
86 struct list_head fence_cbs
;
88 /* registered IOMMU domains: */
89 unsigned int num_iommus
;
90 struct iommu_domain
*iommus
[NUM_DOMAINS
];
92 unsigned int num_planes
;
93 struct drm_plane
*planes
[8];
95 unsigned int num_crtcs
;
96 struct drm_crtc
*crtcs
[8];
98 unsigned int num_encoders
;
99 struct drm_encoder
*encoders
[8];
101 unsigned int num_bridges
;
102 struct drm_bridge
*bridges
[8];
104 unsigned int num_connectors
;
105 struct drm_connector
*connectors
[8];
109 uint32_t pixel_format
;
112 /* callback from wq once fence has passed: */
113 struct msm_fence_cb
{
114 struct work_struct work
;
116 void (*func
)(struct msm_fence_cb
*cb
);
119 void __msm_fence_worker(struct work_struct
*work
);
121 #define INIT_FENCE_CB(_cb, _func) do { \
122 INIT_WORK(&(_cb)->work, __msm_fence_worker); \
123 (_cb)->func = _func; \
126 /* As there are different display controller blocks depending on the
127 * snapdragon version, the kms support is split out and the appropriate
128 * implementation is loaded at runtime. The kms module is responsible
129 * for constructing the appropriate planes/crtcs/encoders/connectors.
131 struct msm_kms_funcs
{
132 /* hw initialization: */
133 int (*hw_init
)(struct msm_kms
*kms
);
135 void (*irq_preinstall
)(struct msm_kms
*kms
);
136 int (*irq_postinstall
)(struct msm_kms
*kms
);
137 void (*irq_uninstall
)(struct msm_kms
*kms
);
138 irqreturn_t (*irq
)(struct msm_kms
*kms
);
139 int (*enable_vblank
)(struct msm_kms
*kms
, struct drm_crtc
*crtc
);
140 void (*disable_vblank
)(struct msm_kms
*kms
, struct drm_crtc
*crtc
);
142 const struct msm_format
*(*get_format
)(struct msm_kms
*kms
, uint32_t format
);
143 long (*round_pixclk
)(struct msm_kms
*kms
, unsigned long rate
,
144 struct drm_encoder
*encoder
);
146 void (*preclose
)(struct msm_kms
*kms
, struct drm_file
*file
);
147 void (*destroy
)(struct msm_kms
*kms
);
151 const struct msm_kms_funcs
*funcs
;
154 struct msm_kms
*mdp4_kms_init(struct drm_device
*dev
);
156 int msm_register_iommu(struct drm_device
*dev
, struct iommu_domain
*iommu
);
157 int msm_iommu_attach(struct drm_device
*dev
, struct iommu_domain
*iommu
,
158 const char **names
, int cnt
);
160 int msm_wait_fence_interruptable(struct drm_device
*dev
, uint32_t fence
,
161 struct timespec
*timeout
);
162 void msm_update_fence(struct drm_device
*dev
, uint32_t fence
);
164 int msm_ioctl_gem_submit(struct drm_device
*dev
, void *data
,
165 struct drm_file
*file
);
167 int msm_gem_mmap(struct file
*filp
, struct vm_area_struct
*vma
);
168 int msm_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
169 uint64_t msm_gem_mmap_offset(struct drm_gem_object
*obj
);
170 int msm_gem_get_iova_locked(struct drm_gem_object
*obj
, int id
,
172 int msm_gem_get_iova(struct drm_gem_object
*obj
, int id
, uint32_t *iova
);
173 struct page
**msm_gem_get_pages(struct drm_gem_object
*obj
);
174 void msm_gem_put_pages(struct drm_gem_object
*obj
);
175 void msm_gem_put_iova(struct drm_gem_object
*obj
, int id
);
176 int msm_gem_dumb_create(struct drm_file
*file
, struct drm_device
*dev
,
177 struct drm_mode_create_dumb
*args
);
178 int msm_gem_dumb_map_offset(struct drm_file
*file
, struct drm_device
*dev
,
179 uint32_t handle
, uint64_t *offset
);
180 struct sg_table
*msm_gem_prime_get_sg_table(struct drm_gem_object
*obj
);
181 void *msm_gem_prime_vmap(struct drm_gem_object
*obj
);
182 void msm_gem_prime_vunmap(struct drm_gem_object
*obj
, void *vaddr
);
183 struct drm_gem_object
*msm_gem_prime_import_sg_table(struct drm_device
*dev
,
184 size_t size
, struct sg_table
*sg
);
185 int msm_gem_prime_pin(struct drm_gem_object
*obj
);
186 void msm_gem_prime_unpin(struct drm_gem_object
*obj
);
187 void *msm_gem_vaddr_locked(struct drm_gem_object
*obj
);
188 void *msm_gem_vaddr(struct drm_gem_object
*obj
);
189 int msm_gem_queue_inactive_cb(struct drm_gem_object
*obj
,
190 struct msm_fence_cb
*cb
);
191 void msm_gem_move_to_active(struct drm_gem_object
*obj
,
192 struct msm_gpu
*gpu
, bool write
, uint32_t fence
);
193 void msm_gem_move_to_inactive(struct drm_gem_object
*obj
);
194 int msm_gem_cpu_prep(struct drm_gem_object
*obj
, uint32_t op
,
195 struct timespec
*timeout
);
196 int msm_gem_cpu_fini(struct drm_gem_object
*obj
);
197 void msm_gem_free_object(struct drm_gem_object
*obj
);
198 int msm_gem_new_handle(struct drm_device
*dev
, struct drm_file
*file
,
199 uint32_t size
, uint32_t flags
, uint32_t *handle
);
200 struct drm_gem_object
*msm_gem_new(struct drm_device
*dev
,
201 uint32_t size
, uint32_t flags
);
202 struct drm_gem_object
*msm_gem_import(struct drm_device
*dev
,
203 uint32_t size
, struct sg_table
*sgt
);
205 struct drm_gem_object
*msm_framebuffer_bo(struct drm_framebuffer
*fb
, int plane
);
206 const struct msm_format
*msm_framebuffer_format(struct drm_framebuffer
*fb
);
207 struct drm_framebuffer
*msm_framebuffer_init(struct drm_device
*dev
,
208 struct drm_mode_fb_cmd2
*mode_cmd
, struct drm_gem_object
**bos
);
209 struct drm_framebuffer
*msm_framebuffer_create(struct drm_device
*dev
,
210 struct drm_file
*file
, struct drm_mode_fb_cmd2
*mode_cmd
);
212 struct drm_fb_helper
*msm_fbdev_init(struct drm_device
*dev
);
214 int hdmi_init(struct drm_device
*dev
, struct drm_encoder
*encoder
);
215 void __init
hdmi_register(void);
216 void __exit
hdmi_unregister(void);
218 #ifdef CONFIG_DEBUG_FS
219 void msm_gem_describe(struct drm_gem_object
*obj
, struct seq_file
*m
);
220 void msm_gem_describe_objects(struct list_head
*list
, struct seq_file
*m
);
221 void msm_framebuffer_describe(struct drm_framebuffer
*fb
, struct seq_file
*m
);
224 void __iomem
*msm_ioremap(struct platform_device
*pdev
, const char *name
,
225 const char *dbgname
);
226 void msm_writel(u32 data
, void __iomem
*addr
);
227 u32
msm_readl(const void __iomem
*addr
);
229 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
230 #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
232 static inline bool fence_completed(struct drm_device
*dev
, uint32_t fence
)
234 struct msm_drm_private
*priv
= dev
->dev_private
;
235 return priv
->completed_fence
>= fence
;
238 static inline int align_pitch(int width
, int bpp
)
240 int bytespp
= (bpp
+ 7) / 8;
241 /* adreno needs pitch aligned to 32 pixels: */
242 return bytespp
* ALIGN(width
, 32);
245 /* for the generated headers: */
246 #define INVALID_IDX(idx) ({BUG(); 0;})
247 #define fui(x) ({BUG(); 0;})
248 #define util_float_to_half(x) ({BUG(); 0;})
251 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
253 /* for conditionally setting boolean flag(s): */
254 #define COND(bool, val) ((bool) ? (val) : 0)
257 #endif /* __MSM_DRV_H__ */