drivers/gpu/drm/nouveau/core/engine/copy/nva3.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/os.h>
  26 #include <core/enum.h>
  27 #include <core/class.h>
  28 #include <core/engctx.h>
  29
  30 #include <subdev/fb.h>
  31 #include <subdev/vm.h>
  32
  33 #include <engine/copy.h>
  34
  35 #include "fuc/nva3.fuc.h"
  36
  37 struct nva3_copy_priv {
  38         struct nouveau_copy base;
  39 };
  40
  41 struct nva3_copy_chan {
  42         struct nouveau_copy_chan base;
  43 };
  44
  45 /*******************************************************************************
  46  * Copy object classes
  47  ******************************************************************************/
  48
  49 static struct nouveau_oclass
  50 nva3_copy_sclass[] = {
  51         { 0x85b5, &nouveau_object_ofuncs },
  52         {}
  53 };
  54
  55 /*******************************************************************************
  56  * PCOPY context
  57  ******************************************************************************/
  58
  59 static int
  60 nva3_copy_context_ctor(struct nouveau_object *parent,
  61                        struct nouveau_object *engine,
  62                        struct nouveau_oclass *oclass, void *data, u32 size,
  63                        struct nouveau_object **pobject)
  64 {
  65         struct nva3_copy_chan *priv;
  66         int ret;
  67
  68         ret = nouveau_copy_context_create(parent, engine, oclass, NULL, 256, 0,
  69                                           NVOBJ_FLAG_ZERO_ALLOC, &priv);
  70         *pobject = nv_object(priv);
  71         if (ret)
  72                 return ret;
  73
  74         return 0;
  75 }
  76
  77 static struct nouveau_oclass
  78 nva3_copy_cclass = {
  79         .handle = NV_ENGCTX(COPY0, 0xa3),
  80         .ofuncs = &(struct nouveau_ofuncs) {
  81                 .ctor = nva3_copy_context_ctor,
  82                 .dtor = _nouveau_copy_context_dtor,
  83                 .init = _nouveau_copy_context_init,
  84                 .fini = _nouveau_copy_context_fini,
  85                 .rd32 = _nouveau_copy_context_rd32,
  86                 .wr32 = _nouveau_copy_context_wr32,
  87
  88         },
  89 };
  90
  91 /*******************************************************************************
  92  * PCOPY engine/subdev functions
  93  ******************************************************************************/
  94
  95 static struct nouveau_enum nva3_copy_isr_error_name[] = {
  96         { 0x0001, "ILLEGAL_MTHD" },
  97         { 0x0002, "INVALID_ENUM" },
  98         { 0x0003, "INVALID_BITFIELD" },
  99         {}
 100 };
 101
 102 static void
 103 nva3_copy_intr(struct nouveau_subdev *subdev)
 104 {
 105         struct nva3_copy_priv *priv = (void *)subdev;
 106         u32 dispatch = nv_rd32(priv, 0x10401c);
 107         u32 stat = nv_rd32(priv, 0x104008) & dispatch & ~(dispatch >> 16);
 108         u32 inst = nv_rd32(priv, 0x104050) & 0x3fffffff;
 109         u32 ssta = nv_rd32(priv, 0x104040) & 0x0000ffff;
 110         u32 addr = nv_rd32(priv, 0x104040) >> 16;
 111         u32 mthd = (addr & 0x07ff) << 2;
 112         u32 subc = (addr & 0x3800) >> 11;
 113         u32 data = nv_rd32(priv, 0x104044);
 114
 115         if (stat & 0x00000040) {
 116                 nv_error(priv, "DISPATCH_ERROR [");
 117                 nouveau_enum_print(nva3_copy_isr_error_name, ssta);
 118                 printk("] ch 0x%08x subc %d mthd 0x%04x data 0x%08x\n",
 119                        inst, subc, mthd, data);
 120                 nv_wr32(priv, 0x104004, 0x00000040);
 121                 stat &= ~0x00000040;
 122         }
 123
 124         if (stat) {
 125                 nv_error(priv, "unhandled intr 0x%08x\n", stat);
 126                 nv_wr32(priv, 0x104004, stat);
 127         }
 128
 129         nv50_fb_trap(nouveau_fb(priv), 1);
 130 }
 131
 132 static int
 133 nva3_copy_tlb_flush(struct nouveau_engine *engine)
 134 {
 135         nv50_vm_flush_engine(&engine->base, 0x0d);
 136         return 0;
 137 }
 138
 139 static int
 140 nva3_copy_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 141                struct nouveau_oclass *oclass, void *data, u32 size,
 142                struct nouveau_object **pobject)
 143 {
 144         bool enable = (nv_device(parent)->chipset != 0xaf);
 145         struct nva3_copy_priv *priv;
 146         int ret;
 147
 148         ret = nouveau_copy_create(parent, engine, oclass, enable, 0, &priv);
 149         *pobject = nv_object(priv);
 150         if (ret)
 151                 return ret;
 152
 153         nv_subdev(priv)->unit = 0x00802000;
 154         nv_subdev(priv)->intr = nva3_copy_intr;
 155         nv_engine(priv)->cclass = &nva3_copy_cclass;
 156         nv_engine(priv)->sclass = nva3_copy_sclass;
 157         nv_engine(priv)->tlb_flush = nva3_copy_tlb_flush;
 158         return 0;
 159 }
 160
 161 static int
 162 nva3_copy_init(struct nouveau_object *object)
 163 {
 164         struct nva3_copy_priv *priv = (void *)object;
 165         int ret, i;
 166
 167         ret = nouveau_copy_init(&priv->base);
 168         if (ret)
 169                 return ret;
 170
 171         /* disable all interrupts */
 172         nv_wr32(priv, 0x104014, 0xffffffff);
 173
 174         /* upload ucode */
 175         nv_wr32(priv, 0x1041c0, 0x01000000);
 176         for (i = 0; i < sizeof(nva3_pcopy_data) / 4; i++)
 177                 nv_wr32(priv, 0x1041c4, nva3_pcopy_data[i]);
 178
 179         nv_wr32(priv, 0x104180, 0x01000000);
 180         for (i = 0; i < sizeof(nva3_pcopy_code) / 4; i++) {
 181                 if ((i & 0x3f) == 0)
 182                         nv_wr32(priv, 0x104188, i >> 6);
 183                 nv_wr32(priv, 0x104184, nva3_pcopy_code[i]);
 184         }
 185
 186         /* start it running */
 187         nv_wr32(priv, 0x10410c, 0x00000000);
 188         nv_wr32(priv, 0x104104, 0x00000000); /* ENTRY */
 189         nv_wr32(priv, 0x104100, 0x00000002); /* TRIGGER */
 190         return 0;
 191 }
 192
 193 static int
 194 nva3_copy_fini(struct nouveau_object *object, bool suspend)
 195 {
 196         struct nva3_copy_priv *priv = (void *)object;
 197
 198         nv_mask(priv, 0x104048, 0x00000003, 0x00000000);
 199         nv_wr32(priv, 0x104014, 0xffffffff);
 200
 201         return nouveau_copy_fini(&priv->base, suspend);
 202 }
 203
 204 struct nouveau_oclass
 205 nva3_copy_oclass = {
 206         .handle = NV_ENGINE(COPY0, 0xa3),
 207         .ofuncs = &(struct nouveau_ofuncs) {
 208                 .ctor = nva3_copy_ctor,
 209                 .dtor = _nouveau_copy_dtor,
 210                 .init = nva3_copy_init,
 211                 .fini = nva3_copy_fini,
 212         },
 213 };