drivers/gpu/drm/nouveau/core/engine/disp/nv94.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <engine/software.h>
  26 #include <engine/disp.h>
  27
  28 #include <core/class.h>
  29
  30 #include "nv50.h"
  31
  32 /*******************************************************************************
  33  * EVO master channel object
  34  ******************************************************************************/
  35
  36 const struct nv50_disp_mthd_list
  37 nv94_disp_mast_mthd_sor = {
  38         .mthd = 0x0040,
  39         .addr = 0x000008,
  40         .data = {
  41                 { 0x0600, 0x610794 },
  42                 {}
  43         }
  44 };
  45
  46 const struct nv50_disp_mthd_chan
  47 nv94_disp_mast_mthd_chan = {
  48         .name = "Core",
  49         .addr = 0x000000,
  50         .data = {
  51                 { "Global", 1, &nv50_disp_mast_mthd_base },
  52                 {    "DAC", 3, &nv84_disp_mast_mthd_dac  },
  53                 {    "SOR", 4, &nv94_disp_mast_mthd_sor  },
  54                 {   "PIOR", 3, &nv50_disp_mast_mthd_pior },
  55                 {   "HEAD", 2, &nv84_disp_mast_mthd_head },
  56                 {}
  57         }
  58 };
  59
  60 /*******************************************************************************
  61  * Base display object
  62  ******************************************************************************/
  63
  64 static struct nouveau_oclass
  65 nv94_disp_sclass[] = {
  66         { NV94_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
  67         { NV94_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
  68         { NV94_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
  69         { NV94_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
  70         { NV94_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
  71         {}
  72 };
  73
  74 static struct nouveau_omthds
  75 nv94_disp_base_omthds[] = {
  76         { HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },
  77         { SOR_MTHD(NV50_DISP_SOR_PWR)         , nv50_sor_mthd },
  78         { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR)    , nv50_sor_mthd },
  79         { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
  80         { DAC_MTHD(NV50_DISP_DAC_PWR)         , nv50_dac_mthd },
  81         { DAC_MTHD(NV50_DISP_DAC_LOAD)        , nv50_dac_mthd },
  82         { PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },
  83         { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },
  84         { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },
  85         {},
  86 };
  87
  88 static struct nouveau_oclass
  89 nv94_disp_base_oclass[] = {
  90         { NV94_DISP_CLASS, &nv50_disp_base_ofuncs, nv94_disp_base_omthds },
  91         {}
  92 };
  93
  94 /*******************************************************************************
  95  * Display engine implementation
  96  ******************************************************************************/
  97
  98 static int
  99 nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 100                struct nouveau_oclass *oclass, void *data, u32 size,
 101                struct nouveau_object **pobject)
 102 {
 103         struct nv50_disp_priv *priv;
 104         int ret;
 105
 106         ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
 107                                   "display", &priv);
 108         *pobject = nv_object(priv);
 109         if (ret)
 110                 return ret;
 111
 112         nv_engine(priv)->sclass = nv94_disp_base_oclass;
 113         nv_engine(priv)->cclass = &nv50_disp_cclass;
 114         nv_subdev(priv)->intr = nv50_disp_intr;
 115         INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
 116         priv->sclass = nv94_disp_sclass;
 117         priv->head.nr = 2;
 118         priv->dac.nr = 3;
 119         priv->sor.nr = 4;
 120         priv->pior.nr = 3;
 121         priv->dac.power = nv50_dac_power;
 122         priv->dac.sense = nv50_dac_sense;
 123         priv->sor.power = nv50_sor_power;
 124         priv->sor.hdmi = nv84_hdmi_ctrl;
 125         priv->sor.dp = &nv94_sor_dp_func;
 126         priv->pior.power = nv50_pior_power;
 127         priv->pior.dp = &nv50_pior_dp_func;
 128         return 0;
 129 }
 130
 131 struct nouveau_oclass *
 132 nv94_disp_oclass = &(struct nv50_disp_impl) {
 133         .base.base.handle = NV_ENGINE(DISP, 0x88),
 134         .base.base.ofuncs = &(struct nouveau_ofuncs) {
 135                 .ctor = nv94_disp_ctor,
 136                 .dtor = _nouveau_disp_dtor,
 137                 .init = _nouveau_disp_init,
 138                 .fini = _nouveau_disp_fini,
 139         },
 140         .mthd.core = &nv94_disp_mast_mthd_chan,
 141         .mthd.base = &nv84_disp_sync_mthd_chan,
 142         .mthd.ovly = &nv84_disp_ovly_mthd_chan,
 143         .mthd.prev = 0x000004,
 144 }.base.base;