drivers/gpu/drm/nouveau/core/engine/disp/nva3.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <engine/software.h>
  26 #include <engine/disp.h>
  27
  28 #include <core/class.h>
  29
  30 #include "nv50.h"
  31
  32 /*******************************************************************************
  33  * Base display object
  34  ******************************************************************************/
  35
  36 static struct nouveau_oclass
  37 nva3_disp_sclass[] = {
  38         { NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
  39         { NVA3_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
  40         { NVA3_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
  41         { NVA3_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
  42         { NVA3_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
  43         {}
  44 };
  45
  46 static struct nouveau_omthds
  47 nva3_disp_base_omthds[] = {
  48         { HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },
  49         { SOR_MTHD(NV50_DISP_SOR_PWR)         , nv50_sor_mthd },
  50         { SOR_MTHD(NVA3_DISP_SOR_HDA_ELD)     , nv50_sor_mthd },
  51         { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR)    , nv50_sor_mthd },
  52         { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
  53         { DAC_MTHD(NV50_DISP_DAC_PWR)         , nv50_dac_mthd },
  54         { DAC_MTHD(NV50_DISP_DAC_LOAD)        , nv50_dac_mthd },
  55         { PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },
  56         { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },
  57         { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },
  58         {},
  59 };
  60
  61 static struct nouveau_oclass
  62 nva3_disp_base_oclass[] = {
  63         { NVA3_DISP_CLASS, &nv50_disp_base_ofuncs, nva3_disp_base_omthds },
  64         {}
  65 };
  66
  67 /*******************************************************************************
  68  * Display engine implementation
  69  ******************************************************************************/
  70
  71 static int
  72 nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
  73                struct nouveau_oclass *oclass, void *data, u32 size,
  74                struct nouveau_object **pobject)
  75 {
  76         struct nv50_disp_priv *priv;
  77         int ret;
  78
  79         ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
  80                                   "display", &priv);
  81         *pobject = nv_object(priv);
  82         if (ret)
  83                 return ret;
  84
  85         nv_engine(priv)->sclass = nva3_disp_base_oclass;
  86         nv_engine(priv)->cclass = &nv50_disp_cclass;
  87         nv_subdev(priv)->intr = nv50_disp_intr;
  88         INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
  89         priv->sclass = nva3_disp_sclass;
  90         priv->head.nr = 2;
  91         priv->dac.nr = 3;
  92         priv->sor.nr = 4;
  93         priv->pior.nr = 3;
  94         priv->dac.power = nv50_dac_power;
  95         priv->dac.sense = nv50_dac_sense;
  96         priv->sor.power = nv50_sor_power;
  97         priv->sor.hda_eld = nva3_hda_eld;
  98         priv->sor.hdmi = nva3_hdmi_ctrl;
  99         priv->sor.dp = &nv94_sor_dp_func;
 100         priv->pior.power = nv50_pior_power;
 101         priv->pior.dp = &nv50_pior_dp_func;
 102         return 0;
 103 }
 104
 105 struct nouveau_oclass *
 106 nva3_disp_oclass = &(struct nv50_disp_impl) {
 107         .base.base.handle = NV_ENGINE(DISP, 0x85),
 108         .base.base.ofuncs = &(struct nouveau_ofuncs) {
 109                 .ctor = nva3_disp_ctor,
 110                 .dtor = _nouveau_disp_dtor,
 111                 .init = _nouveau_disp_init,
 112                 .fini = _nouveau_disp_fini,
 113         },
 114         .base.outp =  nv94_disp_outp_sclass,
 115         .mthd.core = &nv94_disp_mast_mthd_chan,
 116         .mthd.base = &nv84_disp_sync_mthd_chan,
 117         .mthd.ovly = &nv84_disp_ovly_mthd_chan,
 118         .mthd.prev = 0x000004,
 119 }.base.base;