drivers/gpu/drm/nouveau/core/engine/disp/nve0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <engine/software.h>
  26 #include <engine/disp.h>
  27
  28 #include <core/class.h>
  29
  30 #include "nv50.h"
  31
  32 static struct nouveau_oclass
  33 nve0_disp_sclass[] = {
  34         { NVE0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs },
  35         { NVE0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs },
  36         { NVE0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs },
  37         { NVE0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs },
  38         { NVE0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs },
  39         {}
  40 };
  41
  42 static struct nouveau_oclass
  43 nve0_disp_base_oclass[] = {
  44         { NVE0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds },
  45         {}
  46 };
  47
  48 static int
  49 nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
  50                struct nouveau_oclass *oclass, void *data, u32 size,
  51                struct nouveau_object **pobject)
  52 {
  53         struct nv50_disp_priv *priv;
  54         int ret;
  55
  56         ret = nouveau_disp_create(parent, engine, oclass, "PDISP",
  57                                   "display", &priv);
  58         *pobject = nv_object(priv);
  59         if (ret)
  60                 return ret;
  61
  62         nv_engine(priv)->sclass = nve0_disp_base_oclass;
  63         nv_engine(priv)->cclass = &nv50_disp_cclass;
  64         nv_subdev(priv)->intr = nvd0_disp_intr;
  65         priv->sclass = nve0_disp_sclass;
  66         priv->head.nr = nv_rd32(priv, 0x022448);
  67         priv->dac.nr = 3;
  68         priv->sor.nr = 4;
  69         priv->dac.power = nv50_dac_power;
  70         priv->dac.sense = nv50_dac_sense;
  71         priv->sor.power = nv50_sor_power;
  72         priv->sor.hda_eld = nvd0_hda_eld;
  73         priv->sor.dp_train = nvd0_sor_dp_train;
  74         priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl;
  75         priv->sor.dp_drvctl = nvd0_sor_dp_drvctl;
  76
  77         INIT_LIST_HEAD(&priv->base.vblank.list);
  78         spin_lock_init(&priv->base.vblank.lock);
  79         return 0;
  80 }
  81
  82 struct nouveau_oclass
  83 nve0_disp_oclass = {
  84         .handle = NV_ENGINE(DISP, 0x91),
  85         .ofuncs = &(struct nouveau_ofuncs) {
  86                 .ctor = nve0_disp_ctor,
  87                 .dtor = _nouveau_disp_dtor,
  88                 .init = _nouveau_disp_init,
  89                 .fini = _nouveau_disp_fini,
  90         },
  91 };